A fully superconducting TSV interposer structure and method of manufacture

Abstract

The application relates to a full-superconducting TSV adapter plate structure and a manufacturing method. The manufacturing method comprises the following steps: (1) selecting a superconducting carrier wafer and performing mechanical processing; (2) attaching a high-temperature-resistant film on one side of the wafer flat surface and performing plastic packaging; (3) grinding the front surface of the wafer to form a TSV column+line structure and performing cleaning; (4) forming a pattern layer of an insulating layer on the front surface of the wafer and performing photoetching; (5) forming a metal connecting line on the wafer; (6) repeating steps (4)-(5) on the front surface of the wafer; (7) repeating steps (4)-(5) on the back surface of the wafer; (8) using a superconducting ball to perform ball mounting on the chip Pad position corresponding to the wafer; and (9) attaching a chip. The adapter plate uses full-superconducting materials as packaging electric connection materials, can realize the low-delay requirement of quantum communication and supercomputing, and has simple manufacturing process and low cost, and can solve the disadvantage that a multi-element alloy superconducting material cannot form an electric connection line in an electroplating mode.

Description

Technical Field

[0001] This invention belongs to the field of adapter plate technology, and specifically relates to a fully superconducting TSV adapter plate structure and manufacturing method. Background Technology

[0002] Current adapter board products mostly use silicon as the substrate and metal pillars as the connecting lines between the front and back sides. The connecting material is only copper. Before forming the copper pillars, an insulating layer, a barrier layer, and a conductive layer need to be formed on the hole walls. After the metal pillars are deposited, the surface metal layer needs to be removed using CMP (chemical mechanical polishing) to remove the barrier layer and electroplat the metal layer. The entire process is complex and the equipment is expensive. Not only is the manufacturing process complex and costly, but it also cannot meet the zero-resistance requirements of current quantum computing and quantum communication.

[0003] The detailed manufacturing process is as follows:

[0004] 1. Select and use high-resistivity silicon wafers, generally those with a resistance greater than 2MΩ, such as... Figure 1 As shown;

[0005] 2. Photoresist coating: Photoresist is applied to the Si substrate using a spray coating method. A certain thickness of photoresist is applied to serve as a barrier layer during dry etching. Figure 2 As shown;

[0006] 3. Exposure: Using an exposure machine, the areas to be etched on the photoresist-coated Si carrier wafer are exposed or shielded as required (a corresponding mask is created depending on the chosen photoresist). Here, positive photoresist is used; the areas to be etched are exposed, such as... Figure 3 As shown;

[0007] 4. Development: Using a specific chemical solution, the photoresist in the areas to be etched is removed through a chemical reaction, forming a specific pattern, such as... Figure 4 As shown.

[0008] 5. Dry etching: Using a vacuum etching machine, special gases are used to etch silicon to the required depth while maintaining no significant change in the opening. Figure 5 As shown;

[0009] 6. Wet photoresist removal: Residual photoresist on the silicon surface is removed using a wet process, typically through a chemical reaction. Figure 6 As shown;

[0010] 7. Passivation layer deposition: Since silicon is a semiconductor, it cannot directly contact the subsequently deposited metal. Therefore, an insulating layer needs to be deposited. Currently, the common method is PECVD (Plasma-Enhanced Chemical Vapor Deposition). This method is not only expensive but also requires specialized, highly toxic gases. Furthermore, the film's tendency to absorb water affects its insulating properties. Figure 7 As shown;

[0011] 8. Deposition of barrier and conductive layers: PVD (Physical Vapor Deposition) is used to deposit barrier and conductive layers. However, this method involves expensive equipment and results in poor deposition thickness and uniformity on the sidewalls, especially the bottom sidewalls. Figure 8 As shown;

[0012] 9. Metal deposition, using a wafer as the cathode for electroplating, completes the filling of the vias and the growth of planar metal, such as... Figure 9 As shown;

[0013] 10. Annealing + CMP: Stress relief is performed on the wafer under high temperature conditions, followed by removal of the outermost conductive metal layer and barrier layer, such as... Figure 10 As shown; when stress is released, the grains of the metal grow synchronously and non-uniformly in all directions. Due to the relatively low strength of silicon, this is insufficient.

[0014] To overcome stress variations, silicon wafers often develop microcracks or fragments, posing significant risks to subsequent processes and equipment. The CMP process is also quite complex, requiring uniform and clean removal of the conductive metal layer before the barrier layer can be removed. Different chemicals are used for each layer, necessitating the use of different chambers, resulting in expensive equipment hardware, often costing tens of millions of RMB.

[0015] 11. Front-side routing: RDL routing is performed on the front side using a bumping process, such as... Figure 11 As shown;

[0016] 12. Backside exposure: After bonding a substrate to the front side, the silicon is first thinned to a certain thickness, exceeding the thickness of the TSV vias, using a backside thinning process. Then, dry etching is used to thin the silicon until the TSV vias are exposed. To prevent metal diffusion during subsequent CMP exposure from affecting the silicon impedance, thin film deposition is required. Next, CMP is used to remove the oxide layer at the bottom of the TSV vias. Finally, CMP is used to remove the barrier layer, such as... Figure 12 As shown;

[0017] 13. Backside wiring and C4 bump growth: After bonding, backside exposure, and a series of photolithography and electroplating processes to form the RDL conductive layer and C4 bumps on the backside, the final product is formed, and the front-side substrate is removed. Figure 13 As shown. Summary of the Invention

[0018] The technical problem to be solved by the present invention is to provide a fully superconducting TSV adapter plate structure and manufacturing method to overcome the shortcomings of the prior art, such as complex manufacturing process, high process cost, and inability to meet the current requirements of quantum computing and quantum communication for zero resistance.

[0019] This invention provides a method for manufacturing a fully superconducting TSV adapter plate, comprising:

[0020] (1) Select a superconducting carrier wafer; perform mechanical processing on the superconducting carrier wafer to form multiple pillars of different diameters on the processing surface of the wafer, with connecting lines between the pillars and a supporting frame around the pillars, the frame being connected to the pillars by a bracket;

[0021] (2) Apply a high-temperature resistant film to one side of the flat surface of the wafer (this film is used for molding and molding); then mold it, and after molding, make the molded surface flush with the surface of the pillar, and then remove the film on the wafer;

[0022] (3) Grind the front side of the wafer in step (2) until the border described in step (1) is removed to form a TSV pillar + line structure, and clean it (the purpose is to remove metal contaminants and organic impurities).

[0023] (4) A patterned insulating layer is formed on the front side of the wafer obtained in step (3), the pattern is photolithographically etched, and photoresist is fabricated on the wafer with the above structure (the photoresist can be removed by a stripper in the future).

[0024] (5) A metallized wiring layer is formed on the wafer obtained in step (4), and the photoresist and the metal layer on the photoresist are removed together to form a metal interconnect.

[0025] (6) Repeat steps (4)-(5) on the front side of the wafer obtained in step (5);

[0026] (7) Repeat steps (4)-(5) on the back side of the wafer obtained in step (6);

[0027] (8) Using superconducting spheres, spheres are implanted at the chip pad positions corresponding to the above wafers;

[0028] (9) Attach the chip.

[0029] Preferably, the superconducting metal used in step (1) is a single-element or multi-element alloy material.

[0030] Preferably, the machining in step (1) includes machining or laser processing.

[0031] Preferably, the column shape in step (1) includes: a cylinder, a cone, or an octagonal body.

[0032] Preferably, in step (1), the diameter of the column is 10 to 100 μm and the height is 50 to 500 μm.

[0033] Preferably, in step (1), the height of the connecting line is lower than that of the column; and the thickness of the frame is less than 50 μm.

[0034] Preferably, the height of the connecting line is 30-50 μm lower than the height of the column.

[0035] Preferably, in step (2), the diameter of the high-temperature resistant film is 1-3 mm larger than the diameter of the wafer.

[0036] Preferably, the process of forming the patterned layer of the insulating layer in step (4) includes: using Bumping lithography technology and using the process steps of coating, exposure, development and curing.

[0037] Preferably, the method for forming the metallized wiring layer in step (5) is to use a PVD or vapor deposition machine.

[0038] Preferably, in step (5), the photoresist and the metal layer on the photoresist are removed together by using a photoresist remover and lifting off.

[0039] Preferably, in step (8), the superconducting sphere is mainly composed of superconducting particles and supplemented by tin solder; the superconducting sphere has both solderability and high-temperature superconductivity.

[0040] Preferably, different functions and quantities of superconducting chips are attached according to functional requirements.

[0041] The present invention also provides a fully superconducting TSV adapter plate prepared by the above-described manufacturing method.

[0042] The present invention also provides an application of the above-mentioned fully superconducting TSV adapter in super quantum computing and quantum communication.

[0043] This invention relates to a TSV post + line structure, where the TSV serves as a vertically conductive electrical connection line, and the line serves as an electrical connection line between different posts. Posts that need to be connected are connected together at this point, eliminating the need for subsequent rewiring processes. Figure 19 As shown.

[0044] Beneficial effects

[0045] This invention uses superconducting materials as the electrical interconnects throughout, enabling faster connections, shorter latency, and lower energy consumption for quantum communication and supercomputing. The superconducting material serves as the vertical interconnect, enhancing electrical connectivity. Simultaneously, using molding compound as the substrate overcomes the processing difficulties of silicon-based materials and improves insulation performance. Furthermore, the fabrication process is simple and inexpensive, overcoming the limitation of using electroplating to form electrical interconnects with multi-element alloy superconducting materials. The structure of this invention uses the simplest machining process to replace the complex metal wiring process requiring photolithography + electroplating + wet etching, and the complex TSV pillar formation process requiring photolithography + dry etching + metal filling + CMP outcrops in a single step. Attached Figure Description

[0046] Figure 1 A schematic diagram illustrating the selection of silicon wafers for existing adapter board products;

[0047] Figure 2 A schematic diagram of the structure of the barrier layer formed by applying adhesive during the manufacturing process of existing adapter plate products;

[0048] Figure 3 This is a schematic diagram of the structure of an existing adapter plate product after exposure during the manufacturing process.

[0049] Figure 4 This is a schematic diagram of the structure formed by development during the manufacturing process of existing adapter plate products;

[0050] Figure 5 This is a schematic diagram of the structure after etching during the manufacturing process of an existing adapter board product.

[0051] Figure 6 This is a schematic diagram of the structure after wet adhesive removal during the manufacturing process of existing adapter plate products.

[0052] Figure 7 This is a schematic diagram of the structure of the passivation layer deposited during the manufacturing process of existing adapter plate products.

[0053] Figure 8 This is a schematic diagram of the structure of the barrier layer and conductive layer deposited during the manufacturing process of existing adapter plate products;

[0054] Figure 9 This is a schematic diagram of the structure of the deposited metal during the manufacturing process of existing adapter plate products.

[0055] Figure 10 A schematic diagram of the structure for removing the conductive metal layer and barrier layer during the manufacturing process of existing adapter board products using annealing + CMP.

[0056] Figure 11 This is a schematic diagram of the front wiring structure during the manufacturing process of an existing adapter board product.

[0057] Figure 12 This is a schematic diagram of the structure of an existing adapter board product after sequential back-side thinning, dry etching, thin film deposition, oxide layer CMP, and barrier layer CMP during the manufacturing process.

[0058] Figure 13 A schematic diagram of the back-side wiring and C4 bump growth process in the manufacturing process of existing adapter board products;

[0059] Figure 14 This is a schematic diagram of the structure of the superconducting carrier wafer selected for this invention;

[0060] Figure 15This is a schematic diagram of the structure of the superconducting carrier wafer after mechanical processing according to the present invention, where 1 is a connecting line, 2 is a cylinder, 3 is a support, and 4 is a frame.

[0061] Figure 16 This is a schematic diagram of the structure of applying a high-temperature resistant film to the wafer before molding and encapsulation according to the present invention;

[0062] Figure 17 This is a schematic diagram of the wafer after molding and encapsulation according to the present invention;

[0063] Figure 18 This is a schematic diagram of the structure for removing the adhesive film on the wafer according to the present invention;

[0064] Figure 19 This is a schematic diagram of the wafer after mechanical polishing and a schematic diagram of the TSV pillar + circuit structure of the present invention;

[0065] Figure 20 This is a schematic diagram of the structure of the insulating layer formed on the wafer of the present invention;

[0066] Figure 21 This is a schematic diagram of the photolithographic pattern on the wafer of the present invention;

[0067] Figure 22 This is a schematic diagram of the structure of the metallized wiring layer formed on the wafer of the present invention;

[0068] Figure 23 This is a schematic diagram of the structure of forming metal interconnects on a wafer by removing photoresist and metal from the photoresist in this invention.

[0069] Figure 24 This is a schematic diagram of the structure of the wafer after the second insulating layer and wiring layer are formed on the front side and the adhesive is removed.

[0070] Figure 25 This is a schematic diagram of the structure of forming an insulating layer and a wiring layer on the back side of a wafer and then removing the adhesive to form metal interconnects according to the present invention.

[0071] Figure 26 This is a schematic diagram of the structure after superconducting balls are used to attach to the wafer pad position in this invention;

[0072] Figure 27 This is a schematic diagram of the structure of the wafer after the superconducting chip is attached. Detailed Implementation

[0073] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0074] Example 1

[0075] This embodiment provides a method for manufacturing a fully superconducting TSV adapter plate, including:

[0076] (1) Select a superconducting carrier wafer with a certain thickness, generally between 50 and 500 μm (optimal 100 μm). The superconducting metal can be an element or a multi-element alloy (such as niobium, niobium-aluminum, niobium-tin alloys, etc.). Figure 14 As shown;

[0077] (2) Machining: The prepared superconducting wafer is physically processed using methods such as machining or laser processing to create a wafer pattern with the following structure. Below are cross-sectional views of a single chip (the processed surface of the wafer forms multiple pillars of different diameters and shapes (cylinders, cones, or octagonal bodies, etc.) with the same height (generally 10 to 100 μm in diameter and 50 to 500 μm in height (the final structural diameter of 10 μm and thickness of 100 μm is selected based on the performance of the actual package simulation). Connecting lines are provided between the pillars, and the height of the connecting lines is lower than that of the pillars (width is not limited, height is 30-50 μm lower than the height of the pillars (thickness is selected based on the performance of the actual package electrical and thermal simulation)). The frame thickness is the thinnest to facilitate subsequent grinding and removal (preferably less than 50 μm, generally 30 μm); the top view shows a frame around the perimeter, with supports connecting the pillars to the frame, such as... Figure 15 As shown;

[0078] (3) Preparation before wafer molding: Using a laminator, apply a high-temperature resistant film to the flat side of the wafer as shown in the diagram below. This film serves as the substrate for molding and supports the wafer during molding. The film diameter should be slightly larger than the wafer by 1-3 mm (this can be selected based on the actual machine tool dimensions, but 1 mm is preferable). Figure 16 As shown;

[0079] (4) Molding: Mold the wafer to a suitable thickness as required, ensuring the molded surface is flush with the pillar surface. Figure 17 As shown;

[0080] (5) Remove the adhesive film. Use a film peeler to remove the adhesive film from the wafer, such as... Figure 18 As shown;

[0081] (6) Mechanical grinding: Use a grinding wheel to grind the front side from step 5 until the frame mentioned in step 2 is removed, forming a TSV pillar + circuit structure. Then, perform a certain amount of cleaning to remove metal contaminants and organic impurities, such as... Figure 19 As shown;

[0082] (7) The front insulating layer is generally made of polyimide. Using bumping lithography, a patterned insulating layer is formed on the front side as shown in the figure below, following a process of coating, exposure, development, and curing. Figure 20 As shown;

[0083] (8) Photolithography patterning: A photoresist is then fabricated on the wafer with the above-described structure. This photoresist can be removed subsequently using a resist remover, such as... Figure 21 As shown;

[0084] (9) Metallization of the wiring layer: A metallized wiring layer is formed on the wafer using PVD or evaporation equipment. The material is a superconducting material such as niobium or niobium compounds. Figure 22 As shown;

[0085] (10) Resin removal: Using a resist remover and a lift-off method, the photoresist and the metal layer on it are removed together to form the required metal interconnects, such as... Figure 23 As shown;

[0086] (11) For the second insulating layer and wiring layer, repeat steps 7 to 10 to form the following: Figure 24 The structure shown;

[0087] (12) Fabrication of the back insulation layer and wiring layer, repeating steps 7 to 10, to form as shown. Figure 25 The structure shown;

[0088] (13) Chip link point fabrication: Balls are placed at the corresponding chip pad positions on the wafer using a ball-mounting method. Superconducting balls are used, primarily composed of superconducting particles (niobium or niobium compounds, etc.) and supplemented with solder (e.g., Figure 26 (as shown in the diagram), which also has weldability and high-temperature superconductivity;

[0089] (14) Chip mounting: After cutting the above wafer into individual packages, different functions and quantities of superconducting chips can be mounted on it according to functional requirements to form, such as... Figure 27 The structure shown.

Claims

1. A method for manufacturing a fully superconducting TSV adapter plate, comprising: (1) Select a superconducting carrier wafer; The superconducting carrier wafer is mechanically processed to form multiple pillars of different diameters on the processed surface of the wafer. Connecting lines are provided between the pillars, and a supporting frame is provided around the pillars. The frame is connected to the pillars through a bracket. (2) Apply a high-temperature resistant film to one side of the flat surface of the wafer, seal it with plastic, and make the plastic film flush with the surface of the pillar after sealing. Then remove the adhesive film from the wafer. (3) Grind the front side of the wafer obtained in step (2) until the border described in step (1) is removed, forming a TSV pillar + line structure, and then clean it. (4) A patterned insulating layer is formed on the front side of the wafer obtained in step (3), the pattern is photolithographically etched, and photoresist is fabricated on the wafer with the above structure. (5) A metallized wiring layer is formed on the wafer obtained in step (4), and the photoresist and the metal layer on the photoresist are removed together to form a metal interconnect. (6) Repeat steps (4)-(5) on the front side of the wafer obtained in step (5); (7) Repeat steps (4)-(5) on the back side of the wafer obtained in step (6); (8) Using superconducting spheres, spheres are implanted at the chip pad positions corresponding to the above wafers; (9) Attach the chip.

2. The manufacturing method according to claim 1, characterized in that, The superconducting metal used in step (1) is a single-element or multi-element alloy material.

3. The manufacturing method according to claim 1, characterized in that, In step (1), the diameter of the column is 10 to 100 μm and the height is 50 to 500 μm; the height of the connecting line is lower than that of the column; and the thickness of the frame is less than 50 μm.

4. The manufacturing method according to claim 1, characterized in that, In step (2), the diameter of the high-temperature resistant film is 1-3 mm larger than the diameter of the wafer.

5. The manufacturing method according to claim 1, characterized in that, The process of forming the patterned insulating layer in step (4) includes: using Bumping lithography technology and using the process steps of coating, exposure, development and curing.

6. The manufacturing method according to claim 1, characterized in that, The method for forming the metallized wiring layer in step (5) is to use a PVD or vapor deposition machine; the method for removing the photoresist and the metal layer on the photoresist is to use a resist remover and lift off.

7. The manufacturing method according to claim 1, characterized in that, In step (8), the superconducting sphere is mainly composed of superconducting particles and supplemented by tin solder; the superconducting sphere has both solderability and high-temperature superconductivity.

8. The manufacturing method according to claim 1, characterized in that, Depending on the functional requirements, different functions and quantities of superconducting chips are attached.

9. A fully superconducting TSV adapter plate prepared by the manufacturing method as described in claim 1.

10. An application of the fully superconducting TSV adapter plate as described in claim 9 in super quantum computing and quantum communication.

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