A semi-superconducting TSV interposer structure and method of manufacture

Abstract

The application relates to a kind of semi-superconducting TSV adapter plate structure and manufacturing method.The method comprises the following steps: (1) copper wafer is mechanically processed, and cavity space is reserved;(2) copper column is grown on another chip wafer, film is pasted, and cutting is carried out;(3) single chip is embedded into the cavity of copper wafer, and plastic encapsulation is carried out;(4) wafer is mechanically ground;(5) the first insulating layer pattern is formed on the front surface of wafer;(6) the first layer of metalization wiring is formed on wafer;(7) the second layer of insulating layer and wiring layer is formed;(8) wafer back is mechanically ground;(9) the insulating layer and wiring layer are made on the back of wafer;(10) ball is planted in chip Pad position;(11) chip is pasted.The adapter plate is made of copper wafer as frame to make TSV vertical connecting column, and chip is embedded in package body, the path of chip vertical connection is shortened, chip delay is reduced, and the overall quantum communication and supercomputing capacity of package body are improved.The method has simple manufacturing process and low cost.

Description

Technical Field

[0001] This invention belongs to the field of adapter plate technology, and specifically relates to a semi-superconducting TSV adapter plate structure and manufacturing method. Background Technology

[0002] Current adapter board products mostly use silicon as a substrate, with silicon through-hole filling formed by electroplating copper. Before forming the copper pillars, an insulating layer, a barrier layer, and a conductive layer need to be formed on the hole walls. After the metal pillars are deposited, the surface metal layer needs to be removed using CMP (chemical mechanical polishing) to remove the barrier layer and the electroplated metal layer. The entire process is complex and the equipment is expensive. Not only is the manufacturing process complex and costly, but it also cannot meet the zero-resistance requirements of current quantum computing and quantum communication.

[0003] The detailed manufacturing process is as follows:

[0004] 1. Select and use high-resistivity silicon wafers, generally those with a resistance greater than 2MΩ, such as... Figure 1 As shown;

[0005] 2. Photoresist coating: Photoresist is applied to the Si substrate using a spray coating method. A certain thickness of photoresist is applied to serve as a barrier layer during dry etching. Figure 2 As shown;

[0006] 3. Exposure: Using an exposure machine, the areas to be etched on the photoresist-coated Si carrier wafer are exposed or shielded as required (a corresponding mask is created depending on the chosen photoresist). Here, positive photoresist is used; the areas to be etched are exposed, such as... Figure 3 As shown;

[0007] 4. Development: Using a specific chemical solution, the photoresist in the areas to be etched is removed through a chemical reaction, forming a specific pattern, such as... Figure 4 As shown.

[0008] 5. Dry etching: Using a vacuum etching machine, special gases are used to etch silicon to the required depth while maintaining no significant change in the opening. Figure 5 As shown;

[0009] 6. Wet photoresist removal: Residual photoresist on the silicon surface is removed using a wet process, typically through a chemical reaction. Figure 6 As shown;

[0010] 7. Passivation layer deposition: Since silicon is a semiconductor, it cannot directly contact the subsequently deposited metal. Therefore, an insulating layer needs to be deposited. Currently, the common method is PECVD (Plasma-Enhanced Chemical Vapor Deposition). This method is not only expensive but also requires specialized, highly toxic gases. Furthermore, the film's tendency to absorb water affects its insulating properties. Figure 7As shown;

[0011] 8. Deposition of barrier and conductive layers: PVD (Physical Vapor Deposition) is used to deposit barrier and conductive layers. However, this method involves expensive equipment and results in poor deposition thickness and uniformity on the sidewalls, especially the bottom sidewalls. Figure 8 As shown;

[0012] 9. Metal deposition, using a wafer as the cathode for electroplating, completes the filling of the vias and the growth of planar metal, such as... Figure 9 As shown;

[0013] 10. Annealing + CMP: Stress relief is performed on the wafer under high temperature conditions, followed by removal of the outermost conductive metal layer and barrier layer, such as... Figure 10 As shown, when the stress is released, the grains of the metal grow synchronously and non-uniformly in all directions. Since the strength of silicon is relatively small and insufficient to overcome the stress changes, it often leads to microcracks or fragmentation of the silicon wafer, which brings great risks to subsequent processes and equipment. The CMP process is also quite complex. It is necessary to ensure that the conductive metal layer is removed uniformly and cleanly before the barrier layer can be removed. The chemical solution used for each layer removal is different, and different chambers are required, which leads to the high cost of the equipment hardware, often costing tens of millions of RMB.

[0014] 11. Front-side routing: RDL routing is performed on the front side using a bumping process, such as... Figure 11 As shown;

[0015] 12. Backside exposure: After bonding a substrate to the front side, the silicon is first thinned to a certain thickness, exceeding the thickness of the TSV vias, using a backside thinning process. Then, dry etching is used to thin the silicon until the TSV vias are exposed. To prevent metal diffusion during subsequent CMP exposure from affecting the silicon impedance, thin film deposition is required. Next, CMP is used to remove the oxide layer at the bottom of the TSV vias. Finally, CMP is used to remove the barrier layer, such as... Figure 12 As shown;

[0016] Backside wiring and C4 bump growth: After bonding, backside exposure, and a series of photolithography and electroplating processes to form the RDL conductive layer and C4 bumps on the backside, the final product is formed, and the front-side substrate is removed. Figure 13 As shown. Summary of the Invention

[0017] The technical problem to be solved by the present invention is to provide a semi-superconducting TSV adapter plate structure and manufacturing method. The adapter plate greatly improves the functions of chip quantum communication and supercomputing, and the manufacturing process is simple and low cost. It can solve the drawback that multi-element alloy superconducting materials cannot be electroplated to form electrical connection lines.

[0018] This invention provides a method for manufacturing a semi-superconducting TSV adapter plate, comprising:

[0019] (1) Select a copper wafer and machine it from the front side to form pillars of different diameters and shapes. A cavity space for embedding the chip is reserved between the pillars and the cavity space is set in the middle of the pillars.

[0020] (2) Copper pillars are grown on another chip wafer. A film is applied to the back of the wafer with grown copper pillars (to attach and fix the chip to the copper wafer), and the wafer is cut into individual chips (to facilitate subsequent embedding onto the copper wafer).

[0021] (3) Embed the single chip in step (2) into the cavity space of the copper wafer in step (1) and seal it with plastic so that the plastic cover is flush with the surface of the pillar.

[0022] (4) Mechanically grind the wafer obtained in step (3) so that the chip copper pillar and the copper wafer TSV pillar are exposed at the same time and are on the same plane;

[0023] (5) An insulating layer is formed on the front side of the wafer obtained in step (4), and photoresist is then fabricated (the photoresist can be removed later by a stripper).

[0024] (6) A metallized wiring layer is formed on the wafer obtained in step (5), and the photoresist and the metal layer on the photoresist are removed together to form a metal interconnect.

[0025] (7) Form the second insulating layer and wiring layer, and repeat steps (5)-(6);

[0026] (8) Mechanically grind the back side of the wafer obtained in step (7) until the copper on the back side is removed and the bottom of the TSV copper pillar is exposed, and then clean it (to remove metal contaminants and organic impurities).

[0027] (9) An insulating layer and a wiring layer are fabricated on the back side of the wafer obtained in step (8), and steps (5) and (6) are repeated.

[0028] (10) Using superconducting balls, the corresponding chip Pad positions on the wafer obtained in step (9) are used for ball placement;

[0029] (11) Attach the chip.

[0030] Preferably, the copper wafer material in step (1) is elemental copper or a copper alloy.

[0031] Preferably, the machining method in step (1) is machining or laser processing.

[0032] Preferably, the diameter of the columnar body in step (1) is 10 to 100 μm.

[0033] Preferably, the columnar body in step (1) includes a cylindrical, conical, or octagonal body.

[0034] Preferably, in step (1), the thickness of the columnar body is 18-22 μm thicker than the total thickness of the embedded chip and the copper pillars on the chip.

[0035] Preferably, the cavity space size in step (1) is larger than the chip size in step (2).

[0036] Preferably, the copper pillars are grown in step (2) by the bumping method.

[0037] Preferably, the height of the copper column in step (2) is greater than 20 μm.

[0038] Preferably, in step (3), after embedding, a space of at least 50 μm is reserved around the single chip to be adjacent to the columnar body.

[0039] Preferably, in step (3), embedding the single chip in step (2) into the cavity space of the copper wafer in step (1) is done by using a chip mounting machine to attach the chip into the cavity space of the copper wafer.

[0040] Preferably, the process for forming the patterned insulating layer in step (5) is as follows: using Bumping lithography, employing a process of coating, exposure, development, and curing.

[0041] Preferably, the metallized wiring layer is formed in step (6) using a PVD or vapor deposition machine.

[0042] Preferably, in step (6), the removal of the photoresist and the metal layer on the photoresist is performed using a lift-off method.

[0043] Preferably, in step (10), the superconducting sphere is mainly composed of superconducting particles and supplemented by tin solder; the superconducting sphere has solderability and high-temperature superconductivity.

[0044] Preferably, in step (11), the chip attaching process involves attaching superconducting chips with different functions and quantities according to the functional requirements.

[0045] The present invention also provides a semi-superconducting TSV adapter plate manufactured by the above-described manufacturing method.

[0046] The present invention also provides an application of the above-mentioned semi-superconducting TSV adapter plate in super quantum computing and quantum communication.

[0047] Beneficial effects

[0048] This invention uses a copper wafer as a framework to fabricate TSV vertical interconnect pillars and pre-embeds chips within the package, shortening the vertical interconnect path, reducing chip latency, and improving performance. Using superconducting materials as surface electrical interconnects forms a semi-copper plate, semi-superconducting structure, significantly enhancing the chip's quantum communication and supercomputing capabilities. This fabrication process is simple and low-cost, using machining to replace the complex metal wiring process of photolithography + electroplating + wet etching, and the complex TSV pillar formation process requiring photolithography + dry etching + metal filling + CMP exposure. Furthermore, it overcomes the limitation that multi-element alloy superconducting materials cannot be electroplated to form electrical interconnects. Attached Figure Description

[0049] Figure 1 A schematic diagram illustrating the selection of silicon wafers for existing adapter board products;

[0050] Figure 2 A schematic diagram of the structure of the barrier layer formed by applying adhesive during the manufacturing process of existing adapter plate products;

[0051] Figure 3 This is a schematic diagram of the structure of an existing adapter plate product after exposure during the manufacturing process.

[0052] Figure 4 This is a schematic diagram of the structure formed by development during the manufacturing process of existing adapter plate products;

[0053] Figure 5 This is a schematic diagram of the structure after etching during the manufacturing process of an existing adapter board product.

[0054] Figure 6 This is a schematic diagram of the structure after wet adhesive removal during the manufacturing process of existing adapter plate products.

[0055] Figure 7 This is a schematic diagram of the structure of the passivation layer deposited during the manufacturing process of existing adapter plate products.

[0056] Figure 8 This is a schematic diagram of the structure of the barrier layer and conductive layer deposited during the manufacturing process of existing adapter plate products;

[0057] Figure 9 This is a schematic diagram of the structure of the deposited metal during the manufacturing process of existing adapter plate products.

[0058] Figure 10 A schematic diagram of the structure for removing the conductive metal layer and barrier layer during the manufacturing process of existing adapter board products using annealing + CMP.

[0059] Figure 11 This is a schematic diagram of the front wiring structure during the manufacturing process of an existing adapter board product.

[0060] Figure 12This is a schematic diagram of the structure of an existing adapter board product after sequential back-side thinning, dry etching, thin film deposition, oxide layer CMP, and barrier layer CMP during the manufacturing process.

[0061] Figure 13 This is a schematic diagram of the back-side wiring and C4 bump growth process in the manufacturing process of existing adapter board products.

[0062] Figure 14 These are cross-sectional and top views of the copper wafer of this invention;

[0063] Figure 15 This is a schematic diagram of the structure of the columnar body and cavity space formed by the mechanical processing of copper wafers according to the present invention;

[0064] Figure 16 This is a schematic diagram of the structure of copper pillars growing on the chip wafer of the present invention;

[0065] Figure 17 This is a schematic diagram of the structure of the present invention, which has a copper pillar wafer with a film attached to the back side;

[0066] Figure 18 This is a schematic diagram of the structure of the wafer after it has been cut and coated with the film according to the present invention;

[0067] Figure 19 This is a schematic diagram of the structure after the chip is embedded into the copper wafer according to the present invention;

[0068] Figure 20 This is a schematic diagram of the structure of the copper wafer with embedded chip after molding.

[0069] Figure 21 This is a schematic diagram of the structure of the front side of the encapsulated wafer after mechanical polishing according to the present invention;

[0070] Figure 22 This is a schematic diagram of the patterned layer forming the insulating layer on the wafer after grinding, according to the present invention.

[0071] Figure 23 This is a schematic diagram of the structure after photoresist is further fabricated on the wafer according to the present invention;

[0072] Figure 24 This is a schematic diagram of the structure of forming a metallized wiring layer on the front side of a wafer according to the present invention;

[0073] Figure 25 This is a schematic diagram of the structure of the metal interconnects formed after removing the photoresist and its metal layer on the wafer according to the present invention.

[0074] Figure 26 This is a schematic diagram of the structure of forming a second insulating layer and a wiring layer on a wafer according to the present invention;

[0075] Figure 27 This is a schematic diagram of the structure of the wafer after grinding on the back side according to the present invention;

[0076] Figure 28 This is a schematic diagram of the structure of the insulating layer and wiring layer formed on the back side of the wafer according to the present invention;

[0077] Figure 29 This is a schematic diagram of the structure after ball placement at the wafer pad position according to the present invention;

[0078] Figure 30 This is a schematic diagram of the structure of the wafer after the chip is attached. Detailed Implementation

[0079] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0080] Example 1

[0081] This embodiment provides a method for manufacturing a semi-superconducting TSV adapter plate, including:

[0082] (1) Select a copper wafer with a certain thickness, generally between 100 and 500 μm (optimal 150 μm). The wafer material, a superconducting metal, can be a single element or a multi-element alloy (such as niobium, niobium-aluminum, niobium-tin alloys, etc.). Figure 14 As shown;

[0083] (2) Machining: The prepared copper wafers are physically processed using methods such as machining or laser processing to fabricate them into the following shapes. Figure 15 The wafer pattern shown is processed from the front to form columnar bodies of different diameters, generally 10 to 100 μm (30 μm is optimal), heights of 100 to 500 μm (150 μm is optimal), and shapes (cylindrical, conical, or octagonal bodies, with cylinders being preferred). The thickness of this column (100-500 μm) depends on the chip thickness (100 μm), and is slightly more than 20 μm thicker than the total thickness of the chip and chip column that will be embedded later. The cavity space needs to be larger than the chip size, and at least 50 μm of space should be reserved around the chip and the column.

[0084] (3) Copper pillars with a height greater than 20 μm are grown on the chip wafer using the bumping method, such as... Figure 16 As shown;

[0085] (4) Apply a film to the back of the pre-grown copper pillar wafer to adhere and fix the chip onto the copper wafer, such as... Figure 17 As shown;

[0086] (5) The coated wafer is diced to form individual chips, which are then easily embedded onto the copper wafer, such as... Figure 18 As shown;

[0087] (6) Chip mounting: Using a chip mounting machine, the corresponding chips are embedded into the chip cavity space of each copper wafer, such as... Figure 19 As shown;

[0088] (7) Molding: The copper wafer with the embedded chip is molded to a suitable thickness as required, so that the molded surface is flush with the surface of the pillar. Figure 20 As shown;

[0089] (8) Front-side mechanical polishing exposes both the chip copper pillars and the copper wafer TSV pillars simultaneously, placing them on the same plane, such as... Figure 21 As shown;

[0090] (9) Front insulating layer, using Bumping lithography technology, employing a process of coating + exposure + development + curing, in such a way as... Figure 22 The graphic layer shown has an insulating layer formed on the front side;

[0091] (10) Front-side photolithography pattern: A photoresist is then fabricated on the wafer with the above-described structure. This photoresist can be removed subsequently using a photoresist remover, such as... Figure 23 As shown;

[0092] (11) Metallization of the front-side wiring layer: A metallized wiring layer is formed on the wafer using PVD or vapor deposition equipment, such as... Figure 24 As shown;

[0093] (12) Photoresist removal: Using a photoresist remover and a lift-off method, the photoresist and the metal layer on it are removed together to form the required metal interconnects, such as... Figure 25 As shown;

[0094] (13) For the second insulating layer and wiring layer, repeat steps 9 to 12 to form as shown. Figure 26 The structure shown;

[0095] (14) Backside mechanical polishing: Use a polishing wheel to polish the backside of the wafer until the copper is removed and just below the bottom of the TSV copper pillars is exposed. Then perform a cleaning process to remove metallic contaminants and organic impurities, such as... Figure 27 As shown;

[0096] (15) Fabrication of the back insulation layer and wiring layer, repeating steps 9 to 12, to form as shown. Figure 28 The structure shown;

[0097] (16) Chip link point fabrication: Balls are implanted at the chip pad locations using a ball-mounting method. Superconducting balls are used, which are primarily composed of superconducting particles and supplemented with solder (as shown in the diagram below). These balls possess both solderability and high-temperature superconductivity. Figure 29 As shown;

[0098] (17) Chip mounting: After dicing the wafer, different functions and quantities of superconducting chips can be mounted according to functional requirements. This shortens the vertical interconnection path of the chips, reduces chip latency, improves performance, and forms a structure like... Figure 30 The structure shown.

Claims

1. A method for manufacturing a semi-superconducting TSV adapter plate, comprising: (1) Select a copper wafer and perform mechanical processing from the front side of the wafer to form pillars of different diameters and shapes. A cavity space for embedding the chip is reserved between the pillars and the cavity space is set in the middle of the pillars. (2) Grow copper pillars on another chip wafer, apply a film to the back of the grown copper pillar wafer, and cut it into a single chip. (3) Embed the single chip in step (2) into the cavity space of the copper wafer in step (1) and seal it with plastic so that the plastic cover is flush with the surface of the pillar. (4) Mechanically grind the wafer obtained in step (3) so that the chip copper pillar and the copper wafer TSV pillar are exposed at the same time and are on the same plane; (5) A patterned layer of insulating layer is formed on the front side of the wafer obtained in step (4), and photoresist is then fabricated. (6) A metallized wiring layer is formed on the wafer obtained in step (5), and the photoresist and the metal layer on the photoresist are removed together to form a metal interconnect. (7) Form the second insulating layer and wiring layer, and repeat steps (5)-(6); (8) Mechanically grind the back side of the wafer obtained in step (7) until the copper on the back side is removed and the bottom of the TSV copper pillar is exposed, and then clean it. (9) An insulating layer and a wiring layer are fabricated on the back side of the wafer obtained in step (8), and steps (5) and (6) are repeated. (10) Using superconducting balls, the corresponding chip Pad positions on the wafer obtained in step (9) are used for ball placement; (11) Attach the chip.

2. The manufacturing method according to claim 1, characterized in that, In step (1), the copper wafer material is pure copper or copper alloy material; the columnar body includes a cylindrical, conical or octagonal body.

3. The manufacturing method according to claim 1, characterized in that, In step (1), the thickness of the columnar body is 18-22 μm thicker than the total thickness of the embedded chip and the copper pillars on the chip. The cavity space size is larger than the chip size in step (2).

4. The manufacturing method according to claim 1, characterized in that, The copper pillars in step (2) are grown using the Bumping method; the height of the copper pillars is greater than 20 μm.

5. The manufacturing method according to claim 1, characterized in that, The process for forming the patterned insulating layer in step (5) is as follows: using Bumping lithography, the process involves coating, exposure, development and curing.

6. The manufacturing method according to claim 1, characterized in that, In step (6), the metallized wiring layer is formed using a PVD or vapor deposition machine; the photoresist and the metal layer on the photoresist are removed together using a lift-off method.

7. The manufacturing method according to claim 1, characterized in that, In step (10), the superconducting sphere is mainly composed of superconducting particles and supplemented by tin solder; the superconducting sphere has solderability and high-temperature superconductivity.

8. The manufacturing method according to claim 1, characterized in that, In step (11), chip attaching involves attaching superconducting chips with different functions and quantities according to functional requirements.

9. A semi-superconducting TSV adapter plate manufactured by the manufacturing method as described in claim 1.

10. An application of the semi-superconducting TSV adapter plate as described in claim 9 in super quantum computing and quantum communication.

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