A multi-chip stacked package structure of GaN power devices

Abstract

The application relates to a power semiconductor technology, in particular to a GaN power device multi-chip stacked packaging structure. The GaN power device multi-chip stacked packaging structure comprises a GaN chip, a connecting plate and a base substrate. The connecting plate is provided with a through hole and three electrodes, the first and second electrodes are arranged on the front surface of the connecting plate, and the third electrode is arranged on the back surface of the connecting plate through the through hole; the GaN chip is arranged on the connecting plate, the gate of the GaN chip is electrically connected with the first electrode, and the source and the drain of the GaN chip are electrically connected with the second and third electrodes respectively; the connecting plate can be fixedly inserted into the base substrate, the GaN chips can be distributed in a stacked mode, and the GaN chips are electrically connected with the corresponding electrode parts of the base substrate. Compared with the traditional GaN power device packaging form, the application can further reduce the occupied area on the PCB and improve the power density of the device.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology and relates to a multi-chip stacking packaging technology for GaN power devices. Background Technology

[0002] With the continuous advancement of modern society and science and technology, increasingly higher demands are being placed on the use and management of power resources. Power semiconductor technology plays a crucial role in the field of power conversion. However, power semiconductor devices also face several challenges and difficulties. For example, high power density exacerbates heat dissipation problems, packaging stability decreases under high-temperature environments, and high current increases the requirements for connection reliability. Therefore, power semiconductor device packaging technology has become a current research hotspot. Simultaneously, the miniaturization and integration of electronic products are continuously driving the advancement of semiconductor packaging technology, also placing higher demands on it. Gallium nitride (GaN) power semiconductor devices, due to the inherent advantages of their wide bandgap semiconductor material, outperform traditional silicon-based power devices in many aspects, exhibiting strong application advantages in high-frequency, high-efficiency converters. To fully leverage the advantages of wide bandgap semiconductor characteristics, in addition to the internal structure design and processing technology, the packaging of GaN power devices has become a significant limiting factor.

[0003] Gallium nitride (GaN) power semiconductor devices, as a new type of high-power lateral semiconductor device, have seen continuous optimization and improvement in their packaging. GaN power semiconductor devices are generally three-terminal devices, with source (S), drain (D), and gate (G) terminals. Current packaging technologies are primarily designed for wafer-level device design, resulting in relatively large chip sizes. For some applications, this excessive size may have adverse effects. As power module sizes continue to shrink and power densities increase, most current packaging is still based on lateral mounting optimizations (e.g.,...). Figure 1 As shown, the power density of devices within the same printed circuit board (PCB) area is not high. Therefore, how to increase power density while minimizing the increase in size has become a research hotspot. Summary of the Invention

[0004] The purpose of this invention is to address the aforementioned problems by proposing a multi-chip stacked packaging structure for GaN power devices. By changing the traditional packaging method of GaN power devices to a stacked packaging, this stacked packaging can achieve lower parasitic inductance compared to traditional packaging methods, further reducing the PCB board footprint, thereby achieving integration and effectively improving the power density of the device, such as... Figure 1 The image shows a comparison between the GaN chip packaging structure in the prior art and the packaging structure in this invention.

[0005] The technical solution of this invention:

[0006] A multi-chip stacked package structure for GaN power devices, characterized in that it includes a GaN chip 1, a connector plate 2, and a base substrate 3; the GaN chip 1 has a drain 101, a source 102, and a gate 103 on its front side, wherein the drain 101 and the source 102 are arranged parallel to each other at the upper and lower parts of the front side of the GaN chip 1, the horizontal width of the drain 101 is greater than the horizontal width of the source 102, and the gate 103 is on the same horizontal plane as the source 102 and located on both sides of the source 102; the connector plate 2 has a first electrode 21 and a second electrode 22 on its front side, wherein the second electrode 22 is located at the lower part of the front side of the connector plate 2, and the bottom surface of the second electrode 22 protrudes downward, the protruding part of the second electrode 22 beyond the bottom surface of the connector plate 2 is defined as a first protrusion structure; the two ends of the first electrode 21 are respectively located on both sides of the second electrode 22, and Furthermore, the two ends of the first electrode 21 are connected as one unit above the second electrode 22, and one end of the first electrode 21 protrudes downward. The protruding part of the first electrode 21 that extends beyond the bottom surface of the connecting plate 2 is defined as the second protrusion structure. There is a through hole 24 on the upper part of the front side of the connecting plate 2, and a third electrode 23 is provided on the back side of the connecting plate 2 at the position corresponding to the through hole 24. One end of the third electrode 23 extends downward to form a third protrusion structure that extends beyond the bottom surface of the connecting plate 2. The second protrusion structure and the third protrusion structure are respectively located at the two ends of the first protrusion structure. The base plate 3 is divided into three regions by two hollow areas. A first groove 31, a second groove 32, and a third groove 33 are respectively provided on the panel of the three regions, and the first groove 31, the second groove 32, and the third groove 33 are respectively matched with the second protrusion structure, the first protrusion structure, and the third protrusion structure.

[0007] The GaN chip 1, the connector plate 2, and the base substrate 3 are connected as follows: the front side of the GaN chip 1 is mounted on the front side of the connector plate 2, the source 102 is connected to the second electrode 22, the gate 103 is connected to the first electrode 21, and the drain 101 is connected to the third electrode 23 through a through-hole 24; the bottom of the connector plate 2 is directly inserted into the groove on the front side of the base substrate 3 through a raised structure; and there are multiple first grooves 31, second grooves 32, and third grooves 33, which are used to insert multiple GaN chips to form a multi-chip stacked package structure. The same electrical grooves on the base substrate are connected together and then connected to the back side through the through-hole of the base substrate to lead out the electrodes, with the effect as follows. Figure 7 As shown.

[0008] The connector plate 2 has mounting portions corresponding to the electrodes of the GaN chip 1, such as... Figure 4As can be seen from the dimension correspondence diagram, all three electrodes of the GaN chip 1 can be contained within the mounting area of ​​the connector plate 2. The length of the drain mounting portion of the connector plate 2 at both ends is greater than that of the drain 101 of the GaN chip 1, which facilitates the drilling of vias 24 on both sides to bring the electrodes to the back side, and the drilling area does not cover the chip electrode portion. The source mounting portion of the connector plate 2 extends all the way to the second electrode 22. The connector plate 2 brings the gate 103 of the GaN chip 1 to the first electrode 11 through the front-side traces, and there is no interference between the gate and source traces of the connector plate 2.

[0009] like Figure 6 As shown, the base substrate 3 has grooves corresponding to the electrodes of the connecting plate 2. These grooves do not extend through to the back side of the base substrate 3. The first groove 31 of the base substrate 3 corresponds to the first electrode 21 of the connecting plate 2, the second groove 32 of the base substrate 3 corresponds to the second electrode 22 of the connecting plate 2, and the third groove 33 of the base substrate 3 corresponds to the third electrode 23 of the connecting plate 2. The grooves of the base substrate 3 are adjusted according to the characteristics of the electrodes of the connecting plate 2. The first and second grooves, while having the same dimensions as the electrodes of the connecting plate 2, have an additional length on the right side. The third groove, also having the same dimensions as the electrodes of the connecting plate 2, has an additional length on the left side, facilitating a more secure connection of the electrodes during soldering. Grooves with the same electrical properties are connected side-by-side. Since all three electrodes are traced on the back side, it is necessary to drill holes from the front to the back side for routing. The drilled areas do not cover the underlying groove areas.

[0010] The materials of the connecting plate 2 and the base substrate 3 can be high thermal conductivity materials, such as AlN, SiC or graphene; the GaN chip 1 and the connecting plate 2 can be packaged using surface mounting.

[0011] The beneficial results of this invention are: compared with the traditional GaN power device packaging, it can further reduce the area occupied on the PCB board and improve the power density of the device. Attached Figure Description

[0012] Figure 1 This is a comparative schematic diagram of the GaN chip packaging structure in the prior art and the packaging structure in this invention.

[0013] Figure 2 These are three views of the basic structure of the GaN chip used in this invention, where (a) is a front view of the GaN chip, (b) is a back view of the GaN chip, and (c) is a three-dimensional view of the GaN chip.

[0014] Figure 3 This is a schematic diagram of a bonding board for mounting a GaN chip proposed in this invention, wherein (a) is a front view of the bonding board, (b) is a back view of the bonding board, and (c) is a three-dimensional view of the bonding board.

[0015] Figure 4 This is a schematic diagram of the dimensions of a bonding board for mounting a GaN chip, as proposed in this invention, wherein (a) is a dimension correspondence diagram of the bonding board and the GaN chip, and (b) is a front view of the bonding board and the GaN chip being mounted.

[0016] Figure 5 This is an enlarged schematic diagram of the perforated structure of a connector plate for mounting a GaN chip according to the present invention, wherein (a) is an enlarged view of the front of the connector plate and (b) is an enlarged view of the back of the connector plate.

[0017] Figure 6 This is a schematic diagram of a bottom substrate with a bottom plate arranged perpendicularly to the connecting plate proposed in this invention, wherein (a) is a front view of the bottom substrate, (b) is a back view of the bottom substrate, and (c) is a three-dimensional view of the bottom substrate.

[0018] Figure 7 This is a schematic diagram of a GaN chip multi-chip stacked packaging proposed in this invention, wherein (a) is a top view of the packaging effect, (b) is a side view of the packaging effect, (c) is an internal view of the stacked packaging, and (d) is an external view of the stacked packaging.

[0019] Figure 8 This invention provides a step-by-step guide for a multi-chip stacked packaging of GaN chips. Detailed Implementation

[0020] The present invention will now be described in detail with reference to the accompanying drawings.

[0021] like Figure 7 As shown, the device structure includes a GaN chip 1, a connecting plate 2, and a base substrate 3. The connecting plate 2 includes a through hole 24 and three electrodes 11. The first electrode 21 and the second electrode 22 are disposed on the front side of the connecting plate 2, and the third electrode 23 is disposed on the back side of the connecting plate 2 through the through hole 24. The GaN chip 1 is disposed on the connecting plate 2. The gate 103 of the GaN chip 1 is electrically corresponding to the first electrode 21, and the source 102 and the drain 101 of the GaN chip 1 correspond to the second electrode 22 and the third electrode 23, respectively. The connecting plate can be fixedly inserted into the base substrate 3 and connected to the corresponding recessed electrode portion.

[0022] The GaN chip 1 is disposed on the front side of the connector plate 2 and attached thereto, such as... Figure 4As shown, the mounting portion of the connector plate 2 is larger than the electrode size of the GaN chip 1, and its overall area is slightly larger than that of the GaN chip 1, so that the GaN chip 1 can be protected. The gate of the GaN chip 1 is led out from the front side of the connector plate 2 to the first electrode 21, the source of the GaN chip 1 extends from the front side of the connector plate 2 to the second electrode 22, and the drain of the GaN chip 1 is connected to the back side of the connector plate 2 through a via 24 and led out to the third electrode 23. Figure 3 As shown.

[0023] After the GaN chip 1 is mounted on the connecting plate 2, it can be vertically inserted and fixed onto the base substrate 3. The three electrodes on the connecting plate 2 are fixed to the corresponding grooves in the base substrate 3: the first electrode 21 corresponds to the first groove 31 of the base substrate 3, the second electrode 22 corresponds to the second groove 32 of the base substrate 3, and the third electrode 23 corresponds to the third groove 33 of the base substrate 3. Solder can be filled into the bottom of the grooves to solder the electrodes of the connecting plate 2 to the underlying substrate. The gray area next to the grooves serves as a guide for the soldering area. Since the gate 103 and source 102 of the GaN chip 1 are led out on the front side of the connecting plate 2, the soldering areas of the first groove 31 and the second groove 32 are on the right side of the grooves. The drain 101 of the GaN chip 1 is led out on the back side of the connecting plate 2, so the soldering area of ​​the third groove 33 is on the left side of the groove. Figure 6 As shown. Based on the characteristics of the connecting plate electrode, the grooves of the base substrate 3 are the same size as the connecting plate electrode. The first and second grooves have an extra length on the right side, and the third groove has an extra length on the left side. This makes the connection plate 2 and the base substrate 3 more firmly welded together. When the solder liquid seeps into the grooves, it can also strengthen the connection between the connection plate 2 and the base substrate 3 and make the electrode better introduced.

[0024] like Figure 7 As shown, multiple connector plates 2 on which GaN chips 1 are mounted can be vertically inserted into the base substrate 3. The connector plates 2 can completely enclose the GaN chips 1. The length of the base substrate 3 is consistent with the length of the connector plates 2. The height of the packaged device is the height of the connector plates 2. The grooves with the same electrical properties are arranged side by side with a gap of one GaN chip 1 thickness. The first grooves 31 are introduced into the middle of the base substrate 3 through the first through hole 35 to form the gate 402. The second grooves 32 are introduced into the left side of the base substrate 3 through the second through hole 34 to form the source 403. The third grooves 33 are introduced into the right side of the base substrate 3 through the third through hole 36 to form the drain 401. Finally, the corresponding S, G, and D terminals are formed from left to right on the bottom surface of the base substrate 3.

[0025] The structure of this invention can be prepared by the following methods, such as... Figure 8 As shown, the packaging steps are as follows:

[0026] 1. First, attach the GaN chip 1 to the corresponding connector board 2;

[0027] 2. Fix the connector plate 2 with the GaN chip 1 mounted on it to the base substrate 3: Insert the corresponding electrodes into the corresponding grooves respectively. The first electrode 21 corresponds to the first groove 31 of the base substrate 3, the second electrode 22 corresponds to the second groove 32 of the base substrate 3, and the third electrode 23 corresponds to the third groove 33 of the base substrate 3. Then, according to the characteristics of the front and back electrodes, use solder to fix the connector plate 2 and the base substrate 3. Repeat the operation to tightly attach the GaN chip 1 and the connector plate 2 side by side.

[0028] 3. Finally, the upper part of the base substrate 3 with the stacked insertion structure is sealed and packaged into a device 4. The electrodes are all introduced on the bottom surface and arranged in the following order from left to right: source 403, gate 402, and drain 401.

[0029] In this invention, Figure 7 , 8 The number of stacked GaN chips shown in the diagram is only for the purpose of describing the structural relationship of the various components or elements in this invention, and does not specifically refer to the size of the package area in this invention, and should not be construed as a limitation of this invention.

Claims

1. A multi-chip stacked package structure for GaN power devices, characterized in that, The system includes a GaN chip (1), a connector plate (2), and a base substrate (3). The GaN chip (1) has a drain (101), a source (102), and a gate (103) on its front side. The drain (101) and source (102) are arranged parallel to each other on the upper and lower parts of the front side of the GaN chip (1). The horizontal width of the drain (101) is greater than the horizontal width of the source (102). The gate (103) is on the same horizontal plane as the source (102) and located on both sides of the source (102). The connector plate (2) has a first electrode (21) and a second electrode (22) on its front side. The second electrode (22) is located at the lower part of the front side of the connector plate (2), and the middle of the bottom surface of the second electrode (22) protrudes downwards. The protruding portion of the second electrode (22) extending beyond the bottom surface of the connector plate (2) is defined as a first protrusion structure. The two ends of the first electrode (21) are located on both sides of the second electrode (22), and the first... The two ends of an electrode (21) are connected together above the second electrode (22). One end of the first electrode (21) protrudes downward. The protruding part of the first electrode (21) that extends beyond the bottom surface of the connecting plate (2) is defined as the second protrusion structure. There is a through hole (24) on the upper part of the front side of the connecting plate (2). A third electrode (23) is provided on the back side of the connecting plate (2) at the position corresponding to the through hole (24). One end of the third electrode (23) extends downward to extend beyond the bottom surface of the connecting plate (2) to form a third protrusion structure. The second protrusion structure and the third protrusion structure are located at the two ends of the first protrusion structure, respectively. The front side of the base plate (3) has three areas. A first groove (31), a second groove (32), and a third groove (33) are respectively provided on the panel of the three areas. The first groove (31), the second groove (32), and the third groove (33) are matched with the second protrusion structure, the first protrusion structure, and the third protrusion structure, respectively. The GaN chip (1), the connector plate (2), and the base substrate (3) are connected as follows: the front side of the GaN chip (1) is mounted on the front side of the connector plate (2), the source (102) is connected to the second electrode (22), the gate (103) is connected to the first electrode (21), and the drain (101) is connected to the third electrode (23) through the through hole (24); the bottom of the connector plate (2) is directly inserted into the groove on the front side of the base substrate (3) through the protrusion structure; and there are multiple first grooves (31), second grooves (32), and third grooves (33), which are used to insert multiple GaN chips to form a multi-chip stacked package structure.

2. The GaN power device multi-chip stacked packaging structure according to claim 1 is characterized in that: the connecting plate (3) and the base substrate (4) are made of high thermal conductivity materials.

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