Circuitry and protection device with dual ground terminals

Abstract

This invention provides a circuit system and protection device with dual grounding terminals. The protection device mainly forms a bidirectional thyristor at the two grounding terminals through a designed semiconductor structure. Therefore, in addition to isolating the two grounding terminals from voltage, it can also provide an electrostatic discharge path when the voltage difference between the two grounding terminals reaches a certain level, thereby achieving the protection effect of electrostatic discharge and preventing the circuit system from being damaged by high voltage electrostatic shock.

Description

Technical Field

[0001] This invention relates to a protective device for a circuit system with dual grounding terminals, and more particularly to a protective device that can isolate different grounding terminals and achieve electrostatic discharge protection, and a circuit system using the protective device. Background Technology

[0002] Please refer to Figure 1 , Figure 1 This is a block diagram of a conventional circuit system. Circuit system 1 is an application of a driving device and includes a front-end circuit 11 and a driving circuit 12. The front-end circuit 11 is electrically connected to the system voltage terminal VDD and includes a low-voltage side circuit 111 and a high-voltage side circuit 112. The low-voltage side circuit 111 and the high-voltage side circuit 112 are electrically connected to ground terminals GND1 and GND2, respectively, and the high-voltage side circuit 112 is electrically connected to the driving circuit 12. The driving circuit 12 is electrically connected to the input signal terminal VIN and the output signal terminal VOUT.

[0003] In this application, due to the parasitic inductance of the circuit itself, under high current operation, this parasitic inductance will cause changes in the circuit's ground potential. To avoid the influence of this potential change, sometimes the different ground terminals GND1 and GND2 in circuit system 1 are isolated to prevent mutual potential pull. However, when electrostatic discharge occurs, the two isolated ground terminals GND1 and GND2 may block the electrostatic discharge due to their mutual isolation, causing the static electricity to be unable to dissipate and resulting in damage to circuit system 1.

[0004] Please refer to Figure 1 and Figure 2A , Figure 2A This is a cross-sectional schematic diagram of the semiconductor structure of a traditional isolation device. Typically, the ground terminal GND2 operates under high current, therefore, parasitic inductance will cause the voltage value at ground terminal GND2 to rise, creating a voltage difference with ground terminal GND1. Therefore, circuit system 1 will use... Figure 2A The semiconductor structure 21 forms an isolation device to achieve isolation between the two ground terminals GND1 and GND2.

[0005] The semiconductor structure 21 includes a P-type substrate SUB, high-voltage wells HVW1–HVW3, wells W1–W7, doped regions D1–D11, gates G1 and G2, and field isolation devices F1–F8. High-voltage wells HVW1 and HVW3 are high-voltage P-type wells, high-voltage well HVW2 is a high-voltage N-type well, wells W1, W3, W5, and W7 are P-type wells, and wells W2, W4, and W6 are N-type wells. Doped regions D1, D5, D7, and D11 are P-type doped regions, and doped regions D2–D4 and D8–D10 are N-type doped regions. Doped regions D4 and D5 are electrically connected to ground terminal GND2, and doped regions D7 and D8 are electrically connected to ground terminal GND1. Through the arrangement of high-voltage well HVW2, wells W3 and W5 can be effectively isolated. For the symmetrical semiconductor structure 21, the breakdown voltage values ​​in both directions (from ground terminal GND1 to ground terminal GND2 and from ground terminal GND2 to ground terminal GND1) are the same.

[0006] Please refer to Figure 1 and Figure 2B , Figure 2B This is a cross-sectional schematic diagram of a semiconductor structure for a traditional isolation device. Circuit system 1 can also use, for example... Figure 2B The semiconductor structure 22 forms an isolation device to achieve isolation between the two ground terminals GND1 and GND2. The semiconductor structure 22 includes a P-type substrate SUB, high-voltage wells HVW1–HVW4, wells W1–W7, doped regions D1–D9, gates G1 and G2, and field isolation devices F1–F7. High-voltage wells HVW1 and HVW3 are high-voltage P-type wells, high-voltage wells HVW2 and HVW4 are high-voltage N-type wells, wells W1, W3, W4, and W6 are P-type wells, and wells W2, W5, and W7 are N-type wells. Doped regions D1, D4, and D6 are P-type doped regions, and doped regions D2, D3, D5, and D7–D9 are N-type doped regions. Doped regions D3 and D4 are electrically connected to ground terminal GND2, and doped regions D6 and D7 are electrically connected to ground terminal GND1. Through the arrangement of high-voltage wells HVW3 and HVW4, wells W3 and W6 can be effectively isolated. For the asymmetric semiconductor structure 22, the breakdown voltage values ​​in its two directions (from ground terminal GND1 to ground terminal GND2 and from ground terminal GND2 to ground terminal GND1) are different from each other.

[0007] Regardless of the above Figure 2A or Figure 2B In semiconductor structures, the two grounding terminals may be isolated from each other during electrostatic discharge (ESD), preventing the discharge of static electricity and potentially damaging the circuit system. Therefore, there is a need for a protective device that provides both isolation and an ESD path. Summary of the Invention

[0008] To address the problems of prior art and achieve at least one objective of the present invention, embodiments of the present invention provide a protective device for a circuit system having a first ground terminal and a second ground terminal, and comprising a semiconductor structure. This semiconductor structure includes a first high-voltage P-type well, a first P-type well formed within the first high-voltage P-type well, a first P-type doped region, a first N-type doped region, a first high-voltage N-type well horizontally adjacent to the first high-voltage N-type well, a second P-type well formed within the first high-voltage N-type well, a second P-type doped region, and a second N-type doped region. The first P-type doped region and the first N-type doped region are formed within and exposed to the first P-type well, and are horizontally isolated from each other. The second P-type doped region and the second N-type doped region are formed within and exposed to the second P-type well, and are horizontally isolated from each other. The first N-type doped region is located on the first side of the first P-type well near the first high-voltage N-type well, and the first P-type doped region is located on the second side of the first P-type well away from the first high-voltage N-type well. The second N-type doped region is located on the first side of the second P-type well near the first high-voltage P-type well, and the second P-type doped region is located on the second side of the second P-type well away from the first high-voltage P-type well. The first N-type doped region and the second N-type doped region are isolated from each other in the horizontal direction. The first N-type doped region and the first P-type doped region are used to electrically connect to the second ground terminal, and the second N-type doped region and the second P-type doped region are used to electrically connect to the first ground terminal.

[0009] This invention also provides a circuit system comprising the aforementioned protective device, a front-end circuit, and a drive circuit. The front-end circuit includes a low-voltage side circuit and a high-voltage side circuit. The drive circuit is electrically connected to the high-voltage side circuit.

[0010] In summary, the protective device provided by this invention has an isolation effect and can provide an electrostatic discharge path. Compared with traditional isolation devices that only isolate at two grounding terminals, it can more effectively protect the circuit system from damage by high voltage static electricity.

[0011] To further understand the technology, means, and effects of the present invention, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of the present invention. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0012] The accompanying drawings are provided to enable those skilled in the art to further understand the invention and are incorporated in and constitute a part of the specification of the invention. The drawings illustrate exemplary embodiments of the invention and are used together with the specification to explain the principles of the invention.

[0013] Figure 1It is a block diagram of a traditional circuit system.

[0014] Figure 2A This is a cross-sectional schematic diagram of the semiconductor structure of a traditional isolation device.

[0015] Figure 2B This is a cross-sectional schematic diagram of the semiconductor structure of a traditional isolation device.

[0016] Figure 3 This is a block diagram of a circuit system according to an embodiment of the present invention.

[0017] Figure 4 This is a cross-sectional schematic diagram of the symmetrical semiconductor structure of the protective device according to an embodiment of the present invention.

[0018] Figure 5 This is a graph showing the voltage difference and current at the ground terminal of the protective device of this invention with respect to the asymmetric semiconductor structure.

[0019] Figure 6A This is a cross-sectional schematic diagram of the asymmetric semiconductor structure of the protective device according to an embodiment of the present invention.

[0020] Figure 6B This is a cross-sectional schematic diagram of the asymmetric semiconductor structure of a protective device according to another embodiment of the present invention.

[0021] Figure 6C This is a cross-sectional schematic diagram of the asymmetric semiconductor structure of a protective device according to another embodiment of the present invention. Detailed Implementation

[0022] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Where possible, the same component reference numerals are used in the drawings and description to refer to the same or similar parts. Furthermore, the exemplary embodiments are merely one way of implementing the design concept of the invention, and the following examples are not intended to limit the invention.

[0023] To address the problems of prior art, embodiments of the present invention provide a protective device with isolation effect and capable of providing an electrostatic discharge path. This device provides an electrostatic discharge path when the voltage difference between the two grounding terminals reaches a certain level, thereby achieving an electrostatic discharge protection effect. Furthermore, the protective device can provide a bidirectional electrostatic discharge path; that is, when the voltage value at the first grounding terminal is greater than the voltage value at the second grounding terminal and the voltage difference between the grounding terminals is greater than a first conduction voltage value, the protective device provides an electrostatic discharge path from the first grounding terminal to the second grounding terminal; and when the voltage value at the second grounding terminal is greater than the voltage value at the first grounding terminal and the voltage difference between the grounding terminals is greater than a second conduction voltage value, the protective device provides an electrostatic discharge path from the second grounding terminal to the first grounding terminal.

[0024] In one embodiment, the protective device is composed of a symmetrical semiconductor structure, therefore, the first on-state voltage value and the second on-state voltage value are the same. In another embodiment, the protective device is composed of an asymmetrical semiconductor structure, and when the second ground terminal is electrically connected to a high-voltage side current operating at a large current, the first on-state voltage value is designed to be greater than the second on-state voltage value so as not to lose the isolation effect while providing an electrostatic discharge path. The asymmetry here refers to the different electrical characteristics of the high-voltage well regions corresponding to the first and second ground terminals; one is a high-voltage N-type well, and the other is a high-voltage P-type well. Therefore, the breakdown voltage from the first ground terminal to the second ground terminal is not the same as the breakdown voltage from the second ground terminal to the first ground terminal.

[0025] First, please refer to Figure 3 , Figure 3 This is a block diagram of a circuit system according to an embodiment of the present invention. The circuit system 3 includes a protective device 33, a front-end circuit 31, and a drive circuit 32. The high-voltage side circuit 312 of the front-end circuit 31 is electrically connected to the drive circuit 32. The front-end circuit 31 is electrically connected to the system voltage terminal VDD, and ground terminals GND1 and GND2 are electrically connected to the low-voltage side circuit 311 and the high-voltage side circuit 312 of the front-end circuit 31, respectively. The protective device 33 is electrically connected between ground terminals GND1 and GND2 to isolate them and provide a bidirectional electrostatic discharge path, thereby achieving electrostatic discharge protection.

[0026] The main feature of this invention is the design of the semiconductor structure of the protective device 33. This design enables the semiconductor structure to generate an electrostatic discharge path when the voltage difference at the grounding terminal reaches a certain level, thereby preventing damage to the circuit system 3. Furthermore, the design of the on-state voltage must be less than the breakdown voltage and not lower than the isolation voltage to ensure that the protective device 33, constructed from the semiconductor structure, provides both isolation and an electrostatic discharge path.

[0027] Next, please refer to Figure 3 and Figure 4 , Figure 4 This is a cross-sectional schematic diagram of the symmetrical semiconductor structure of the protective device according to an embodiment of the present invention. Figure 3 Protective equipment 33 can be Figure 4The symmetrical semiconductor structure 4 is implemented. Semiconductor structure 4 includes a P-type substrate SUB, a high-voltage well HVW1, wells W1-W3, doped regions D1-D5, and field isolation devices F1-F6. The high-voltage well HVW1 is a high-voltage N-type well, wells W1 and W3 are P-type wells, well W2 is an N-type well, doped regions D1 and D5 are P-type doped regions, and doped regions D2-D4 are N-type doped regions. Doped regions D1 and D2 are electrically connected to the ground terminal GND2, and doped regions D4 and D5 are electrically connected to the ground terminal GND1.

[0028] High-voltage well HVW1 is formed on a P-type substrate SUB, and wells W1 to W3 are sequentially formed within high-voltage well HVW1 in the horizontal direction (from left to right). Well W2 is adjacent to the right side of well W1 and the left side of well W3 on its left and right sides respectively. Doped regions D1 and D2 are formed on and exposed to well W1, and are horizontally isolated from each other (via field isolator F2). Doped regions D4 and D5 are formed on and exposed to well W3, and are horizontally isolated from each other (via field isolator F5). Doped region D3 is formed on wells W1 to W3, and is horizontally isolated from doped regions D2 and D4 (via field isolators F3 and F4). Field isolation element F1 is located above high-pressure well HVW1 and well W1, field isolation elements F2 and F3 are formed above well W1, field isolation elements F4 and F5 are formed above well W3, and field isolation element F6 is located above high-pressure well HVW1 and well W3.

[0029] Furthermore, a portion of field isolator F1 is located on the left side of high-voltage well HVW1, and another portion of field isolator F1 is located on the left side of well W1. Doped region D1 is located on the side of well W1 furthest from well W2 (i.e., on the left side of well W1), and the left side of doped region D1 is adjacent to the right side of field isolator F1. The left and right sides of field isolator F2 are adjacent to the right side of doped region D1 and the left side of doped region D2, respectively. Doped region D2 is located on the side of well W1 closest to well W2 (i.e., on the right side of well W1). The left and right sides of field isolator F3 are adjacent to the right side of doped region D2 and the left side of doped region D3, respectively. The left side of doped region D3 is located above well W1, the middle part of doped region D3 is located above well W2, and the right side of doped region D3 is located above well W3. The left and right sides of field isolator F4 are adjacent to the right side of doped region D3 and the left side of doped region D4, respectively. Doped region D4 is located on the side of well W3 closest to well W2 (i.e., on the left side of well W3). Field isolator F5 is located adjacent to the right side of doped region D4 and the left side of doped region D5, respectively. Doped region D5 is located on the side of well W3 furthest from well W2 (i.e., the right side of well W3), and the right side of doped region D5 is adjacent to the left side of field isolator F6. Part of field isolator F6 is located on the right side of well W3, and another part of field isolator F1 is located on the right side of high-voltage well HVW1.

[0030] Semiconductor structure 4 is symmetrical, so the forward voltage values ​​in both directions (from ground terminal GND1 to ground terminal GND2 and from ground terminal GND2 to ground terminal GND1) are the same. Similarly, the isolation voltage values ​​in both directions are the same, as are the breakdown voltage values ​​in both directions. With the aforementioned semiconductor structure 4, when the voltage value at ground terminal GND2 is greater than the voltage value at ground terminal GND1 (or the voltage value at ground terminal GND1 is greater than the voltage value at ground terminal GND2), and the voltage difference between the two ground terminals is greater than the forward voltage value, the PNPN thyristor formed between ground terminals GND1 and GND2 will conduct, providing an electrostatic discharge path and thus achieving electrostatic discharge protection. Furthermore, the doped region D3 on well W2 is an N-type doped region, which can reduce the forward voltage value, preventing it from becoming excessively high. In addition, the conduction voltage value can be adjusted by the width of the doped region D3. Therefore, with proper adjustment, the conduction voltage value can be prevented from being too high or too low, so that the protective device 33 can have an isolation effect and provide an electrostatic discharge path.

[0031] Please refer to Figure 5 , Figure 5 This is a graph showing the voltage difference versus current at the ground terminal of the asymmetric semiconductor structure of the protective device according to an embodiment of the present invention. Figure 5 As shown, regions R11, R12, and R13 represent the isolation region, conduction region, and breakdown region in the direction from ground terminal GND1 to ground terminal GND2, respectively. In region R11, ground terminals GND1 and GND2 are isolated from each other and do not conduct, generating a voltage isolation effect. In region R12, the thyristor in the semiconductor structure conducts to provide an electrostatic discharge path from ground terminal GND1 to ground terminal GND2, and its conduction curve is shown as curve C2. In region R13, the semiconductor structure will break down, causing component damage. Because an electrostatic discharge path from ground terminal GND1 to ground terminal GND2 is provided in region R12, the semiconductor structure can be prevented from operating in region R13.

[0032] Regions R21, R22, and R23 represent the isolation region, conduction region, and breakdown region in the direction from ground terminal GND2 to ground terminal GND1, respectively. In region R21, ground terminals GND2 and GND1 are isolated from each other and do not conduct, creating a voltage isolation effect. In region R22, the thyristor in the semiconductor structure conducts, providing an electrostatic discharge path from ground terminal GND2 to ground terminal GND1, and its conduction curve is shown as curve C3. In region R23, the semiconductor structure breaks down, causing component damage. Because an electrostatic discharge path from ground terminal GND1 to ground terminal GND2 is provided in region R22, the semiconductor structure can be prevented from operating in region R23.

[0033] In protective devices constructed with asymmetrical semiconductor structures, the forward voltage values ​​in the two directions must be designed to be different. If they are designed to be the same, the thyristor in the semiconductor structure will conduct in region R11 in the direction from ground terminal GND1 to GND2, with a conduction curve as shown in curve C1, thus degrading the voltage isolation effect between ground terminals GND1 and GND2. Therefore, the asymmetrical semiconductor structure in this embodiment aims to form a bidirectional thyristor with different forward voltage values ​​in the two directions, in order to maintain better isolation and electrostatic discharge protection.

[0034] Please refer to Figure 3 and Figure 6A , Figure 6A This is a cross-sectional schematic diagram of the asymmetric semiconductor structure of the protective device according to an embodiment of the present invention. Figure 3 Protective equipment 33 can be Figure 6A The asymmetric semiconductor structure 61 is used to implement this. The semiconductor structure 61 includes a P-type substrate SUB, high-voltage wells HVW1, HVW2, HVW3, wells W1-W3, doped regions D1-D5, and field isolation devices F1-F5. High-voltage wells HVW1 and HVW3 are high-voltage P-type wells, high-voltage well HVW2 is a high-voltage N-type well, wells W1-W3 are P-type wells, doped regions D1, D4, and D5 are P-type doped regions, and doped regions D2 and D3 are N-type doped regions. Doped regions D1, D2, and D5 are electrically connected to ground terminal GND2, and doped regions D3 and D4 are electrically connected to ground terminal GND1.

[0035] High-voltage wells HVW1 to HVW3 are formed on a P-type substrate SUB. Well W1 is formed in high-voltage well HVW1. Doped regions D1 and D2 are formed in and exposed to well W1, and horizontally, doped regions D1 and D2 are isolated from each other by field isolator F2. The left side of high-voltage well HVW2 is horizontally adjacent to the right side of high-voltage well W1. Well W2 is formed in high-voltage well HVW2. Doped regions D3 and D4 are formed in and exposed to well W2. Horizontally, doped regions D3 and D4 are isolated from each other by field isolator F4. The left side of high-voltage well HVW3 is horizontally adjacent to the right side of high-voltage well HVW2. Well W3 is formed in high-voltage well HVW3. Doped region D5 is formed in and exposed to well W3.

[0036] Doped region D2 is located on the side of well W1 closest to high-pressure well HVW2 (i.e., the right side of well W1), and doped region D1 is located on the other side of well W1 furthest from high-pressure well HVW2 (i.e., the left side of well W1). Doped region D3 is located on the side of well W2 closest to high-pressure well HVW1 (i.e., the left side of well W2), and doped region D4 is located on the side of well W2 furthest from high-pressure well HVW1 (i.e., the right side of well W2). Doped regions D2 and D3 are horizontally isolated from each other by field isolator F3. Doped region D5 is horizontally isolated from doped region D4 by field isolator F5.

[0037] A portion of field isolator F1 is formed on high-voltage well HVW1, and another portion of field isolator F1 is formed on well W1, and horizontally located on the side of doped region D1 away from high-voltage well HVW2 (i.e., the left side of doped region D1). Field isolator F2 is formed on well W1 and horizontally located between doped regions D1 and D2. Several portions of field isolator F3 are formed on well W1, high-voltage well HVW1, HVW2, and well W2, respectively, and horizontally located between doped regions D2 and D3. Field isolator F4 is formed on well W2 and horizontally located between doped regions D3 and D4. Several portions of field isolator F5 are formed on well W2, high-voltage well HVW2, HVW3, and well W3, respectively, and horizontally located on the side of doped region D4 away from high-voltage well HVW1 (i.e., the right side of doped region D4).

[0038] High-voltage wells HVW1, HVW2, wells W1, W2, doped regions D1-D4, and field isolation elements F1-F5 constitute a bidirectional thyristor, which can be used to isolate the voltage between grounding terminals GND2 and GND1. When the grounding terminal voltage difference from grounding terminal GND1 to grounding terminal GND2 is positive and greater than the first conduction voltage value, the bidirectional thyristor formed by semiconductor structure 61 provides an electrostatic discharge path from grounding terminal GND1 to grounding terminal GND2. When the grounding terminal voltage difference from grounding terminal GND2 to grounding terminal GND1 is positive and greater than the second conduction voltage value, the bidirectional thyristor formed by semiconductor structure 61 provides an electrostatic discharge path from grounding terminal GND2 to grounding terminal GND1. In this embodiment, since grounding terminal GND2 is electrically connected to the high-voltage side circuit 312 and grounding terminal GND1 is electrically connected to the low-voltage side circuit 311, the first conduction voltage value is designed to be greater than the second conduction voltage value, such as... Figure 5 As shown. Additionally, it should be noted that in this embodiment of the invention, the bidirectional thyristor is composed of high-pressure wells HVW1, HVW2, wells W1, W2, doped regions D1-D4, and field isolation elements F1-F5. In other words, doped region D4, high-pressure wells HVW3, wells W3, and the P-type substrate SUB are optional components of this invention and can be removed.

[0039] Please refer to Figure 3 and Figure 6B , Figure 6B This is a cross-sectional schematic diagram of the asymmetric semiconductor structure of a protective device according to another embodiment of the present invention. Unlike... Figure 6A In one embodiment, the semiconductor structure 62 further includes a well W4. Well W4 is an N-type well formed within the high-voltage well HVW2 and is horizontally adjacent to both well W2 and high-voltage well HVW1. High-voltage wells HVW1 and HVW2, wells W1, W2, and W4, doped regions D1 to D4, and field isolation elements F1 to F5 constitute a bidirectional thyristor, similarly providing voltage isolation and electrostatic discharge protection.

[0040] Please refer to Figure 3 and Figure 6C , Figure 6C This is a cross-sectional schematic diagram of the asymmetric semiconductor structure of a protective device according to another embodiment of the present invention. Unlike... Figure 6B In one embodiment, the semiconductor structure 63 further includes a doped region D6 and a field isolator F6. The doped region D6 is an N-type doped region, and multiple portions of the doped region D6 are formed on and exposed to high-voltage wells HVW1, W4, and HVW2, respectively. Field isolator F6 is formed on well W2, and field isolator F3 is formed only on well W1 and high-voltage well HVW1. In the horizontal direction, field isolator F3 is used to isolate doped regions D2 and D6, and field isolator F6 is used to isolate doped regions D6 and D3. High-voltage wells HVW1, HVW2, wells W1, W2, W4, doped regions D1–D4, D6, and field isolators F1–F6 constitute a bidirectional thyristor, and similarly provide voltage isolation and electrostatic discharge protection.

[0041] In summary, this invention provides a protective device implemented using a semiconductor structure, which can be used in circuit systems with dual grounding terminals. Besides providing voltage isolation between the two grounding terminals, it also achieves electrostatic discharge protection. The implementation of the semiconductor structure in this invention is neither complex nor difficult, thus enabling mass production and widespread application in various circuit systems with dual grounding terminals, thereby possessing economic value and industrial applicability.

[0042] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes thereto will be suggested to those skilled in the art and will be included within the spirit and scope of this application and the scope of the appended claims.

Claims

1. A protection device for circuitry having a first ground and a second ground, consisting of a semiconductor structure, characterized by, The semiconductor structure includes: First high-pressure P-type well; The first P-type well is formed within the first high-pressure P-type well; A first P-type doped region and a first N-type doped region, wherein the first P-type doped region and the first N-type doped region are formed in and exposed to the first P-type well, and in the horizontal direction, the first P-type doped region and the first N-type doped region are isolated from each other. The first high-pressure N-type well is adjacent to the first high-pressure P-type well in the horizontal direction; A second P-type well is formed within the first high-pressure N-type well; and A second P-type doped region and a second N-type doped region, wherein the second P-type doped region and the second N-type doped region are formed in and exposed to the second P-type well, and in the horizontal direction, the second P-type doped region and the second N-type doped region are isolated from each other; The first N-type doped region is located on the first side of the first P-type well near the first high-voltage N-type well, the first P-type doped region is located on the second side of the first P-type well away from the first high-voltage N-type well, the second N-type doped region is located on the first side of the second P-type well near the first high-voltage P-type well, the second P-type doped region is located on the second side of the second P-type well away from the first high-voltage P-type well, the first N-type doped region and the second N-type doped region are isolated from each other in the horizontal direction, the first N-type doped region and the first P-type doped region are used to electrically connect to the second ground terminal, and the second N-type doped region and the second P-type doped region are used to electrically connect to the first ground terminal.

2. The protective equipment of claim 1, wherein, The semiconductor structure further includes a P-type substrate, wherein the first high-voltage P-type well and the first high-voltage N-type well are formed on the P-type substrate.

3. The protective equipment of claim 1, wherein, The semiconductor structure further includes: A first field isolator is formed on the first high-pressure P-type well and above the first P-type well, and is located in the horizontal direction on the side of the first P-type doped region away from the first high-pressure N-type well; and The second field isolator is formed on the first high-pressure N-type well and the second P-type well, and is located in the horizontal direction on the side of the second P-type doped region away from the first high-pressure P-type well.

4. The protective equipment as described in claim 1, characterized in that, The semiconductor structure further includes: The third isolation element is formed on the first P-type well and is located in the horizontal direction between the first P-type doped region and the first N-type doped region. A fourth field isolator is formed on the first high-voltage P-type well, the first P-type well, the first high-voltage N-type well, and the second P-type well, and is located in the horizontal direction between the first N-type doped region and the second N-type doped region; and The fifth field isolator is formed on the second P-type well and is located in the horizontal direction between the second N-type doped region and the second P-type doped region.

5. The protective equipment as described in claim 1, characterized in that, The semiconductor structure further includes: The second high-pressure P-type well is located adjacent to the first high-pressure N-type well in the horizontal direction; The third P-type well was formed within the second high-pressure P-type well; and A third P-type doped region is formed in and exposed to the third P-type well. The third P-type doped region is isolated from the second N-type doped region in the horizontal direction, and the third P-type doped region is electrically connected to the second ground terminal.

6. The protective equipment as described in claim 1, characterized in that, The semiconductor structure further includes: An N-type well is formed within the first high-pressure N-type well and is located adjacent to the second P-type well and the first high-pressure P-type well in the horizontal direction.

7. The protective equipment as described in claim 6, characterized in that, The semiconductor structure further includes: A third N-type doped region is formed on and exposed to the N-type well, the first high-voltage N-type well, and the first high-voltage P-type well, and is isolated from the first N-type doped region and the second N-type doped region in the horizontal direction.

8. The protective equipment as described in claim 1, characterized in that, When the voltage difference between the first ground terminal and the second ground terminal is positive and greater than the first on-state voltage, the semiconductor structure provides an electrostatic discharge path from the first ground terminal to the second ground terminal; and when the voltage difference between the second ground terminal and the first ground terminal is positive and greater than the second on-state voltage, the semiconductor structure provides an electrostatic discharge path from the second ground terminal to the first ground terminal.

9. The protective equipment as described in claim 8, characterized in that, The first on-voltage value is greater than the second on-voltage value.

10. A circuit system, characterized in that, The circuit system includes: The protective equipment as described in any one of claims 1-9; The front-end circuit includes a low-voltage side circuit and a high-voltage side circuit; and The drive circuit is electrically connected to the high-voltage side circuit.

11. The circuit system as claimed in claim 10, characterized in that, The first grounding terminal is electrically connected to the low-voltage side circuit, and the second grounding terminal is electrically connected to the high-voltage side circuit.

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