Semiconductor device

Abstract

A semiconductor device includes first to fourth electrodes, a semiconductor element, and an insulating element. The semiconductor element includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the second conductivity type. The third semiconductor region includes a first partial region and a second partial region. The second partial region is between the first semiconductor region and the second semiconductor region in a first direction. The first partial region is between the first semiconductor region and the third electrode in the first direction. The third electrode overlaps the second semiconductor region, the fourth semiconductor region, and the fifth semiconductor region in a second direction intersecting the first direction. The fourth electrode is between the first partial region and the third electrode in the first direction. A direction from the fourth electrode to the second partial region is along the second direction.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2022-019264 (filed on February 10, 2022). The entire contents of that application are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor device. Background Technology

[0003] For example, semiconductor devices such as IGBTs (insulated gate bipolar transistors) are used in power conversion circuits. There is a need for drive devices and semiconductor modules that can suppress losses in semiconductor devices. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device capable of suppressing losses.

[0005] According to an embodiment of the present invention, a semiconductor device includes a first electrode, a second electrode, a third electrode, a fourth electrode, a semiconductor component, and an insulating component. The semiconductor component includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the second conductivity type. The position of the first semiconductor region in a first direction from the first electrode to the first semiconductor region is between the position of the first electrode in the first direction and the position of the second semiconductor region in the first direction. The third semiconductor region includes a first partial region and a second partial region. The second partial region is located between the first semiconductor region and the second semiconductor region in the first direction. At least a portion of the fourth semiconductor region is located between the second partial region and the second semiconductor region in the first direction. The fifth semiconductor region is located between the second partial region and the at least a portion of the fourth semiconductor region in the first direction. The sixth semiconductor region is located between the first electrode and the first semiconductor region in the first direction. The second electrode is electrically connected to the second semiconductor region. The first partial region is located between the first semiconductor region and the third electrode in the first direction. In a second direction intersecting the first direction, the third electrode overlaps with at least a portion of the second semiconductor region, the fourth semiconductor region, and the fifth semiconductor region. The fourth electrode is located between the first partial region and the third electrode in the first direction. The direction from the fourth electrode to the second partial region follows the second direction. At least a portion of the insulating member is disposed between the semiconductor member and the third electrode, between the semiconductor member and the fourth electrode, and between the third electrode and the fourth electrode.

[0006] The semiconductor device configured as described above can provide a semiconductor device capable of suppressing losses. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional view illustrating the semiconductor device of the first embodiment.

[0008] Figure 2 This is a schematic cross-sectional view illustrating a portion of the semiconductor device according to the first embodiment.

[0009] Figure 3 (a) and Figure 3 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0010] Figure 4(a) and Figure 4 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0011] Figure 5 (a) and Figure 5 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0012] Figure 6 (a) and Figure 6 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0013] Figure 7 (a) and Figure 7 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0014] Figure 8 (a) and Figure 8 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0015] Figure 9 This is a graph illustrating the characteristics of the semiconductor device according to the first embodiment.

[0016] Figure 10 This is a graph illustrating the characteristics of the semiconductor device according to the first embodiment.

[0017] Figure 11 This is a graph illustrating the characteristics of a semiconductor device according to an example implementation.

[0018] Figure 12 This is a graph illustrating the characteristics of a semiconductor device according to an example implementation.

[0019] Explanation of symbols

[0020] 10: Semiconductor component; 10T: Trench; 11-17: First semiconductor region to seventh semiconductor region; 13a-13c: First part region to third part region; 40: Insulating component; 41: First insulating region; 51-54: First electrode to fourth electrode; 53a: First end; 54b: Second end; 61: First conductive component; 61a, 61b: First conductive part, second conductive part; 70: Control unit; 70D: Drive circuit; 70P: Power supply circuit; Δt1, Δt2: Difference; 110: Half Conductor device; D1~D3: Direction 1~Direction 3; DC1~DC6: Driving condition 1~Driving condition 6; DS1, DS2: Driving signal 1, Driving signal 2; E2: Second electrode potential; Eoff: Cut-off loss; Eon: Turn-on loss; L1, L2: Length; OP1, OP2: First action, Second action; V1~V4: Potential 1~Potential 4; b1: Boundary; d1, d2: Distance 1, Distance 2; t1~t4: Time 1~Time 4; tm: Time. Detailed Implementation

[0021] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0022] The accompanying drawings are schematic or conceptual, and the relationships between the thickness and width of the parts, as well as the size ratios between the parts, are not necessarily limited to the actual situation. Even when representing the same parts, the dimensions and proportions of each part may differ according to the accompanying drawings.

[0023] In this application specification and the various drawings, elements that are the same as those previously described in relation to the drawings are marked with the same reference numerals and detailed descriptions are appropriately omitted.

[0024] (First Embodiment)

[0025] Figure 1 This is a schematic cross-sectional view illustrating the semiconductor device of the first embodiment.

[0026] like Figure 1 As shown, the semiconductor device 110 of the embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a fourth electrode 54, a semiconductor component 10, and an insulating component 40.

[0027] The semiconductor component 10 includes a first semiconductor region 11 of a first conductivity type, a second semiconductor region 12 of a first conductivity type, a third semiconductor region 13 of a second conductivity type, a fourth semiconductor region 14 of a second conductivity type, a fifth semiconductor region 15 of a first conductivity type, and a sixth semiconductor region 16 of a second conductivity type.

[0028] For example, the first conductivity type is n-type and the second conductivity type is p-type. In an embodiment, the first conductivity type may also be p-type and the second conductivity type may be n-type. Hereinafter, we will assume that the first conductivity type is n-type and the second conductivity type is p-type.

[0029] The direction from the first electrode 51 to the first semiconductor region 11 is defined as the first direction D1. The first direction D1 is defined as the Z-axis direction. A direction perpendicular to the Z-axis direction is defined as the X-axis direction. A direction perpendicular to both the Z-axis and X-axis directions is defined as the Y-axis direction.

[0030] The position of the first semiconductor region 11 in the first direction D1 is between the position of the first electrode 51 in the first direction D1 and the position of the second semiconductor region 12 in the first direction D1.

[0031] The third semiconductor region 13 includes a first portion region 13a and a second portion region 13b. The second portion region 13b is located between the first semiconductor region 11 and the second semiconductor region 12 in the first direction D1.

[0032] At least a portion of the fourth semiconductor region 14 is located between the second partial region 13b and the second semiconductor region 12 in the first direction D1. The fifth semiconductor region 15 is located between the second partial region 13b and the aforementioned at least a portion of the fourth semiconductor region 14 in the first direction D1. The sixth semiconductor region 16 is located between the first electrode 51 and the first semiconductor region 11 in the first direction D1.

[0033] The second electrode 52 is electrically connected to the second semiconductor region 12.

[0034] The first part, region 13a, lies between the first semiconductor region 11 and the third electrode 53 in the first direction D1. In the second direction D2, which intersects the first direction D1, the third electrode 53 overlaps with at least a portion of the second semiconductor region 12, the fourth semiconductor region 14, and the fifth semiconductor region 15.

[0035] The second direction D2 is, for example, the X-axis direction. For example, it extends along the second direction D2 from a portion of the third electrode 53 toward the second semiconductor region 12. It also extends along the second direction D2 from another portion of the third electrode 53 toward at least a portion of the fourth semiconductor region 14. Finally, it extends along the second direction D2 from another portion of the third electrode 53 toward the fifth semiconductor region 15.

[0036] The fourth electrode 54 is located between the first partial region 13a and the third electrode 53 in the first direction D1. The direction from the fourth electrode 54 to the second partial region 13b is along the second direction D2. The third electrode 53 and the fourth electrode 54 extend, for example, along the third direction D3. The third direction D3 intersects a plane that includes the first direction D1 and the second direction D2. The third direction D3 is, for example, the Y-axis direction.

[0037] At least a portion of the insulating member 40 is disposed between the semiconductor member 10 and the third electrode 53, between the semiconductor member 10 and the fourth electrode 54, and between the third electrode 53 and the fourth electrode 54.

[0038] The current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potentials of the third electrode 53 and the fourth electrode 54. The potentials of the third electrode 53 and the fourth electrode 54 can, for example, be potentials referenced to the potential of the second electrode 52 (second electrode potential E2). The semiconductor device 110 is, for example, a transistor. The semiconductor device 110 is, for example, an IGBT (Insulated Gate Bipolar Transistor). The first electrode 51 functions, for example, as a collector. The second electrode 52 functions, for example, as an emitter. The third electrode 53 functions as a first gate. The fourth electrode 54 functions as a second gate.

[0039] Semiconductor region 11 functions as a drift layer, for example. Semiconductor region 12 functions as an emitter layer, for example. Semiconductor region 14 functions as a base layer, for example. Semiconductor region 15 functions as a barrier layer, for example.

[0040] For example, the carrier concentration of the first conductivity type in the second semiconductor region 12 is higher than the carrier concentration of the first conductivity type in the first semiconductor region 11. The first semiconductor region 11 is, for example, n - Layer. The second semiconductor region 12 is, for example, an n-layer.

[0041] For example, the carrier concentration of the first conductivity type in the fifth semiconductor region 15 is higher than the carrier concentration of the first conductivity type in the first semiconductor region 11. The fifth semiconductor region 15 is, for example, an n-layer.

[0042] like Figure 1As shown, the semiconductor component 10 may further include a seventh semiconductor region 17. The seventh semiconductor region 17 is of a first conductivity type. The seventh semiconductor region 17 is located between the sixth semiconductor region 16 and the first semiconductor region 11 in the first direction D1. The carrier concentration of the first conductivity type in the seventh semiconductor region 17 is higher than the carrier concentration of the first conductivity type in the first semiconductor region 11. The seventh semiconductor region 17 is, for example, an n-layer. The seventh semiconductor region 17 is provided as needed and may also be omitted.

[0043] For example, a semiconductor component 10 is disposed on the first electrode 51. For example, a sixth semiconductor region 16, a seventh semiconductor region 17, a first semiconductor region 11, a third semiconductor region 13, a fifth semiconductor region 15, a fourth semiconductor region 14, and a second semiconductor region 12 are sequentially disposed on the first electrode 51. A trench 10T is disposed on the semiconductor component 10. A fourth electrode 54 and a third electrode 53 are disposed inside the trench 10T.

[0044] In this embodiment, a third semiconductor region 13 is provided. This mitigates the electric field in the portion corresponding to the bottom of the trench 10T. For example, it suppresses dynamic avalanche.

[0045] By configuring the third semiconductor region 13 and the fourth electrode 54, losses can be suppressed, for example. For example, losses can be suppressed while maintaining good switching characteristics (di / dt). For example, the balance between switching characteristics and losses can be improved.

[0046] For example, in the first reference example, neither the third semiconductor region 13 nor the fourth electrode 54 is provided. In the second reference example, the third semiconductor region 13 is not provided, but the fourth electrode 54 is provided. In the third reference example, the third semiconductor region 13 is provided, but the fourth electrode 54 is not provided. In this embodiment, both the third semiconductor region 13 and the fourth electrode 54 are provided.

[0047] In the first reference example, the conduction loss Eon is, for example, 6.43 mJ, and the cutoff loss Eoff is, for example, 20.9 mJ. In the second reference example, the conduction loss Eon is, for example, 5.29 mJ, and the cutoff loss Eoff is, for example, 20.2 mJ. In the third reference example, the conduction loss Eon is, for example, 3.6 mJ, and the cutoff loss Eoff is, for example, 20.1 mJ. In the embodiment, the conduction loss Eon is, for example, 3.45 mJ, and the cutoff loss Eoff is, for example, 19.2 mJ.

[0048] Thus, losses can be reduced in the implementation. By driving the fourth electrode 54, the gate capacitance during switching can be reduced. Therefore, losses can be considered to be reduced. For example, the reason for the reduction in gate capacitance can be considered to be that the depletion layer is controlled by driving the fourth electrode 54.

[0049] Figure 2 This is a schematic cross-sectional view illustrating a portion of the semiconductor device according to the first embodiment.

[0050] Figure 2 yes Figure 1 A magnified view of a portion. For example... Figure 2 As shown, the third electrode 53 does not overlap with the second part region 13b in the second direction D2.

[0051] The insulating component 40 includes a first insulating region 41. The first insulating region 41 is disposed between the third electrode 53 and the fourth electrode 54. The first insulating region 41 overlaps with the fifth semiconductor region 15 in the second direction D2. The first insulating region 41 does not overlap with the third semiconductor region 13 in the second direction D2. For example, a portion of the fourth electrode 54 overlaps with the fifth semiconductor region 15 in the second direction D2.

[0052] The third electrode 53 includes a first end 53a on the side of the fourth electrode 54. The first end 53a is, for example, the lower end of the third electrode 53. The fourth electrode 54 includes a second end 54b on the side of the third electrode 53. The second end 54b is, for example, the upper end of the fourth electrode 54. A first insulating region 41 is provided between the second end 54b and the first end 53a. The distance in the first direction D1 between the second end 54b and the first end 53a is defined as a second distance d2. The second distance d2 is the distance along the first direction S1 between the fourth electrode 54 and the third electrode 53. The second distance d2 is preferably, for example, 10 nm or more and 360 nm or less. The second distance d2 may also be 120 nm or more. By having a second distance d2 of 120 nm or more, driving the fourth electrode 54 becomes easier, for example. The second distance d2 may also be 480 nm or less. By having a second distance d2 of 480 nm or less, for example, it is easier to reduce the gate capacitance.

[0053] For example, semiconductor component 10 includes a first boundary b1 between the second portion region 13b and the fifth semiconductor region 15. The first boundary b1 is located below the second end 54b. The distance along the first direction D1 between the position of the first boundary b1 in the first direction D1 and the position of the second end 54b in the first direction D1 is defined as a first distance d1. The first distance d1 is preferably, for example, 10 nm or more and 200 nm or less. When the first distance d1 is 10 nm or more, driving the fourth electrode 54 becomes easier, for example. When the first distance d1 is 200 nm or less, the gate capacitance is easily reduced, for example.

[0054] The length of the third electrode 53 along the first direction D1 is defined as length L1. The length of the fourth electrode 54 along the first direction D1 is defined as length L2. Length L1 is longer than length L2. Therefore, for example, it is easier to reduce the gate capacitance.

[0055] The length L1 is preferably 1.5 μm or more and 4 μm or less. The length L2 is preferably 1.0 μm or more and less than 1.5 μm.

[0056] like Figure 1 As shown, the semiconductor device 110 may further include a first conductive member 61. At least a portion of the second portion region 13b is located between the fourth electrode 54 and a portion of the first conductive member 61 in the second direction D2. At least a portion of the fifth semiconductor region 15 and the fourth semiconductor region 14 are located between the third electrode 53 and another portion of the first conductive member 61 in the second direction D2. The first conductive member 61 is electrically insulated from the third electrode 53 and from the fourth electrode 54. A portion of the insulating member 40 is disposed between the semiconductor device 10 and the first conductive member 61. The first conductive member 61 is, for example, a dummy gate. By providing the first conductive member 61, the saturation current value can be reduced, for example, compared to the case where the first conductive member 61 is not provided.

[0057] like Figure 1 As shown, in this example, the first conductive member 61 includes a first conductive portion 61a and a second conductive portion 61b. At least a portion of the second partial region 13b is located between the fourth electrode 54 and the second conductive portion 61b in the second direction D2. At least a portion of the fifth semiconductor region 15 and the fourth semiconductor region 14 are located between the third electrode 53 and the first conductive portion 61a in the second direction D2.

[0058] like Figure 1As shown, the third semiconductor region 13 may include a third partial region 13c. The third partial region 13c is located between the first semiconductor region 11 and the first conductive member 61 in the first direction D1. For example, the second conductive member 61b is located between the third partial region 13c and the first conductive member 61a in the first direction D1. The position of the second partial region 13b in the second direction D2 is between the position of the first partial region 13a in the second direction D2 and the position of the third partial region 13c in the second direction D2.

[0059] For example, the direction from the third electrode 53 to the first conductive portion 61a is along the second direction D2. For example, the direction from the fourth electrode 54 to the second conductive portion 61b is along the second direction D2. The first conductive portion 61a contains the material contained in the third electrode 53. The first conductive portion 61a is, for example, in the same layer as the third electrode 53. The second conductive portion 61b contains the material contained in the fourth electrode 54. The second conductive portion 61b is, for example, in the same layer as the fourth electrode 54.

[0060] like Figure 1 As shown, in this example, in the second direction D2, a portion of a fourth semiconductor region 14 exists between the second semiconductor region 12 and the first conductive member 61. This portion of the fourth semiconductor region 14 is connected to the second electrode 52. A portion of the insulating member 40 is connected to both the aforementioned portion of the fourth semiconductor region 14 and the first conductive member 61 (e.g., the first conductive portion 61a).

[0061] like Figure 1 As shown, multiple third electrodes 53 and multiple fourth electrodes 54 can be provided. The multiple third electrodes 53 are arranged along the second direction D2. The multiple fourth electrodes 54 are arranged along the second direction D2. Multiple first conductive components 61 can be provided. The multiple first conductive components 61 are arranged along the second direction D2.

[0062] like Figure 1 As shown, the semiconductor device 110 may include a control unit 70. The control unit 70 may include, for example, a drive circuit 70D and a power supply circuit 70P. A voltage (and current) for driving is supplied from the power supply circuit 70P to the drive circuit 70D. The voltage (and current) supplied to the electrodes by the drive circuit 70D is controlled (switched).

[0063] like Figure 1 As shown, the control unit 70 (e.g., drive circuit 70D) can supply a first drive signal DS1 to the third electrode 53. The control unit 70 (e.g., drive circuit 70D) can supply a second drive signal DS2 to the fourth electrode 54. The potentials of these electrodes (e.g., gate electrodes) are controlled by these drive signals. Thus, the turn-on and turn-off operations are performed.

[0064] The following is an example of the operation of the control unit 70.

[0065] Figure 3 (a) and Figure 3 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0066] The horizontal axis of these graphs represents time (tm). Figure 3 The vertical axis of (a) is the magnitude (height) of the first drive signal DS1. Figure 3 The vertical axis of (b) represents the magnitude (height) of the second drive signal DS2. These diagrams correspond to the first drive condition DC1 in the first action OP1. The first action OP1 corresponds, for example, to the turn-on action.

[0067] like Figure 3 As shown in (a), in the first action OP1, the first drive signal DS1 changes from the first potential V1 to a second potential V2, which is higher than the first potential V1. Figure 3 As shown in (b), in the first action OP1, the second drive signal DS2 changes from the third potential V3 to the fourth potential V4, which is higher than the third potential V3.

[0068] These potentials can be based on the second electrode potential E2 (refer to...). Figure 1 The potential is taken as a reference. The third potential V3 can be substantially the same as the first potential V1. The fourth potential V4 can be substantially the same as the second potential V2. In one example, the first potential V1 and the third potential V3 are -15V. In another example, the second potential V2 and the fourth potential V4 are +15V.

[0069] The potentials of the third electrode 53 and the fourth electrode 54 can be controlled by the first drive signal DS1 and the second drive signal DS2, thereby performing the switching action.

[0070] Let time t1 be the moment when the first driving signal DS1 changes from potential V1 to potential V2. Let time t2 be the moment when the second driving signal DS2 changes from potential V3 to potential V4. In the first driving condition DC1, the difference Δt1 (=t2-t1) between time t1 and time t2 is essentially 0. The potentials of the third electrode 53 and the fourth electrode 54 are substantially simultaneously controlled.

[0071] Figure 4 (a) and Figure 4 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0072] The horizontal axis of these graphs represents time (tm). Figure 4 The vertical axis of (a) is the magnitude (height) of the first drive signal DS1. Figure 4 The vertical axis of (b) represents the magnitude (height) of the second drive signal DS2. These graphs correspond to the second drive condition DC2 in the first action OP1. In the second drive condition DC2, time t1 is after time t2. The difference between time t1 and time t2, Δt1 (=t2-t1), is negative.

[0073] Figure 5 (a) and Figure 5 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0074] The horizontal axis of these graphs represents time (tm). Figure 5 The vertical axis of (a) is the magnitude (height) of the first drive signal DS1. Figure 5 The vertical axis of (b) represents the magnitude (height) of the second drive signal DS2. These graphs correspond to the third drive condition DC3 in the first action OP1. In the third drive condition DC3, time t1 is before time t2. The difference between time t1 and time t2, Δt1 (=t2-t1), is positive.

[0075] Figure 6 (a) and Figure 6 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0076] The horizontal axis of these graphs represents time (tm). Figure 6 (a) The vertical axis represents the magnitude (height) of the first drive signal DS1. Figure 6 The vertical axis of (b) represents the magnitude (height) of the second drive signal DS2. These graphs correspond to the fourth drive condition DC4 in the second action OP2. The second action OP2 corresponds, for example, to a disconnection action.

[0077] like Figure 6 As shown in (a), in the second action OP2, the first drive signal DS1 changes from the second potential V2 to the first potential V1. Figure 6 As shown in (b), in the second action OP2, the second drive signal DS2 changes from the fourth potential V4 to the third potential V3.

[0078] The potentials of the third electrode 53 and the fourth electrode 54 can be controlled by the first drive signal DS1 and the second drive signal DS2. This enables the disconnection operation.

[0079] The moment when the first driving signal DS1 changes from the second potential V2 to the first potential V1 is defined as time t3 (the third time). The moment when the second driving signal DS2 changes from the fourth potential V4 to the third potential V3 is defined as time t4 (the fourth time). In the fourth driving condition DC4, the difference Δt2 (=t4-t3) between time t3 and time t4 is substantially 0. The potentials of the third electrode 53 and the fourth electrode 54 are substantially simultaneously controlled.

[0080] Figure 7 (a) and Figure 7 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0081] The horizontal axis of these graphs represents time (tm). Figure 7 The vertical axis of (a) is the magnitude (height) of the first drive signal DS1. Figure 7 The vertical axis of (b) represents the magnitude (height) of the second drive signal DS2. These graphs correspond to the fifth drive condition DC5 in the second action OP2. In the fifth drive condition DC5, time t3 is after time t4. The difference between time t3 and time t4, Δt2 (=t4-t3), is negative.

[0082] Figure 8 (a) and Figure 8 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0083] The horizontal axis of these graphs represents time (tm). Figure 8 The vertical axis of (a) is the magnitude (height) of the first drive signal DS1. Figure 8 The vertical axis of (b) represents the magnitude (height) of the second drive signal DS2. These graphs correspond to the sixth drive condition DC6 in the first action OP1. In the sixth drive condition DC6, time t3 is before time t4. The difference between time t3 and time t4, Δt2 (=t4-t3), is positive.

[0084] Figure 9 This is a graph illustrating the characteristics of the semiconductor device according to the first embodiment.

[0085] Figure 9 The horizontal axis represents the difference Δt1 in the first action OP1. The vertical axis represents the conduction loss Eon. In this example, the conduction loss Eon is normalized. Figure 9 As shown, the turn-on loss Eon is smaller when the difference Δt1 is negative than when the difference Δt1 is positive. This can be attributed to, for example, the gate capacitance during switching being smaller when the difference Δt1 is negative compared to when the difference Δt1 is positive.

[0086] In this embodiment, it is preferable that the first time t1 (the moment when the first drive signal DS1 changes from the first potential V1 to the second potential V2) occurs before the second time t2 (the moment when the second drive signal DS2 changes from the third potential V3 to the fourth potential V4). In this case, the absolute value of the difference Δt1 between the first time t1 and the second time t2 is preferably 2 μs or more. This allows for a stable and low on-time loss Eon. The absolute value of the difference Δt1 is preferably, for example, 5 μs or less. This facilitates operation of the semiconductor device at a higher frequency. This is particularly advantageous, for example, when the semiconductor device is applied to inverters, etc.

[0087] Figure 10 This is a graph illustrating the characteristics of the semiconductor device according to the first embodiment.

[0088] Figure 10 The horizontal axis represents the difference Δt2 in the second action OP2. The vertical axis represents the cutoff loss Eoff. In this example, the cutoff loss Eoff is standardized. Figure 10 As shown, the cutoff loss Eoff is smaller when the difference Δt2 is positive. The cutoff loss Eoff is also smaller when the difference Δt2 is positive and its absolute value is less than 3 μm. This can be attributed to the smaller gate capacitance during switching.

[0089] In this embodiment, the third time t3 (the moment when the first drive signal DS1 changes from the second potential V2 to the first potential V1) is preferably after the fourth time t4 (the moment when the second drive signal DS2 changes from the fourth potential V4 to the third potential V3). Alternatively, the third time t3 may be substantially the same as the fourth time t4. Alternatively, when the third time t3 is before the fourth time t4, the absolute value of the difference between the third time t3 and the fourth time t4 is preferably 3 μs or less. Under this condition, a small cutoff loss Eoff can be stably obtained.

[0090] Figure 11 This is a graph illustrating the characteristics of a semiconductor device according to an example implementation.

[0091] Figure 11 The horizontal axis represents the switching characteristic SC1, which is the rate of change of current with respect to time (di / dt). In this example, the switching characteristic SC1 relates to the change between 20% and 80% of the current variation. The vertical axis represents the conduction loss Eon. Figure 11 The characteristics of the semiconductor device 110 described above and the semiconductor device 119 of the first reference example are shown in the diagram. As already explained, in the first reference example, the third semiconductor region 13 and the fourth electrode 54 are not provided. In this example, the p-type impurity concentration (carrier concentration) in the third semiconductor region 13 is 5.0 × 10⁻⁶. 15 (cm-3 ).like Figure 11 As shown, in semiconductor device 110, compared with semiconductor device 119, the balance between turn-on loss Eon and switching characteristics (di / dt) can be improved.

[0092] Figure 12 This is a graph illustrating the characteristics of a semiconductor device according to an example implementation.

[0093] Figure 12 The horizontal axis represents the switching characteristic SC2, which is the rate of change of voltage with respect to time (dv / dt). In this example, the switching characteristic SC2 is related to the change between 20% and 80% of the voltage change. The vertical axis represents the cutoff loss Eoff. Figure 12 The characteristics of the semiconductor device 110 and the semiconductor device 119 of the first reference example are shown in the figure. In this example, the p-type impurity concentration (carrier concentration) in the third semiconductor region 13 is 2.5 × 10⁻⁶. 15 (cm -3 ).like Figure 12 As shown, in semiconductor device 110, compared with semiconductor device 119, the balance between cutoff loss Eoff and switching characteristics (dv / dt) can be improved.

[0094] Thus, in this implementation, the balance between turn-on loss Eon and switching characteristics (e.g., di / dt) can be improved. For example, it is possible to suppress turn-on loss Eon while maintaining good switching characteristics (e.g., di / dt).

[0095] In this implementation, the balance between cutoff loss Eoff and switching characteristics (e.g., dv / dt) can be improved. For example, it is possible to suppress cutoff loss Eoff while maintaining good switching characteristics (e.g., dv / dt).

[0096] (Second Implementation)

[0097] The second embodiment relates to a driving device for a semiconductor device. The driving device corresponds to the control unit 70 described above. The driving device (control unit 70) is capable of performing the above-described operations on the semiconductor device 110.

[0098] In this embodiment, the semiconductor component includes, for example, silicon. The semiconductor component may also include SiC or GaN, etc. The first electrode 51 includes, for example, at least one selected from the group consisting of aluminum, nickel, and titanium. The second electrode 52 includes, for example, at least one selected from the group consisting of aluminum, nickel, and titanium. The third electrode 53 and the fourth electrode 54 include, for example, polycrystalline silicon or amorphous silicon. The first conductive component 61 includes, for example, at least one selected from the group consisting of aluminum, nickel, and titanium. The insulating component 40 includes, for example, at least one selected from the group consisting of oxygen and nitrogen, and silicon.

[0099] In this embodiment, the carrier concentration of the first conductivity type in the first semiconductor region 11 is, for example, 8.0 × 10⁻⁶. 11 / cm 3 Above 1.3×10 13 / cm 3 The carrier concentration of the first conductivity type in the second semiconductor region 12 is, for example, 1.0 × 10⁻⁶. 17 / cm 3 Above 1.0×10 21 / cm 3 The carrier concentration of the second conductivity type in the third semiconductor region 13 is, for example, 5.0 × 10⁻⁶. 14 / cm 3 Above 1.0×10 17 / cm 3 The carrier concentration of the second conductivity type in the fourth semiconductor region 14 is, for example, 1.0 × 10⁻⁶. 15 / cm 3 Above 1.0×10 17 / cm 3 The carrier concentration of the first conductivity type in the fifth semiconductor region 15 is, for example, 1.0 × 10⁻⁶. 15 / cm 3 Above 2.0×10 17 / cm 3 The carrier concentration of the second conductivity type in the sixth semiconductor region 16 is, for example, 1.0 × 10⁻⁶. 15 / cm 3 Above 1.0×10 18 / cm 3 The carrier concentration of the first conductivity type in the seventh semiconductor region 17 is, for example, 1.0 × 10⁻⁶. 15 / cm 3 Above 1.0×10 17 / cm 3 the following.

[0100] In this implementation, information related to the shape of the semiconductor region is obtained, for example, by observation using an electron microscope. Information related to the impurity concentration in the semiconductor region is obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry). Information related to the carrier concentration in the semiconductor region is obtained, for example, by SCM (Scanning Capacitance Microscopy).

[0101] The implementation method may include the following components (e.g., technical solutions).

[0102] (Component 1)

[0103] A semiconductor device, comprising:

[0104] Electrode 1;

[0105] The semiconductor component includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the second conductivity type.

[0106] The position of the first semiconductor region in the first direction from the first electrode to the first semiconductor region is between the position of the first electrode in the first direction and the position of the second semiconductor region in the first direction.

[0107] The third semiconductor region comprises a first portion region and a second portion region, wherein the second portion region is located between the first semiconductor region and the second semiconductor region in the first direction.

[0108] At least a portion of the fourth semiconductor region is located between the second portion region and the second semiconductor region in the first direction.

[0109] The fifth semiconductor region is located between the second portion region and at least a portion of the fourth semiconductor region in the first direction.

[0110] The sixth semiconductor region is located between the first electrode and the first semiconductor region in the first direction.

[0111] The second electrode is electrically connected to the aforementioned second semiconductor region.

[0112] The third electrode, wherein the first portion of the region is located between the first semiconductor region and the third electrode in the first direction, and in the second direction intersecting the first direction, the third electrode overlaps with the second semiconductor region, at least a portion of the fourth semiconductor region, and the fifth semiconductor region.

[0113] The fourth electrode is located between the first partial region and the third electrode in the first direction, and the direction from the fourth electrode to the second partial region is along the second direction.

[0114] An insulating component, at least a portion of which is disposed between the semiconductor component and the third electrode, between the semiconductor component and the fourth electrode, and between the third electrode and the fourth electrode.

[0115] (Component 2)

[0116] According to the semiconductor device described in configuration 1, wherein...

[0117] The third electrode mentioned above does not overlap with the second part of the region mentioned above in the second direction.

[0118] (Component 3)

[0119] According to configuration 1 or configuration 2, in the semiconductor device, wherein...

[0120] The aforementioned insulating component includes a first insulating region disposed between the third electrode and the fourth electrode.

[0121] The first insulating region overlaps with a portion of the fifth semiconductor region in the second direction.

[0122] The first insulating region does not overlap with the third semiconductor region in the second direction.

[0123] (Component 4)

[0124] According to any one of the semiconductor devices comprising 1 to 3, wherein...

[0125] The second distance between the fourth electrode and the third electrode along the first direction is more than 10 nm and less than 360 nm.

[0126] (Component 5)

[0127] According to any one of the following semiconductor devices, wherein...

[0128] The aforementioned semiconductor component includes a first boundary between the second portion region and the fifth semiconductor region.

[0129] The fourth electrode mentioned above includes the second end portion on the side of the third electrode mentioned above.

[0130] The first distance along the first direction between the position of the first boundary in the first direction and the position of the second end in the first direction is more than 10 nm and less than 200 nm.

[0131] (Composition 6)

[0132] According to any one of the semiconductor devices comprising 1 to 5, wherein...

[0133] The carrier concentration of the first conductivity type in the second semiconductor region is higher than the carrier concentration of the first conductivity type in the first semiconductor region.

[0134] (Component 7)

[0135] According to the semiconductor device described in configuration 6, wherein...

[0136] The carrier concentration of the first conductivity type in the fifth semiconductor region is higher than the carrier concentration of the first conductivity type in the first semiconductor region.

[0137] (Composition 8)

[0138] According to the semiconductor device described in 6 or 7, wherein...

[0139] The aforementioned semiconductor component also includes the seventh semiconductor region of the first conductivity type.

[0140] The seventh semiconductor region is located between the sixth semiconductor region and the first semiconductor region in the first direction.

[0141] The carrier concentration of the first conductivity type in the seventh semiconductor region is higher than the carrier concentration of the first conductivity type in the first semiconductor region.

[0142] (Composition 9)

[0143] According to the semiconductor device comprising any one of 1 to 8, wherein,

[0144] It also has a first conductive component.

[0145] At least a portion of the second region is located between the fourth electrode and a portion of the first conductive component in the second direction.

[0146] At least a portion of the fifth semiconductor region and the fourth semiconductor region are located between the third electrode and another portion of the first conductive component in the second direction.

[0147] The first conductive component is electrically insulated from the third electrode and from the fourth electrode.

[0148] A portion of the aforementioned insulating component is disposed between the aforementioned semiconductor component and the aforementioned first conductive component.

[0149] (Composition 10)

[0150] According to the semiconductor device described in configuration 9, wherein...

[0151] The aforementioned first conductive component includes a first conductive portion and a second conductive portion.

[0152] At least a portion of the second region is located between the fourth electrode and the second conductive portion in the second direction.

[0153] At least a portion of the fifth semiconductor region and the fourth semiconductor region are located between the third electrode and the first conductive portion in the second direction.

[0154] (Composition 11)

[0155] According to the semiconductor device comprising 9 or 10, wherein,

[0156] In the second direction described above, a portion of the fourth semiconductor region is located between the second semiconductor region and the first conductive component.

[0157] (Composition 12)

[0158] According to the semiconductor device comprising 11, wherein...

[0159] A portion of the aforementioned insulating component is connected to a portion of the aforementioned fourth semiconductor region and the aforementioned first conductive component.

[0160] (Composition 13)

[0161] According to any one of the following configurations, the semiconductor device,

[0162] It also includes a control unit that can supply a first drive signal to the third electrode and a second drive signal to the fourth electrode.

[0163] In the first action, the first driving signal changes from a first potential to a second potential that is higher than the first potential.

[0164] In the first action described above, the second driving signal changes from the third potential to a fourth potential that is higher than the third potential.

[0165] (Composition 14)

[0166] According to the semiconductor device described in configuration 13

[0167] The first moment when the first driving signal changes from the first potential to the second potential is before the second moment when the second driving signal changes from the third potential to the fourth potential.

[0168] (Composition 15)

[0169] According to the semiconductor device described in configuration 14

[0170] The absolute value of the difference between the first time point and the second time point mentioned above is more than 2 μs and less than 5 μs.

[0171] (Composition 16)

[0172] According to any one of 13 to 15, the semiconductor device

[0173] In the second action, the first driving signal changes from the second potential to the first potential.

[0174] In the second action described above, the second driving signal changes from the fourth potential to the third potential.

[0175] (Composition 17)

[0176] According to the semiconductor device described in configuration 16

[0177] The third moment when the first driving signal changes from the second potential to the first potential occurs after the fourth moment when the second driving signal changes from the fourth potential to the third potential.

[0178] (Composition 18)

[0179] According to the semiconductor device described in configuration 17

[0180] The absolute value of the difference between the third time point and the fourth time point mentioned above is less than 3 μs.

[0181] (Composition 19)

[0182] According to any one of 13 to 18, the semiconductor device

[0183] The third potential mentioned above is essentially the same as the first potential mentioned above.

[0184] The fourth potential mentioned above is essentially the same as the second potential mentioned above.

[0185] (Composition 20)

[0186] According to any one of the following configurations, a semiconductor device,

[0187] The length of the third electrode along the first direction is longer than the length of the fourth electrode along the first direction.

[0188] According to the implementation method, a semiconductor device capable of suppressing losses can be provided.

[0189] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, any specific configuration of the elements included in a semiconductor device, such as electrodes, semiconductor components, insulating components, conductive components, insulating portions, and control portions, is included within the scope of the present invention, provided that a person skilled in the art appropriately selects from the known scope to similarly implement the present invention and obtain the same effects.

[0190] Furthermore, any combination of any two or more elements of each specific example within the technically possible range is included within the scope of this invention, as long as it contains the essence of the invention.

[0191] In addition, all semiconductor devices that can be appropriately designed and implemented by those skilled in the art based on the semiconductor devices described above as embodiments of the present invention, as long as they contain the spirit of the present invention, fall within the scope of the present invention.

[0192] In addition, within the scope of the present invention, various modifications and variations can be conceived by those skilled in the art, and it should be understood that these modifications and variations also fall within the scope of the present invention.

[0193] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: Electrode 1; The semiconductor component includes a first semiconductor region of a first conductivity type, a second semiconductor region of a first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of a second conductivity type, a fifth semiconductor region of a first conductivity type, and a sixth semiconductor region of a second conductivity type. The position of the first semiconductor region in the first direction from the first electrode to the first semiconductor region is between the position of the first electrode in the first direction and the position of the second semiconductor region in the first direction. The third semiconductor region comprises a first portion region and a second portion region, wherein the second portion region is located between the first semiconductor region and the second semiconductor region in the first direction. At least a portion of the fourth semiconductor region is located between the second portion region and the second semiconductor region in the first direction. The fifth semiconductor region is located between the second portion region and at least a portion of the fourth semiconductor region in the first direction. The sixth semiconductor region is located between the first electrode and the first semiconductor region in the first direction. The second electrode is electrically connected to the aforementioned second semiconductor region; The third electrode, wherein the first portion of the region is located between the first semiconductor region and the third electrode in the first direction, and in the second direction intersecting the first direction, the third electrode overlaps with at least a portion of the second semiconductor region, the fourth semiconductor region, and the fifth semiconductor region. The fourth electrode is located between the first partial region and the third electrode in the first direction, and the direction from the fourth electrode to the second partial region is along the second direction. An insulating component, at least a portion of which is disposed between the semiconductor component and the third electrode, between the semiconductor component and the fourth electrode, and between the third electrode and the fourth electrode; and The control unit is capable of supplying a first drive signal to the third electrode and a second drive signal to the fourth electrode. In the first action, the first driving signal changes from a first potential to a second potential that is higher than the first potential. In the first action described above, the second driving signal changes from the third potential to a fourth potential that is higher than the third potential. The first moment when the first driving signal changes from the first potential to the second potential occurs before the second moment when the second driving signal changes from the third potential to the fourth potential. In the second action, the first driving signal changes from the second potential to the first potential. In the second action described above, the second driving signal changes from the fourth potential to the third potential. The third moment when the first driving signal changes from the second potential to the first potential occurs after the fourth moment when the second driving signal changes from the fourth potential to the third potential.

2. The semiconductor device according to claim 1, wherein, The aforementioned insulating component includes a first insulating region disposed between the third electrode and the fourth electrode. The first insulating region overlaps with a portion of the fifth semiconductor region in the second direction. The first insulating region does not overlap with the third semiconductor region in the second direction.

3. The semiconductor device according to claim 1, wherein, It also has a first conductive component. At least a portion of the second region is located between the fourth electrode and a portion of the first conductive component in the second direction. At least a portion of the fifth semiconductor region and the fourth semiconductor region are located between the third electrode and another portion of the first conductive component in the second direction. The first conductive component is electrically insulated from the third electrode and from the fourth electrode. A portion of the aforementioned insulating component is disposed between the aforementioned semiconductor component and the aforementioned first conductive component.

4. The semiconductor device according to claim 3, wherein, The aforementioned first conductive component includes a first conductive portion and a second conductive portion. At least a portion of the second region is located between the fourth electrode and the second conductive portion in the second direction. At least a portion of the fifth semiconductor region and the fourth semiconductor region are located between the third electrode and the first conductive portion in the second direction.

5. The semiconductor device according to claim 1, wherein, The absolute value of the difference between the first time point and the second time point mentioned above is more than 2 μs and less than 5 μs.

6. The semiconductor device according to claim 1, wherein, The length of the third electrode along the first direction is longer than the length of the fourth electrode along the first direction.

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