Medium voltage transistor and method of making the same

Abstract

The present application discloses a medium voltage transistor and a method for fabricating the same. The method for fabricating the medium voltage transistor includes providing a substrate, defining a gate predetermined region on the substrate, forming a mask layer to cover only a part of the gate predetermined region, performing a first ion implantation process to implant dopants into the substrate on both sides of the mask layer to form two first shallow doped regions, removing the mask layer, forming a gate overlapping the whole gate predetermined region, forming two second shallow doped regions each located in one of the first shallow doped regions, forming two source / drain doped regions each located in one of the second shallow doped regions, and forming two metal silicide layers each covering and contacting one of the source / drain doped regions.

Description

Technical Field

[0001] This invention relates to a medium-voltage transistor having two shallowly doped regions surrounding the source / drain doped regions and a method for fabricating the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the multiple material layers to form circuit elements on the semiconductor substrate.

[0003] As the integration density of semiconductor devices increases, more components can be integrated into a given area. However, as the minimum structure size shrinks, additional problems arise in each fabrication process that need to be solved. For example, when removing the dielectric layer, the gate dielectric layer is etched, causing leakage current in the subsequently completed transistor. Summary of the Invention

[0004] In view of this, the present invention provides a new transistor structure and manufacturing process to effectively avoid leakage current problems.

[0005] According to a preferred embodiment of the present invention, a medium-voltage transistor includes a substrate, a gate disposed on the substrate, a gate dielectric layer disposed between the substrate and the gate, a first shallow doped region buried in the substrate and extending below the gate, a second shallow doped region buried within the first shallow doped region, the first shallow doped region surrounding the second shallow doped region, wherein the second shallow doped region has a first edge, a source / drain doped region buried within the second shallow doped region, the second shallow doped region surrounding the source / drain doped region, wherein the source / drain doped region has a second edge, a metal silicide layer covering and contacting the source / drain doped region, wherein the metal silicide layer has an end located between the first edge and the second edge.

[0006] According to another preferred embodiment of the present invention, a method for fabricating a medium-voltage transistor includes providing a substrate on which a gate predetermined region is defined, then forming a mask layer that covers only a portion of the gate predetermined region, then performing a first ion implantation process to implant dopants in the substrate on both sides of the mask layer to form two first shallow doped regions, then removing the mask layer to form a gate, wherein the gate completely overlaps the gate predetermined region, then forming two second shallow doped regions, each located within one of the first shallow doped regions, then forming two source / drain doped regions, each located within one of the second shallow doped regions, and finally forming two metal silicide layers, each covering and contacting one of the source / drain doped regions.

[0007] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. However, the following preferred embodiments and drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0008] Figures 1 to 4 This is a schematic diagram illustrating a method for manufacturing a medium-voltage transistor according to a preferred embodiment of the present invention.

[0009] Explanation of main component symbols

[0010] 10: Base

[0011] 11: Doped Well

[0012] 12: Mask layer

[0013] 14: Gate dielectric layer

[0014] 16: Gate

[0015] 18: First gap wall

[0016] 20: Second spacer wall

[0017] 22: Depression

[0018] 24: Metal silicide layer

[0019] 24a: terminal

[0020] 100: Medium-voltage transistor

[0021] A: Gate Pre-defined Region

[0022] E1: First Edge

[0023] E2: Second Edge

[0024] E3: Third Edge

[0025] E4: Fourth Edge

[0026] I1: First ion implantation fabrication process

[0027] I2: Second ion implantation process

[0028] I3: Third ion implantation process

[0029] LDD1: First shallow doped region

[0030] LDD2: Second shallow doped region

[0031] S: Axis of symmetry

[0032] S / D: Source / Drain Doped Region

[0033] W: Width

[0034] X: Second direction

[0035] Y: First direction Detailed Implementation

[0036] Figures 1 to 4 This illustration depicts a method for fabricating a medium-voltage transistor according to a preferred embodiment of the present invention. Figure 1 As shown, a substrate 10 is first provided, on which a gate pre-drilled region A is defined. A doped well 11 is then formed in the substrate 10. Next, a mask layer 12 is formed, covering only a portion of the gate pre-drilled region A. The mask layer 12 can be a material layer such as photoresist, silicon nitride, or silicon oxynitride. Specifically, the gate pre-drilled region A has a symmetry axis S, and the symmetry axis of the mask layer 12 overlaps with the symmetry axis S of the gate pre-drilled region A. That is, the mask layer 12 is located in the middle of the gate pre-drilled region A, and the width W of the mask layer 12 is smaller than that of the gate pre-drilled region A. Next, a first ion implantation fabrication process I1 is performed, using the mask layer 12 as a mask, to implant dopants into the substrate 10 on both sides of the mask layer 12 to form two first shallowly doped regions LDD1.

[0037] like Figure 2 As shown, after removing the mask layer 12, a gate dielectric layer 14 is formed to fully cover the substrate 12. Then, a gate 16 is formed on the gate dielectric layer 14, and the gate 16 covers the entire gate predetermined region A. At this time, part of the first shallow doped region LDD1 will be located directly below the gate 16. In other words, part of the first shallow doped region LDD1 will overlap with the gate 16. It is worth noting that since the position of the first shallow doped region LDD1 is defined by the aforementioned mask layer 12, the size of the overlapping area between the first shallow doped region LDD1 and the gate 16 can be controlled by adjusting the width W of the mask layer 12. Next, two first spacer walls 18 are formed on both sides of the gate 16. Then, a second ion implantation process I2 is performed. Using the gate 16 and the first spacer walls 18 as masks, the implanted dopant penetrates the gate dielectric layer 14 and forms two second shallow doped regions LDD2 in the substrate 10. The second shallow doped regions LDD2 are located on both sides of the gate 16 and are each located in one of the first shallow doped regions LDD1. The first shallow doped region LDD1 surrounds the second shallow doped region LDD2. The range of the first shallow doped region LDD1 is larger than that of the second doped region LDD2.

[0038] like Figure 3As shown, two second spacer walls 20 are formed, each located on a first spacer wall 18. Then, a third ion implantation process I3 is performed, using the gate 16, the first spacer wall 18 and the second spacer wall 20 as masks. Dopants are implanted so that the dopants penetrate the gate dielectric layer 14 and enter the substrate 10 to form two source / drain doped regions S / D located on both sides of the gate 16. The two source / drain doped regions S / D are each buried in a second shallow doped region LDD2. In addition, the second shallow doped region LDD2 surrounds the source / drain doped regions S / D.

[0039] like Figure 4 As shown, removing the gate dielectric layer 14 located directly above the source / drain doped region S / D exposes the source / drain doped region S / D. That is, the gate dielectric layer 14 not covered by the gate 16, the first spacer 18, and the second spacer 20 is removed. When removing the gate dielectric layer 14 located directly above the source / drain doped region S / D, a portion of the gate dielectric layer 14 below the second spacer 20 is also uncontrollably removed, causing a depression 22 in the gate dielectric layer 14 below the second spacer 20. This depression 22 may even extend below the first spacer 18. A metal silicide fabrication process is then performed to form two metal silicide layers 24, each covering and contacting one of the source / drain doped regions S / D. The metal silicide layers 24 are not only directly above the source / drain doped region S / D but also formed in the aforementioned depression 22, meaning they extend beyond the area directly above the source / drain doped region S / D. The medium-voltage transistor 100 of the present invention is now complete. The method for manufacturing the medium-voltage transistor 100 of the present invention is applicable to both N-type and P-type transistors.

[0040] Figure 4 The illustration shows a medium-voltage transistor manufactured using the method provided by the present invention. The medium-voltage transistor 100 of the present invention can be an N-type transistor or a P-type transistor. The medium-voltage transistor 100 includes a substrate 10, a first direction Y defined as perpendicular to the upper surface of the substrate 10, a second direction X defined parallel to the upper surface of the substrate 10, a gate disposed 16 on the substrate 10, a gate dielectric layer 14 disposed between the substrate 10 and the gate 16, a first shallow doped region LDD1 buried in the substrate 10 and extending below the gate 16, a second shallow doped region LDD2 buried in the first shallow doped region LDD1, the first shallow doped region LDD1 surrounding the second shallow doped region LDD2, wherein the second shallow doped region LDD2 has a first edge E1, a source / drain doped region S / D buried in the second shallow doped region LDD2, the second shallow doped region LDD2 surrounding the source / drain doped region S / D, wherein the source / drain doped region S / D has a second edge E2, and both the first edge E1 and the second edge E2 are parallel to the first direction Y.

[0041] A metal silicide layer 24 covers and contacts the source / drain doped region S / D, wherein the metal silicide layer 24 has an end 24a, and the end 24a of the metal silicide layer 24 contacts the gate dielectric layer 14. It is worth noting that the end 24a is located between the first edge E1 and the second edge E2. Furthermore, a first gap wall 18 contacts the gate 16 and is located on one side of the gate 16, another first gap wall 18 contacts the gate 16 and is located on the other side of the gate 16, a second gap wall 20 contacts the first gap wall 18 located on one side of the gate 16, and another second gap wall 20 contacts the first gap wall 18 located on the other side of the gate 16. The first gap wall 18 and the second gap wall 20 are both completely located on the gate dielectric layer 14. The width of the gate dielectric layer 14 is greater than the width of the gate 16. The width of the gate dielectric layer 14 and the width of the gate 16 are both parallel to the second direction X. The second direction X is not only parallel to the upper surface of the substrate 10, but also along the direction from one source / drain doped region S / D to another source / drain doped region S / D. The width of the gate dielectric layer 14 is equal to the width of the gate 16 plus the width of the two first gap walls 18 and the two second gap walls 20.

[0042] Furthermore, the gate 16 has a third edge E3 parallel to the first direction Y, and the first shallowly doped region LDD1 has a fourth edge E4 parallel to the first direction Y. According to a preferred embodiment of the invention, along the second direction X, the distance between the third edge E3 and the fourth edge E4 is less than half the width of the gate 16. Additionally, the operating voltage of the medium-voltage transistor 100 of the present invention can include both the operating voltage under normal operating conditions and the operating voltage under underdrive conditions. For example, the operating voltage of the medium-voltage transistor 100 can be between 1.8 and 9 volts, while the thickness of the gate dielectric layer 14 is preferably between 100 angstroms and 250 angstroms.

[0043] The first shallow-doped region LDD1 has a first dopant concentration, the second shallow-doped region LDD2 has a second dopant concentration, and the source / drain doped region S / D has a third dopant concentration, the third dopant concentration being greater than the second dopant concentration, and the second dopant concentration being greater than the first dopant concentration. For example, the first dopant concentration is between 1E17 and 5E18 cm⁻¹. -3 The concentration of the second dopant is between 5E18 and 9E18 cm⁻¹. -3 The concentration of the third dopant is between 5E18 and 9E20 cm⁻¹. -3In other words, the source / drain doped region S / D of this invention is surrounded by two shallow doped regions, and the depth of the first shallow doped region LDD1 is greater than the depth of the second shallow doped region LDD2, and the depth of the second shallow doped region LDD2 is greater than the depth of the source / drain doped region S / D. In a typical transistor, the depth of the shallow doped region is less than that of the source / drain doped region.

[0044] As mentioned earlier in the fabrication process of the medium-voltage transistor 100, the metal silicide layer 24 is formed not only directly above the source / drain doped region S / D, but also in the recess 22 of the gate dielectric layer 14, so that the end 24a of the metal silicide layer 24 extends directly below the second spacer wall 20. At this time, if there is no second shallow doped region LDD2, the difference in dopant concentration between the source / drain doped region S / D and the first shallow doped region LDD1 is too large, which will cause electron breakdown at the recess 22 and cause leakage current. In this invention, a second shallow doped region LDD2 is specially formed with a dopant concentration between the dopant concentration of the source / drain doped region S / D and the dopant concentration of the first shallow doped region LDD1, and the end 24a does not exceed the first edge E1 of the second shallow doped region LDD2, which can effectively prevent leakage current from occurring.

[0045] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A medium-voltage transistor, comprising: Base; A gate is disposed on the substrate; A gate dielectric layer is disposed between the substrate and the gate; A first shallowly doped region is buried in the substrate and extends below the gate. A second shallow doped region is embedded within the first shallow doped region, the first shallow doped region surrounding the second shallow doped region, wherein the second shallow doped region has a first edge; A source / drain doped region is buried within the second shallow doped region, the second shallow doped region surrounding the source / drain doped region, wherein the source / drain doped region has a second edge; as well as A metal silicide layer covers and contacts a portion of the source / drain doped region and the second shallow doped region. The metal silicide layer has an end located between the first edge and the second edge, and the end is in contact with the gate dielectric layer. The first shallow doped region has a first dopant concentration, the second shallow doped region has a second dopant concentration, and the source / drain doped region has a third dopant concentration, which is greater than the second dopant concentration and the second dopant concentration is greater than the first dopant concentration.

2. The medium-voltage transistor of claim 1, further comprising: The first gap wall contacts the gate and is located on one side of the gate; The second gap wall contacts the first gap wall, wherein both the first gap wall and the second gap wall are completely located on the gate dielectric layer, and the width of the gate dielectric layer is greater than the width of the gate.

3. The medium-voltage transistor of claim 1, wherein the first direction is defined as perpendicular to the upper surface of the substrate, and both the first edge and the second edge are parallel to the first direction.

4. The medium-voltage transistor of claim 1, wherein the first direction is defined as perpendicular to the upper surface of the substrate, the second direction is defined as parallel to the upper surface of the substrate, the gate has a third edge parallel to the first direction, the first lightly doped region has a fourth edge parallel to the first direction, and the distance between the third edge and the fourth edge along the second direction is less than half the width of the gate.

5. The medium-voltage transistor of claim 1, wherein the thickness of the gate dielectric layer is between 100 angstroms and 250 angstroms.

6. The medium-voltage transistor of claim 1, wherein the operating voltage of the medium-voltage transistor is between 1.8 and 9 volts.

7. The medium-voltage transistor of claim 1, wherein the first dopant concentration is between 1E17 and 5E18 cm⁻¹. -3 The concentration of the second dopant is between 5E18 and 9E18 cm⁻¹. -3 The concentration of the third dopant is between 5E18 and 9E20 cm⁻¹. -3 between.

8. A method for manufacturing a medium-voltage transistor, comprising: A substrate is provided on which a gate predetermined region is defined; The mask layer is formed to cover only a portion of the predetermined area of ​​the gate; A first ion implantation process is performed, using the mask layer as the first mask, and dopants are implanted into the substrate on both sides of the mask layer to form two first shallow doped regions; After removing the mask layer, a gate dielectric layer and a gate are formed, wherein the gate dielectric layer completely covers the substrate, the gate is located above the gate dielectric layer, and the gate overlaps the entire predetermined area of ​​the gate. Two second shallow-doped regions are formed, each located within one of the two first shallow-doped regions, wherein each second shallow-doped region has a first edge; Two source / drain doped regions are formed, each located within one of the two second shallow doped regions, and each of the source / drain doped regions has a second edge; as well as Two metal silicide layers are formed, each covering and contacting one of the two source / drain doped regions, and each covering and contacting a portion of the corresponding second shallow doped region. Each metal silicide layer has an end located between the corresponding first edge and second edge, and the end contacts the gate dielectric layer. The first shallow doped region has a first dopant concentration, the second shallow doped region has a second dopant concentration, and the source / drain doped region has a third dopant concentration, the third dopant concentration being greater than the second dopant concentration, and the second dopant concentration being greater than the first dopant concentration.

9. The method for manufacturing a medium-voltage transistor as described in claim 8, further comprising: After the gate is formed, two first gap walls are formed on both sides of the gate; A second ion implantation process is performed, using the gate and the two first spacer walls as a second mask. After the implanted dopant penetrates the gate dielectric layer, the two second shallow doped regions are formed. Two second gap walls are formed on each of the first gap walls; A third ion implantation process is performed, using the gate, the two first spacer walls, and the two second spacer walls as a third mask. After the implanted dopant penetrates the gate dielectric layer, the two source / drain doped regions are formed. as well as Before forming the two metal silicide layers, and after forming the two source / drain doped regions, the gate dielectric layer located directly above the two source / drain doped regions is removed.

10. The method for manufacturing a medium-voltage transistor as claimed in claim 8, wherein the first direction is defined as perpendicular to the upper surface of the substrate, and the first edge and the second edge are both parallel to the first direction.

11. The method of fabricating a medium-voltage transistor as claimed in claim 8, wherein the thickness of the gate dielectric layer is between 100 angstroms and 250 angstroms.

12. The method for fabricating a medium-voltage transistor as described in claim 8, wherein the first dopant concentration is between 1E17 and 5E18 cm⁻¹. -3 The concentration of the second dopant is between 5E18 and 9E18 cm⁻¹. -3 The concentration of the third dopant is between 5E18 and 9E20 cm⁻¹. -3 between.

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