A drive circuit, method and power supply system

Abstract

The application discloses a driving circuit, a method and a power supply system, which comprises a first current mirror, a second current mirror, a first switch, a second switch, a gate-drain detection circuit and a power tube; the first detection end of the gate-drain detection circuit is connected with the gate of the power tube; the second detection end of the gate-drain detection circuit is connected with the drain of the power tube; the output end of the gate-drain detection circuit is connected with the first input end of the first current mirror; the second input end of the first current mirror is connected with the first output end of the first current mirror; the third input end of the first current mirror is connected with the first end of the first switch; the output end of the first current mirror is grounded; the input end of the second current mirror is connected with a voltage source; the second output end of the second current mirror is connected with the first end of the second switch; the second end of the first switch is connected with the gate of the power tube; and the second end of the second switch is connected with the gate of the power tube. By adopting the embodiment of the application, the control process of the power tube driving can be simplified.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more particularly to a drive circuit, method, and power supply system. Background Technology

[0002] like Figure 1 The diagram shows a schematic of a driving circuit provided by the prior art. Current driving circuits reduce switching delay by combining logic control signals to detect the gate voltage Vg and drain voltage Vout of the corresponding power transistor MN0. Then, auxiliary charging and discharging circuits are activated via K3 and K4 to accelerate the entry or exit of the switching transistor MN0 from the plateau effect operating region, thereby reducing switching delay. Without auxiliary charging and discharging circuits, the turn-on / turn-off of the switching transistor is entirely determined by the charging current Ichg and the discharging current Idis. If these two currents are set to small values ​​due to output slew rate requirements, the turn-on and turn-off delays become significant.

[0003] like Figure 2 The diagram illustrates the Miller plateau effect during the turn-on and turn-off process, as provided by existing technology. When the power transistor MN0 needs to be turned off, the logic signal CMD_P changes from high to low, and CMD_N changes from low to high. Switch K2 opens, and the discharge current Idis discharges through the gate of the power transistor MN0, causing the gate voltage Vg to decrease slowly. After a delay time Td1, Vg drops to Vm, entering the Miller plateau region. At this point, the output voltage Vout begins to rise. After Vout rises to a certain value and exits the Miller plateau region, the gate voltage continues to be discharged to 0 by the discharge current Idis through T2. When the power switch needs to be turned on, the logic signal CMD_P changes from low to high, and CMD_N changes from high to low. Switch K1 opens, and the charging current Ichg charges the gate of the power transistor MN0, causing the gate voltage Vg to increase slowly. After a delay time Td2, Vg rises to Vm, entering the Miller plateau region. At this point, the output voltage Vout begins to decrease. After Vout drops to a certain value and exits the Miller plateau region, the gate voltage continues to be charged to the supply voltage by the charging current Ichg through T3. When the charging and discharging currents Ichg and Idis are relatively small due to the output slew rate requirements, the turn-on and turn-off delay times Td1 and Td2 are relatively large.

[0004] When the power switch needs to be turned on, the logic signal CMD_P changes from low to high, and CMD_N changes from high to low, opening switches K1, K3, and K5. At this time, the gate / drain detection circuit detects that the gate voltage Vg is lower than the threshold Vth2, generating an auxiliary discharge current Ic_aux1 to charge the gate of power transistor MN0. After a delay time Td2, the gate voltage Vg rises to Vm, and Ic_aux1 decreases to 0. The output voltage Vout then begins to decrease at the set slew rate. After a time Tf, power transistor MN0 begins to exit the Miller plateau region, and the gate voltage Vg continues to be charged by the discharge current Ichg. When the gate / drain detection circuit detects that Vout is less than the set threshold Vth1, it generates an auxiliary discharge current Ic_aux2, quickly pulling Vg back to the supply voltage, and power transistor MN0 is fully turned on. To achieve slew rate regulation, this existing technology requires the combination of multiple logic signals, making control complex. Summary of the Invention

[0005] This invention provides a driving circuit, method, and power supply system to solve the technical problem of complex control of power transistor drive in the prior art while satisfying slew rate regulation.

[0006] To solve the above-mentioned technical problems, embodiments of the present invention provide a driving circuit, including: a first current mirror, a second current mirror, a first switch, a second switch, a gate-drain detection circuit, and a power transistor; The first detection terminal of the gate-drain detection circuit is connected to the gate of the power transistor. The second detection terminal of the gate-drain detection circuit is connected to the drain of the power transistor; The output terminal of the gate leakage detection circuit is connected to the first input terminal of the first current mirror. The second input terminal of the first current mirror is connected to the first output terminal of the second current mirror; The third input terminal of the first current mirror is connected to the first terminal of the first switch; The output terminal of the first current mirror is grounded; The input terminal of the second current mirror is connected to a voltage source; The second output terminal of the second current mirror is connected to the first terminal of the second switch; The second terminal of the first switch is connected to the gate of the power transistor; The second terminal of the second switch is connected to the gate of the power transistor; The gate-drain detection circuit is used to generate a drive current based on the gate voltage and drain voltage of the power transistor. The first current mirror is used to copy the drive current received at the first input terminal to the second input terminal and the third input terminal; The second current mirror is used to copy the current from the first output terminal to the second output terminal.

[0007] This invention uses only one gate-drain detection circuit to detect the voltage at the gate and source of the power transistor, reducing the use of detection circuits. In addition, the gate-drain detection circuit only outputs a drive current to control the first and second current mirrors. Under the condition of slew rate regulation, it can be used as an auxiliary current source to cooperate with the first and second switching transistors to charge and discharge the gate of the power transistor, without using logic signals. Therefore, the control process of driving the power transistor is greatly simplified.

[0008] Furthermore, the driving circuit also includes: a first current source; The positive terminal of the first current source is grounded; The negative terminal of the first current source is connected to the first terminal of the first switch.

[0009] The first current source of the present invention can be used as the main discharge path and is connected in parallel with the first current mirror. Under the condition of slew rate regulation, it works together with the first switch to discharge the power transistor. This eliminates the need for multiple switches to receive logic signal control, thus simplifying the control process of power transistor driving.

[0010] Furthermore, the driving circuit also includes: a second current source; The negative terminal of the second current source is connected to the voltage source; The positive terminal of the second current source is connected to the first terminal of the second switch.

[0011] The second current source of the present invention can be used as the main charging circuit and is connected in parallel with the second current mirror. Under the condition of slew rate regulation, it works together with the second switch to charge the power transistor. This eliminates the need for multiple switches to receive logic signal control, thus simplifying the control process of power transistor driving.

[0012] Furthermore, the first current mirror includes: a first switching transistor, a second switching transistor, and a third switching transistor; Wherein, the first terminal of the first switching transistor is the first input terminal of the first current mirror; The first terminal of the first switching transistor is connected to the control terminal of the first switching transistor; The control terminal of the first switching transistor is connected to the control terminal of the second switching transistor; The control terminal of the first switching transistor is connected to the control terminal of the third switching transistor; The first terminal of the second switching transistor is the second input terminal of the first current mirror; The first terminal of the third switch is the third input terminal of the first current mirror; The second terminal of the first switch, the second terminal of the second switch, and the second terminal of the third switch together constitute the output terminal of the first current mirror.

[0013] The first current mirror of the present invention is controlled by the drive current of the gate-drain detection circuit, and the operation of the second current mirror is controlled by the second switching transistor. Thus, the control of two current mirrors is achieved using only one detection circuit and drive current. Under the condition of slew rate regulation, the switching transistor assists in completing the charging and discharging operation of the power transistor. The use of detection circuit and logic signals is reduced, and the control process of power transistor driving is simplified.

[0014] Furthermore, the first switching transistor is a transistor or a MOSFET; the second switching transistor is a transistor or a MOSFET; and the third switching transistor is a transistor or a MOSFET.

[0015] Furthermore, the second current mirror includes: a fourth switch and a fifth switch; The first end of the fourth switch and the first end of the fifth switch together constitute the input end of the second current mirror. The control terminal of the fourth switch is connected to the control terminal of the fifth switch; The control terminal of the fourth switch is connected to the second terminal of the fourth switch; The second terminal of the fourth switching transistor is the first output terminal of the second current mirror. The second terminal of the fifth switch is the second output terminal of the second current mirror.

[0016] The second current mirror of the present invention is controlled by the second input terminal of the first current mirror, thereby achieving the control of the two current mirrors with only one detection circuit and driving current. Under the condition of slew rate regulation, it cooperates with the switching transistor to complete the charging and discharging operation of the power transistor; reducing the use of detection circuits and logic signals, and simplifying the control process of power transistor driving.

[0017] Furthermore, the fourth switching transistor is a transistor or a MOSFET; the fifth switching transistor is a transistor or a MOSFET.

[0018] Furthermore, the power transistor includes an NMOS transistor or a PMOS transistor.

[0019] On the other hand, embodiments of the present invention also provide a driving method applied to the driving circuit as described in the embodiments of the present invention, comprising: The gate voltage and drain voltage of the power transistor are collected. When the gate voltage is less than the threshold voltage of the power transistor, or the drain voltage is less than a preset voltage value, a drive current is output to the first current mirror so that the first current mirror and the second current mirror generate a mirror current, which, in conjunction with the first switch and the second switch, charges and discharges the gate of the power transistor; or, when the gate voltage is greater than the first voltage difference, or the drain voltage is greater than the second voltage difference, a drive current is output to the first current mirror so that the first current mirror and the second current mirror generate a mirror current, which, in conjunction with the first switch and the second switch, charges and discharges the gate of the power transistor; wherein, the first voltage difference is the difference between the power supply voltage and the threshold voltage of the power transistor, and the second voltage difference is the difference between the power supply voltage and the preset voltage value.

[0020] After detecting the voltage at the gate and source of the power transistor, this invention can control both current mirrors by only outputting a drive signal to the first current mirror, reducing the use of detection circuits. In addition, by only outputting the drive current to control the first and second current mirrors, it can be used as an auxiliary current source to cooperate with the first and second switching transistors to charge and discharge the gate of the power transistor under slew rate regulation, without using logic signals, thus greatly simplifying the control process of power transistor driving.

[0021] On the other hand, embodiments of the present invention also provide a power supply system, including the drive circuit as described in embodiments of the present invention. Attached Figure Description

[0022] Figure 1 A schematic diagram of a driving circuit provided for the prior art; Figure 2 A schematic diagram of the Miller plateau effect during the turn-on and turn-off process provided for existing technology; Figure 3 A schematic diagram of one embodiment of the driving circuit provided by the present invention; Figure 4 A schematic diagram of another embodiment of the driving circuit provided by the present invention; Figure 5 The waveform diagram of the driving circuit provided by the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Please refer to Figure 1is a schematic structural diagram of an embodiment of the driving circuit provided by the present invention, the driving circuit comprising: a first current mirror, a second current mirror, a first switch K2, a second switch K1, a gate-drain detection circuit and a power transistor; wherein a first detection terminal of the gate-drain detection circuit is connected to the gate of the power transistor; a second detection terminal of the gate-drain detection circuit is connected to the drain of the power transistor; the output terminal of the gate-drain detection circuit is connected to the first input terminal of the first current mirror; the second input terminal of the first current mirror is connected to the first output terminal of the second current mirror; the third input terminal of the first current mirror is connected to the first end of the first switch K2; the output terminal of the first current mirror is grounded; the input terminal of the second current mirror is connected to a voltage source; the second output terminal of the second current mirror is connected to the first end of the second switch K1; the second end of the first switch K2 is connected to the gate of the power transistor; the second end of the second switch K1 is connected to the gate of the power transistor; the gate-drain detection circuit is configured to generate a driving current according to the gate voltage of the power transistor and the drain voltage of the power transistor; the first current mirror is configured to copy the driving current received at the first input terminal to the second input terminal and the third input terminal; the second current mirror is configured to copy the current at the first output terminal to the second output terminal.

[0025] In this embodiment, the power transistor is an NMOS transistor, which requires low-side driving; in addition, only one gate-drain detection circuit is used in this embodiment, and the detection circuit does not need to be combined with a logic control signal. It generates the driving current Iaux only when the gate voltage is less than the threshold voltage of the power transistor, Vg<Vth2, or the drain voltage is less than a preset voltage value, Vout<Vth1. The first current mirror MP1~MP2 and the second current mirror MN1~MN3 respectively generate an auxiliary charging current Ic_aux and an auxiliary discharging current Id_aux. These two currents do not directly control the gate of the power transistor MN0, but control the gate of the power transistor MN0 through the first switch K2 and the second switch K1. In this way, the operation of the main charging and discharging path will not be interfered, and the time for the power transistor MN0 to enter and exit the Miller plateau is reduced very intelligently, thereby effectively reducing the turn-on and turn-off delays, and the circuit is simple, more reliable and safer.

[0026] Further, the driving circuit further comprises: a first current source; The positive terminal of the first current source is grounded; The negative terminal of the first current source is connected to the first terminal of the first switch K2.

[0027] The first current source of the present invention can be used as the main discharge path and is connected in parallel with the first current mirror. Under the condition of slew rate regulation, it works together with the first switch to discharge the power transistor. This eliminates the need for multiple switches to receive logic signal control, thus simplifying the control process of power transistor driving.

[0028] Furthermore, the driving circuit also includes: a second current source; The negative terminal of the second current source is connected to the voltage source; The negative terminal of the second current source is connected to the first terminal of the second switch K1.

[0029] The second current source of the present invention can be used as the main charging circuit and is connected in parallel with the second current mirror. Under the condition of slew rate regulation, it works together with the second switch to charge the power transistor. This eliminates the need for multiple switches to receive logic signal control, thus simplifying the control process of power transistor driving.

[0030] Furthermore, the first current mirror includes: a first switching transistor MN1, a second switching transistor MN2, and a third switching transistor MN3; Wherein, the first terminal of the first switching transistor MN1 is the first input terminal of the first current mirror; The first terminal of the first switching transistor MN1 is connected to the control terminal of the first switching transistor MN1. The control terminal of the first switching transistor MN1 is connected to the control terminal of the second switching transistor MN2; The control terminal of the first switching transistor MN1 is connected to the control terminal of the third switching transistor MN3. The first terminal of the second switch MN2 is the second input terminal of the first current mirror; The first terminal of the third switch MN3 is the third input terminal of the first current mirror; The second terminal of the first switch MN1, the second terminal of the second switch MN2, and the second terminal of the third switch MN3 together constitute the output terminal of the first current mirror.

[0031] The first current mirror of the present invention is controlled by the drive current of the gate-drain detection circuit, and the operation of the second current mirror is controlled by the second switching transistor. Thus, the control of two current mirrors is achieved using only one detection circuit and drive current. Under the condition of slew rate regulation, the switching transistor assists in completing the charging and discharging operation of the power transistor. The use of detection circuit and logic signals is reduced, and the control process of power transistor driving is simplified.

[0032] Furthermore, the first switch MN1 is a transistor or a MOSFET; the second switch MN2 is a transistor or a MOSFET; and the third switch MN3 is a transistor or a MOSFET.

[0033] Furthermore, the second current mirror includes: a fourth switch MP1 and a fifth switch MP2; The first terminal of the fourth switch MP1 and the first terminal of the fifth switch MP2 together constitute the input terminal of the second current mirror. The control terminal of the fourth switch MP1 is connected to the control terminal of the fifth switch MP2; The control terminal of the fourth switch MP1 is connected to the second terminal of the fourth switch MP1; The second terminal of the fourth switching transistor MP1 is the first output terminal of the second current mirror. The second terminal of the fifth switch MP2 is the second output terminal of the second current mirror.

[0034] The second current mirror of the present invention is controlled by the second input terminal of the first current mirror, thereby achieving the control of the two current mirrors with only one detection circuit and driving current. Under the condition of slew rate regulation, it cooperates with the switching transistor to complete the charging and discharging operation of the power transistor; reducing the use of detection circuits and logic signals, and simplifying the control process of power transistor driving.

[0035] Furthermore, the fourth switch MP1 is a transistor or a MOSFET; the fifth switch MP2 is a transistor or a MOSFET.

[0036] Furthermore, the power transistor includes an NMOS transistor or a PMOS transistor.

[0037] Please refer to Figure 4 This is a schematic diagram of another embodiment of the driving circuit provided by the present invention. The driving circuit of the present invention can also be used for high-side driving when the power transistor is a PMOS transistor. When the gate voltage is greater than a first voltage difference (Vg > VB - Vth2) or the drain voltage is greater than a second voltage difference (Vout > VB - Vth1), a driving current Iaux is generated to accelerate the turn-on and turn-off speed of the power transistor MP0. The first voltage difference is the difference between the power supply voltage and the threshold voltage of the power transistor, and the second voltage difference is the difference between the power supply voltage and a preset voltage value. Please refer to... Figure 5is the operating waveform diagram of the driving circuit provided by the present invention. When it is necessary to turn on the power transistor MP0, CMD_P changes from high to low, CMD_N changes from low to high, the gate-drain detection circuit detects that Vg>VB-Vth2, generates current Iaux, which passes through current mirrors MP1 to MP5 and MN1 to MN3 to generate auxiliary charging current Ic_aux and auxiliary discharging current Id_aux respectively. Since CMD_N is turned on at this time, Vg is quickly pulled down to Vm<VB-Vth2, Iaux drops to 0, and the power transistor MP0 enters the Miller plateau region. After a period of Tr, Vout>VB-Vth1, the gate-drain detection circuit generates current Iaux again, pulling Vg to the ground, and the power transistor MP0 is fully turned on.

[0038] When it is necessary to turn off the power transistor MP0, CMD_P changes from low to high, CMD_N changes from high to low, the gate-drain detection circuit detects that Vout>VB-Vth1, generates current Iaux, which generates auxiliary discharging current Id_aux and auxiliary charging current Ic_aux through current mirrors. Since CMD_P is turned on at this time, Vg is quickly pulled up to Vm, and the power transistor MP0 enters the Miller plateau region. After a period of Tf, Vg>VB-Vth2, the gate-drain detection circuit generates current Iaux again, pulling Vg to VB, and the power transistor MP0 is fully turned off.

[0039] On the other hand, embodiments of the present invention further provide a driving method, which is applied to the driving circuit according to the embodiments of the present invention, including: collecting the gate voltage of the power transistor and the drain voltage of the power transistor; when the gate voltage is less than the threshold voltage of the power transistor, or the drain voltage is less than a preset voltage value, outputting a driving current to a first current mirror, so that the first current mirror and the second current mirror generate mirrored currents, which cooperate with a first switch and a second switch to charge and discharge the gate of the power transistor; or, when the gate voltage is greater than a first voltage difference, or the drain voltage is greater than a second voltage difference, outputting a driving current to the first current mirror, so that the first current mirror and the second current mirror generate mirrored currents, which cooperate with the first switch and the second switch to charge and discharge the gate of the power transistor; wherein the first voltage difference is the difference between the power supply voltage and the threshold voltage of the power transistor, and the second voltage difference is the difference between the power supply voltage and the preset voltage value.

[0040] In this embodiment, when the gate voltage is less than the threshold voltage of the power transistor, or the drain voltage is less than the preset voltage value, outputting the driving current to the first current mirror, so that the first current mirror and the second current mirror generate mirrored currents, which cooperate with the first switch and the second switch to charge and discharge the gate of the power transistor, specifically comprises: When the gate voltage is less than the threshold voltage of the power transistor, a drive current is output to the first input terminal of the first current mirror so that the first current mirror controls the second current mirror to replicate the drive current; the second switch is closed so that the second current mirror charges the gate of the power transistor; or, when the gate voltage is less than the preset voltage value, a drive current is output to the first input terminal of the first current mirror so that the first current mirror replicates the drive current; the first switch is closed so that the first current mirror discharges the gate of the power transistor.

[0041] In this embodiment, when the gate voltage is greater than the first voltage difference, or the drain voltage is greater than the second voltage difference, a drive current is output to the first current mirror, so that the first current mirror and the second current mirror generate a mirror current, which, in conjunction with the first switch and the second switch, charges and discharges the gate of the power transistor. Specifically: When the gate voltage is greater than the first voltage difference, a drive current is output to the first input terminal of the first current mirror so that the first current mirror replicates the drive current; the first switch is closed so that the first current mirror discharges the gate of the power transistor; or, when the gate voltage is greater than the second voltage difference, a drive current is output to the first input terminal of the first current mirror so that the first current mirror controls the second current mirror to replicate the drive current; the second switch is closed so that the second current mirror charges the gate of the power transistor.

[0042] After detecting the voltage at the gate and source of the power transistor, this invention can control both current mirrors by only outputting a drive signal to the first current mirror, reducing the use of detection circuits. In addition, by only outputting the drive current to control the first and second current mirrors, it can be used as an auxiliary current source to cooperate with the first and second switching transistors to charge and discharge the gate of the power transistor under slew rate regulation, without using logic signals, thus greatly simplifying the control process of power transistor driving.

[0043] On the other hand, embodiments of the present invention also provide a power supply system, including the drive circuit as described in embodiments of the present invention.

[0044] This invention uses only one gate-drain detection circuit to detect the voltage at the gate and source of the power transistor, reducing the use of detection circuits. In addition, the gate-drain detection circuit only outputs a drive current to control the first and second current mirrors. Under the condition of slew rate regulation, it can be used as an auxiliary current source to cooperate with the first and second switching transistors to charge and discharge the gate of the power transistor, without using logic signals. Therefore, the control process of driving the power transistor is greatly simplified.

[0045] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A driving circuit, characterized in that, include: First current mirror, second current mirror, first switch, second switch, gate-drain detection circuit and power transistor; The first detection terminal of the gate-drain detection circuit is connected to the gate of the power transistor. The second detection terminal of the gate-drain detection circuit is connected to the drain of the power transistor; The output terminal of the gate leakage detection circuit is connected to the first input terminal of the first current mirror. The second input terminal of the first current mirror is connected to the first output terminal of the second current mirror; The third input terminal of the first current mirror is connected to the first terminal of the first switch; The output terminal of the first current mirror is grounded; The input terminal of the second current mirror is connected to a voltage source; The second output terminal of the second current mirror is connected to the first terminal of the second switch; The second terminal of the first switch is connected to the gate of the power transistor; The second terminal of the second switch is connected to the gate of the power transistor; The gate-drain detection circuit is used to generate a drive current based on the gate voltage and drain voltage of the power transistor. The first current mirror is used to copy the drive current received at the first input terminal to the second input terminal and the third input terminal; The second current mirror is used to copy the current from the first output terminal to the second output terminal.

2. The driving circuit as described in claim 1, characterized in that, Also includes: First current source; The positive terminal of the first current source is grounded; The negative terminal of the first current source is connected to the first terminal of the first switch.

3. The driving circuit as described in claim 1, characterized in that, Also includes: Second current source; The negative terminal of the second current source is connected to the voltage source; The positive terminal of the second current source is connected to the first terminal of the second switch.

4. The driving circuit as described in any one of claims 1-3, characterized in that, The first current mirror includes: a first switching transistor, a second switching transistor, and a third switching transistor; Wherein, the first terminal of the first switching transistor is the first input terminal of the first current mirror; The first terminal of the first switching transistor is connected to the control terminal of the first switching transistor; The control terminal of the first switching transistor is connected to the control terminal of the second switching transistor; The control terminal of the first switching transistor is connected to the control terminal of the third switching transistor; The first terminal of the second switching transistor is the second input terminal of the first current mirror; The first terminal of the third switch is the third input terminal of the first current mirror; The second terminal of the first switch, the second terminal of the second switch, and the second terminal of the third switch together constitute the output terminal of the first current mirror.

5. The driving circuit as described in claim 4, characterized in that, The first switching transistor is a transistor or a MOSFET; the second switching transistor is a transistor or a MOSFET; and the third switching transistor is a transistor or a MOSFET.

6. The driving circuit according to any one of claims 1-3, characterized in that, The second current mirror includes: a fourth switch and a fifth switch; The first end of the fourth switch and the first end of the fifth switch together constitute the input end of the second current mirror. The control terminal of the fourth switch is connected to the control terminal of the fifth switch; The control terminal of the fourth switch is connected to the second terminal of the fourth switch; The second terminal of the fourth switching transistor is the first output terminal of the second current mirror. The second terminal of the fifth switch is the second output terminal of the second current mirror.

7. The driving circuit as described in claim 6, characterized in that, The fourth switching transistor is a transistor or a MOSFET; the fifth switching transistor is a transistor or a MOSFET.

8. The driving circuit according to any one of claims 1-3, characterized in that, The power transistor includes an NMOS transistor or a PMOS transistor.

9. A driving method, characterized in that, The drive circuit described in any one of claims 1-8 includes: The gate voltage and drain voltage of the power transistor are collected. When the gate voltage is less than the threshold voltage of the power transistor, or the drain voltage is less than a preset voltage value, a drive current is output to the first current mirror so that the first current mirror and the second current mirror generate a mirror current, which, in conjunction with the first switch and the second switch, charges and discharges the gate of the power transistor; or, when the gate voltage is greater than the first voltage difference, or the drain voltage is greater than the second voltage difference, a drive current is output to the first current mirror so that the first current mirror and the second current mirror generate a mirror current, which, in conjunction with the first switch and the second switch, charges and discharges the gate of the power transistor; wherein, the first voltage difference is the difference between the power supply voltage and the threshold voltage of the power transistor, and the second voltage difference is the difference between the power supply voltage and the preset voltage value.

10. A power supply system, characterized in that, Includes the driving circuit as described in any one of claims 1-8.

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