Charge pump filter circuit

Abstract

The application discloses a charge pump filter circuit, which comprises a first PMOS tube and a first capacitor. The source of the first PMOS tube is connected with an output end of a charge pump. The drain of the first PMOS tube is connected with a first end of the first capacitor and serves as an output end of an output voltage. The second end of the first capacitor is grounded. The gate of the first PMOS tube is connected with a first node, the voltage of the first node is a first voltage, and the first PMOS tube has a first conduction resistance. The power supply end of the charge pump is connected with a power supply voltage. The first voltage is proportional to the power supply voltage, so that the first conduction resistance is adjusted by the size of the power supply voltage. When the power supply voltage increases, the voltage of the first node increases, the first conduction resistance increases, and the filtering effect increases. When the power supply voltage decreases, the voltage of the first node decreases, the first conduction resistance decreases, and the driving capacity increases. The application can guarantee the driving capacity under low voltage and reduce the ripple defects under high voltage.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a charge pump filter circuit. Background Technology

[0002] With the development of semiconductor technology, the operating voltage of devices is getting lower and lower. For memory, the power supply voltage required for operation is constantly shrinking to below 2.5V, 1.8V, or 1V. However, the programming and erasing voltages of memory are much higher than the power supply voltage. That is, the programming and erasing voltages of memory are high voltages relative to the power supply voltage. In this case, a charge pump circuit is usually required to convert the power supply voltage to the required programming or erasing voltage. In integrated circuits, it is often necessary to use both positive and negative voltages simultaneously.

[0003] like Figure 1 The diagram shown is a structural diagram of an existing charge pump circuit; the power supply terminal of charge pump 101 is connected to the power supply voltage VCC. Figure 1 The document also shows that the power supply voltage VCC ranges from 1.6V to 5.5V. The charge pump, controlled by a switching circuit, charges the capacitor, creating a voltage difference between its two electrodes. When the capacitor stores charge, a sudden change in voltage at one electrode causes a sudden change in voltage at the other electrode, thus maintaining a constant voltage difference. When the voltage at one electrode is equal to the power supply voltage VCC, the voltage at the other electrode is greater than VCC, resulting in a voltage boost. By cascading multiple charge pump units, an output voltage Vout much larger than the power supply voltage VCC can be obtained at the output terminal. The magnitude of the output voltage Vout is determined according to the needs of the chip, such as memory, which includes flash memory.

[0004] In existing charge pump circuits, to ensure driving capability at low voltages, the high-voltage ripple is relatively large, affecting chip performance and reliability. For example... Figure 2 The figure shows the waveform curves of the output voltage of the existing charge pump circuit under different power supply voltages. When VCC = 1.6V, the ripple of the output voltage Vout in curve 102 is small. However, since the power supply voltage VCC is small, the driving capability of the charge pump needs to be guaranteed.

[0005] When VCC = 5.5V, although it has a large driving capability, the output voltage Vout has a large ripple in curve 103.

[0006] Therefore, in order to ensure the drive capability requirements at low voltage (i.e., when VCC is low), the drive capability of the charge pump needs to be increased; however, when the drive capability of the charge pump is increased, the output voltage Vout will fluctuate, i.e., have large ripples, in applications with high voltage (i.e., when VCC is high). Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a charge pump filter circuit that can ensure driving capability under low voltage while reducing ripple defects under high voltage.

[0008] To solve the above-mentioned technical problems, the charge pump filter circuit provided by the present invention includes: a first PMOS transistor and a first capacitor.

[0009] The source of the first PMOS transistor is connected to the output terminal of the charge pump.

[0010] The drain of the first PMOS transistor is connected to the first terminal of the first capacitor, and the drain of the first PMOS transistor is the output terminal of the output voltage.

[0011] The second terminal of the first capacitor is grounded.

[0012] The gate of the first PMOS transistor is connected to a first node, the voltage of the first node is a first voltage, and the first PMOS transistor has a first on-resistance.

[0013] The power supply terminal of the charge pump is connected to the power supply voltage.

[0014] The first voltage is proportional to the power supply voltage, so that the first on-resistance is adjusted by the magnitude of the power supply voltage.

[0015] When the power supply voltage increases, the voltage of the first node increases, the first on-resistance increases, and the filtering effect of the filter circuit increases.

[0016] When the power supply voltage decreases, the voltage of the first node decreases, the first on-resistance decreases, and the driving capability of the charge pump increases.

[0017] A further improvement is that the first voltage is obtained by a first voltage divider circuit.

[0018] The first voltage divider circuit is connected between the power supply voltage and ground.

[0019] The first voltage divider circuit includes a series structure formed by multiple diode-connected MOS transistors connected in series, and the first node is led out from a series point in the series structure.

[0020] A further improvement is that each of the MOS transistors in the series structure is a PMOS transistor. The gate and drain of each MOS transistor are shorted to achieve a diode connection.

[0021] A further improvement is that the number of MOS transistors in the series structure includes two.

[0022] A further improvement is that the first voltage divider circuit also includes a switching transistor, which is connected in series with the series structure, and the switching transistor controls the conduction and cutoff of the first voltage divider circuit.

[0023] The control terminal of the switching transistor is connected to a first control signal. When the output voltage is greater than or equal to a set value, the first control signal turns the switching transistor off; when the output voltage is less than the set value, the first control signal turns the switching transistor on.

[0024] A further improvement is that the switching transistor is composed of a second PMOS transistor.

[0025] The source of the second PMOS transistor is connected to the power supply voltage.

[0026] The drain of the second PMOS transistor is connected to the first terminal of the series structure, and the second terminal of the series structure is grounded.

[0027] A further improvement is that the first control signal is an inverted signal of the feedback signal of the charge pump.

[0028] A further improvement is that the charge pump also includes a feedback circuit that outputs the feedback signal.

[0029] When the output voltage is greater than or equal to the set value, the feedback signal is at a low level.

[0030] When the output voltage is less than the set value, the feedback signal is at a high level.

[0031] A further improvement includes: a first inverter, the input of which is connected to the feedback signal, and the output of which outputs the first control signal.

[0032] A further improvement is that the power supply voltage varies from 1.6V to 5.5V.

[0033] This invention includes a filter circuit at the output of the charge pump. The resistor in the filter circuit is a first on-resistance formed by a first PMOS transistor, and the first voltage supplied to the gate of the first PMOS transistor is set to be proportional to the power supply voltage. Since the magnitude of the first on-resistance changes with the first voltage, the magnitude of the first on-resistance changes with the magnitude of the power supply voltage. When the power supply voltage increases, the source-gate voltage of the first PMOS transistor decreases, thus increasing the first on-resistance. This improves the filtering effect of the filter circuit formed by the first on-resistance and the first capacitor. Therefore, it can improve the filtering effect at high voltage (i.e., when the power supply voltage is high), thereby reducing the ripple defects of the output voltage under high voltage. Conversely, when the power supply voltage decreases, the source-gate voltage of the first PMOS transistor increases, thus decreasing the first on-resistance. This increases the driving capability of the charge pump. Therefore, this invention can also ensure the driving capability at low voltage (i.e., when the power supply voltage is low). Attached Figure Description

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0035] Figure 1 This is a structural diagram of an existing charge pump circuit;

[0036] Figure 2 These are the waveform curves of the output voltage of an existing charge pump circuit under different power supply voltages;

[0037] Figure 3 This is a structural diagram of the charge pump filter circuit of the present invention. Detailed Implementation

[0038] like Figure 3 The diagram shown is a structural diagram of the charge pump 201 filter circuit of the present invention. The charge pump filter circuit of this embodiment includes a first PMOS transistor MP1 and a first capacitor C1. The first PMOS transistor MP1 and the first capacitor C1 constitute the main body 202 of the filter circuit.

[0039] The source of the first PMOS transistor MP1 is connected to the output terminal of the charge pump 201.

[0040] The drain of the first PMOS transistor MP1 is connected to the first terminal of the first capacitor C1, and the drain of the first PMOS transistor MP1 is the output terminal of the output voltage Vout.

[0041] The second terminal of the first capacitor C1 is grounded.

[0042] The gate of the first PMOS transistor MP1 is connected to a first node, the voltage of the first node is a first voltage V1, and the first PMOS transistor MP1 has a first on-resistance.

[0043] The power supply terminal of the charge pump 201 is connected to the power supply voltage VCC.

[0044] In some embodiments, the power supply voltage VCC varies from 1.6V to 5.5V.

[0045] The first voltage V1 is proportional to the power supply voltage VCC, so that the first on-resistance is adjusted by the magnitude of the power supply voltage VCC.

[0046] When the power supply voltage VCC increases, the voltage of the first node increases, the first on-resistance increases, and the filtering effect of the filter circuit increases.

[0047] When the power supply voltage VCC decreases, the voltage of the first node decreases, the first on-resistance decreases, and the driving capability of the charge pump 201 increases.

[0048] In this embodiment of the invention, the first voltage V1 is obtained by the first voltage divider circuit 203.

[0049] The first voltage divider circuit 203 is connected between the power supply voltage VCC and ground.

[0050] In some embodiments, the first voltage divider circuit 203 includes a series structure 204 formed by multiple diode-connected MOS transistors connected in series, and the first node is led out from one of the series points in the series structure 204. Further, each MOS transistor in the series structure 204 is a PMOS transistor, and the gate and drain of each MOS transistor are shorted to achieve a diode connection. Further, the number of MOS transistors in the series structure 204 includes two. Figure 3 In the above, the two MOS transistors in the series structure 204 are represented by MP3 and MP4, respectively.

[0051] In this embodiment of the invention, the first voltage divider circuit 203 further includes a switching transistor 205, which is connected in series with the series structure 204. The switching transistor 205 controls the conduction and cutoff of the first voltage divider circuit 203.

[0052] The control terminal of the switch 205 is connected to a first control signal. When the output voltage Vout is greater than or equal to a set value, the first control signal turns off the switch 205; when the output voltage Vout is less than the set value, the first control signal turns on the switch 205.

[0053] In some embodiments, the switching transistor 205 is composed of a second PMOS transistor MP2.

[0054] The source of the second PMOS transistor MP2 is connected to the power supply voltage VCC.

[0055] The drain of the second PMOS transistor MP2 is connected to the first terminal of the series structure 204, and the second terminal of the series structure 204 is grounded. Figure 3 In the series structure 204, the first end is the source of PMOS transistor MP3, and the second end is the drain of PMOS transistor MP4.

[0056] In some embodiments, the first control signal is the inverted signal of the feedback signal FB of the charge pump 201.

[0057] The charge pump 201 also includes a feedback circuit, which outputs the feedback signal FB.

[0058] When the output voltage Vout is greater than or equal to the set value, the feedback signal FB is at a low level.

[0059] When the output voltage Vout is less than the set value, the feedback signal FB is at a high level.

[0060] It also includes: a first inverter 206, the input of which is connected to the feedback signal FB, and the output of which outputs the first control signal.

[0061] In this embodiment of the invention, a filter circuit is provided at the output terminal of the charge pump 201. The resistor of the filter circuit is a first on-resistance formed by the first PMOS transistor MP1, and the first voltage V1 provided to the gate of the first PMOS transistor MP1 is set to be proportional to the power supply voltage VCC. Since the magnitude of the first on-resistance changes with the first voltage V1, the magnitude of the first on-resistance changes with the magnitude of the power supply voltage VCC. When the power supply voltage VCC increases, the source-gate voltage of the first PMOS transistor MP1 decreases, so the first on-resistance increases. This is beneficial to improving the filtering effect of the filter circuit formed by the first on-resistance and the first capacitor C1. Therefore, the filtering effect can be improved when the power supply voltage VCC is high, thereby reducing the ripple defect of the output voltage Vout under high voltage. When the power supply voltage VCC decreases, the source-gate voltage of the first PMOS transistor MP1 increases, so the first on-resistance decreases. This increases the driving capability of the charge pump 201. Therefore, this embodiment of the invention can also ensure the driving capability when the power supply voltage VCC is low.

[0062] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A charge pump filter circuit, characterized in that, The filter circuit includes: a first PMOS transistor and a first capacitor; The source of the first PMOS transistor is connected to the output terminal of the charge pump; The drain of the first PMOS transistor is connected to the first terminal of the first capacitor, and the drain of the first PMOS transistor is the output terminal of the output voltage. The second terminal of the first capacitor is grounded; The gate of the first PMOS transistor is connected to a first node, the voltage of the first node is a first voltage, and the first PMOS transistor has a first on-resistance. The power supply terminal of the charge pump is connected to the power supply voltage; The first voltage is proportional to the power supply voltage, so that the first on-resistance is adjusted by the magnitude of the power supply voltage; When the power supply voltage increases, the voltage of the first node increases, the first on-resistance increases, and the filtering effect of the filter circuit increases. When the power supply voltage decreases, the voltage of the first node decreases, the first on-resistance decreases, and the driving capability of the charge pump increases.

2. The charge pump filter circuit as described in claim 1, characterized in that: The first voltage is obtained by the first voltage divider circuit; The first voltage divider circuit is connected between the power supply voltage and ground; The first voltage divider circuit includes a series structure formed by multiple diode-connected MOS transistors connected in series, and the first node is led out from a series point in the series structure.

3. The charge pump filter circuit as described in claim 2, characterized in that: Each of the MOS transistors in the series structure is a PMOS transistor, and the gate and drain of each MOS transistor are shorted to achieve a diode connection.

4. The charge pump filter circuit as described in claim 3, characterized in that: The number of MOS transistors in the series structure includes two.

5. The charge pump filter circuit as described in claim 2, characterized in that: The first voltage divider circuit also includes a switching transistor, which is connected in series with the series structure, and the switching transistor controls the conduction and cutoff of the first voltage divider circuit; The control terminal of the switching transistor is connected to a first control signal. When the output voltage is greater than or equal to a set value, the first control signal turns the switching transistor off; when the output voltage is less than the set value, the first control signal turns the switching transistor on.

6. The charge pump filter circuit as described in claim 5, characterized in that: The switching transistor is composed of a second PMOS transistor; The source of the second PMOS transistor is connected to the power supply voltage; The drain of the second PMOS transistor is connected to the first terminal of the series structure, and the second terminal of the series structure is grounded.

7. The charge pump filter circuit as described in claim 6, characterized in that: The first control signal is the inverted signal of the feedback signal of the charge pump.

8. The charge pump filter circuit as described in claim 7, characterized in that: The charge pump also includes a feedback circuit, which outputs the feedback signal. When the output voltage is greater than or equal to the set value, the feedback signal is at a low level; When the output voltage is less than the set value, the feedback signal is at a high level.

9. The charge pump filter circuit as described in claim 8, characterized in that, Also includes: A first inverter, the input of which is connected to the feedback signal, and the output of which outputs the first control signal.

10. The charge pump filter circuit as described in claim 1, characterized in that: The power supply voltage ranges from 1.6V to 5.5V.

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