Programmable gain amplifier with impedance matching and reverse isolation

Abstract

The present disclosure relates to a programmable gain amplifier with impedance matching and reverse isolation. The programmable gain amplifier includes a programmable resistance ladder, a common-gate cascode amplification multiplexer, and an AC coupling capacitor. The programmable resistance ladder is configured on N max number of junction nodes and is controlled by N max −1 resistance control signals, where N max is an integer greater than 1. The common-gate cascode amplification multiplexer includes N max common-gate cascode amplifiers to receive N max internal voltages at the N max junction nodes and to output N max output currents to an output node with a load according to N max amplifier control signals, respectively. The AC coupling capacitor is used to couple an input node to a first junction node of the N max junction nodes.

Description

Technical Field

[0001] This disclosure relates to programmable gain amplifiers, and more particularly to programmable gain amplifiers with impedance matching and reverse isolation. Background Technology

[0002] In a communication system, a first signal transmitted by a transmitter is transmitted through a communication medium (e.g., free air or cable) as a second signal received by a receiver. The receiver amplifies the second signal into a third signal according to a gain factor, so that the third signal has a level suitable for detection. The gain of the receiver is defined by the ratio between the level of the third signal and the level of the second signal. Since the level of the second signal can vary drastically due to the insertion loss of the communication medium, the gain needs to be programmable. For this purpose, a programmable gain amplifier is typically implemented. In many applications, impedance matching is required, and impedance matching is satisfied when an input impedance of the programmable gain amplifier is approximately equal to the source impedance. Furthermore, those skilled in the art expect the programmable gain amplifier to have excellent reverse isolation so that the receiver's internal signals cannot be transmitted back to the communication medium.

[0003] In U.S. Patent 8,299,870, "Wu" and "Gomez" proposed a programmable gain amplifier / attenuator that can provide a wide attenuation arrangement and fine attenuation steps, wherein several switches are used to couple the input or the attenuation of the input to the output. These switches allow for programmable gain; however, the circuitry of the programmable gain amplifier / attenuator system proposed by "Wu" and "Gomez" allows the output to be directly coupled back to the input, resulting in poor reverse isolation.

[0004] Therefore, those skilled in the art would expect a programmable gain amplifier to have excellent impedance matching and excellent reverse isolation. Summary of the Invention

[0005] In one embodiment, a programmable gain amplifier includes a programmable resistor ladder, a cascode multiplexer, and an AC (alternate current) coupling capacitor. The programmable resistor ladder is configured on N... max On each joint node, and subject to N max -1 resistor control signal, where N max The integer is greater than 1. A common-gate cascaded amplifier multiplexer contains N... maxN common-gate cascodeamplifiers (CGCAs). max A common-grid stacked amplifier is used for N max Each junction node receives N max An internal voltage, and according to N max The amplifier control signal will N max Each output current is output to an output node with a load. An AC coupling capacitor is used to couple an input node to N. max The first junction node of a set of junction nodes. A programmable resistance ladder contains N max -1 series resistor, one parallel resistor, and N max -1 switched resistor circuit. N max -1 series resistor is used to connect in series with N max At each junction node. A parallel resistor is used to connect N. max The first junction node of the junction nodes is connected in parallel to the reference ground. N max -1 switched resistor circuit is used to determine N max -1 resistor control signal, respectively, to the remaining N max -1 junction node is connected in parallel to the reference ground. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a programmable gain amplifier according to an embodiment of the present disclosure.

[0007] Figure 2 This is an embodiment of the present disclosure. Figure 1 A schematic diagram of a common-gate stacked amplifier with a programmable gain amplifier.

[0008] Figure 3 For an embodiment of this disclosure, suitable for use by Figure 2 A schematic diagram of the bias generation circuit used in the common-gate stacked amplifier.

[0009] Symbol Explanation

[0010] 100: Programmable gain amplifier

[0011] 110: Common-grid stacked amplifier multiplexer

[0012] A1~A4: Common-grid stacked amplifiers

[0013] 120: Programmable Resistor Ladder

[0014] N: Integer

[0015] ENC: Encoder

[0016] E1~E4: Amplifier control signals

[0017] S1~S3: Resistor control signals

[0018] V DD Power Node

[0019] ZL: Load

[0020] V o Output voltage

[0021] I o1 ~I o4 Output current

[0022] Z a1 ~Z a4 Input impedance

[0023] Z s1 ~Z s4 Source impedance

[0024] V i Input voltage

[0025] C ac AC coupling capacitor

[0026] Z i Input impedance

[0027] V1~V4: Internal voltage

[0028] R r1 ~R r3 Series resistor

[0029] R s0 Parallel resistors

[0030] SR1~SR3: Switched Resistor Circuit

[0031] R s1 ~R s3 :resistance

[0032] SW1~SW3: Switches

[0033] N10: Input node

[0034] N11~N23: Nodes

[0035] V B1 ~V B2 Bias voltage

[0036] 221-225: Switch

[0037] V G1 First gate voltage

[0038] V G2Second gate voltage

[0039] 211~212: NMOS transistors

[0040] S 1B Logic inversion signal

[0041] 300: Bias voltage generation circuit

[0042] 331: Current Source

[0043] 321~322: NMOS transistors

[0044] 311: Source resistor Detailed Implementation

[0045] This disclosure relates to programmable gain amplifiers. Although the specification describes several embodiments of this disclosure, and these embodiments are considered preferred ways of implementing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the specific examples described below, or to any particular way of implementing any feature of these examples. In other instances, well-known details are not shown or described to avoid obscuring aspects of this disclosure.

[0046] Those skilled in the art will understand the microelectronics-related terminology and basic concepts used herein, such as "voltage," "current," "signal," "amplifier," "common gate," "load," "parallel," "impedance," "impedance value," "resistance value," "series connection," "parallel connection," "multiplexer," "overlay," "switch," "resistor," "capacitor," "circuit node," "ground," "DC," "AC," "power supply," "metal oxide semiconductor (MOS) transistor," "complementary metal oxide semiconductor (CMOS) process technology," "n-channel metal oxide semiconductor (NMOS) transistor," and "p-channel metal oxide semiconductor (PMOS) transistor." Such terminology is used in the context of microelectronics, and the related concepts are self-evident to those skilled in the art; therefore, they will not be explained in detail here.

[0047] There is no need to explain the unit terms such as Ohm, pico-Farad (pF), femto-Farad (fF), nanometer (nm), micrometer (μm), and micro-Ampere (μA), as those skilled in the art can understand these unit terms.

[0048] Without the need for a lengthy description of how one component in a circuit diagram is connected to another, those skilled in the art can read a circuit diagram containing electronic components (e.g., inductors, capacitors, resistors, NMOS transistors, PMOS transistors, etc.). Those skilled in the art can also identify the reference ground symbol, capacitor symbol, inductor symbol, resistor symbol, and the symbols for PMOS and NMOS transistors, and can identify the "source," "gate," and "drain" terminals of the PMOS and NMOS transistor symbols. For the sake of brevity, the "source terminal" will be simply referred to as "source," the "gate terminal" as "gate," and the "drain terminal" as "drain."

[0049] A circuit is composed of a transistor, a capacitor, a resistor, and / or other electronic devices, which are interconnected in some way to achieve a specific function.

[0050] In this article, "circuit node" is often simply referred to as "node" when the meaning of "node" is clearly understood from the context.

[0051] A signal is a voltage with a variable level that carries some information and can change over time. The level of a signal at a given point in time indicates the state of the signal at that point. In this article, "signal" and "voltage signal" refer to the same thing and are therefore interchangeable.

[0052] A network is a circuit or a collection of circuits.

[0053] The power node is a circuit node with a nearly stable voltage, as is the ground node. Both the power node and the ground node are DC nodes, but they have different voltage levels; that is, the voltage level of the power node is greater than the voltage level of the ground node. Following the convention widely used in the literature, in the circuit presented here, "V..." DD This indicates a power node. Although the DC level of the reference ground node is typically 0V, it is not limited to this (i.e., it does not have to be 0V). The key point is that there is a potential difference between the power node and the reference ground node. For a given circuit, if the DC voltage levels of all nodes are increased by the same amount, the circuit's operation will remain unchanged.

[0054] Logic signals are voltage signals with two states: low and high. A logic signal is in a high state when its voltage level is above a trip point; conversely, it is in a low state when its voltage level is below the trip point. The low state is also called the "0" state, and the high state is also called the "1" state. Regarding the logic signal Q, describing it as "high" ("high level") or "low" ("low level") means that the logic signal Q is in a high state or a low state. Similarly, describing it as "1" or "0" means that the logic signal Q is in a "1" state or a "0" state.

[0055] The transition point of the first logic signal is not necessarily the same as the transition point of the second logic signal.

[0056] If the first logic signal and the second logic signal are always in opposite states, then the first logic signal is called the logic inversion of the second logic signal. That is, when the first logic signal is "low", the second logic signal is "high"; when the first logic signal is "high", the second logic signal is "low". When the first logic signal is the logic inversion of the second logic signal, the first logic signal is said to be complementary to the second logic signal.

[0057] Logic signals are frequently used as control signals to enable or disable circuit functions. When a logic signal is in an enabling state, it is said to be "asserted"; conversely, when it is in a disabling state, it is said to be "de-asserted." When a logic signal is asserted at a high level, it is called "high-level assertion." When a logic signal is asserted at a low level, it is called "low-level assertion."

[0058] Switches are used extensively in this paper. An open switch is a device used to controllably connect a first node to a second node according to a logic signal. When the logic signal is established, the switch is open and presents a short circuit; when the logic signal is de-established, the switch is closed and presents an open circuit.

[0059] When an NMOS transistor is biased to the saturation region, it can function as an amplifier. In the saturation region, the gate-source voltage is greater than the critical voltage, and the gate-drain voltage is less than the critical voltage. If the gate voltage is almost constant, the source voltage is variable and represents the input signal, and the drain voltage represents the output signal and varies with the input signal, then the amplifier is called a common-gate amplifier. When a first NMOS transistor and a second NMOS transistor are stacked together and both are biased as common-gate amplifiers (where the output signal of the first NMOS transistor is the input signal of the second NMOS transistor), these two NMOS transistors together form a common-gate stacked amplifier.

[0060] When an NMOS transistor is in the triode region (where both the gate-source and gate-drain voltages are greater than the critical voltage) when the control signal is established, and in the cut-off region (where both the gate-source and gate-drain voltages are less than the critical voltage) when the control signal is de-established, the NMOS transistor can operate as a switch controlled by the control signal. In one embodiment, when the NMOS transistor is used to implement a switch, this embodiment is a "high-level established" embodiment; specifically, the NMOS transistor is turned on when the control signal is established at a high level.

[0061] Reference Figure 1 This is a schematic diagram of a programmable gain amplifier 100 according to an embodiment of the present disclosure. The programmable gain amplifier 100 includes a programmable resistor ladder 120 and an AC coupling capacitor C. ac A common-gate cascode amplifier multiplexer 110 and an encoder ENC. A programmable resistor ladder 120 is distributed across N. max There are N joint nodes, and they are subject to N max -1 resistor control signal. Where N max N is an integer greater than 1. max For example, but not limited to, 4. N max Each junction node includes a first junction node N11 and the other (remaining) N nodes. max -1 junction nodes N12, N13, N14. N max -1 resistor control signal includes resistor control signals S1, S2, and S3. AC coupling capacitor C ac This is used to couple the input node N10 to the first junction node N11. The common-gate stacked amplifier multiplexer 110 includes N... maxA common-gate stacked amplifier A1, A2, A3, and A4. The common-gate stacked amplifiers A1, A2, A3, and A4 are subjected to N... max Each amplifier is controlled by control signals E1, E2, E3, and E4. Common-gate stacked amplifiers A1, A2, A3, and A4 are used to receive N. max N of the junction nodes N11, N12, N13, and N14 max Each has an internal voltage V1, V2, V3, and V4, and outputs N respectively. max Output current I o1 I o2 I o3 I o4 To the output node N19 with load ZL. The encoder ENC is used to encode the integer N to N1. max -1 resistor control signal S1, S2, S3 and N max The amplifier control signals are E1, E2, E3, and E4. In this paper, "V..." DD "Indicates a power node. The integer N controls the gain setting of the programmable gain amplifier 100. The programmable resistor ladder 120 contains N." max -1 series resistor R r1 R r2 R r3 A parallel resistor R s0 and N max -1 switched resistor circuit SR1, SR2, SR3. N max -1 series resistor R r1 R r2 R r3 Used for N max Connecting nodes N11, N12, N13, and N14 provide a series connection. A parallel resistor R... s0 Used to connect the first junction node N11 in parallel to the reference ground. N max -1 switched resistor circuit SR1, SR2, SR3 is used according to N max -1 resistor control signals S1, S2, and S3, respectively, will control the remaining N... max - One junction node N12, N13, N14 is connected in parallel to the reference ground. The switched resistor circuit SR1 (SR2, SR3) includes a resistor R connected in series. s1 (R s2 R s3 The amplifier consists of switches SW1 (SW2, SW3), where switches SW1 (SW2, SW3) are controlled by resistor control signals S1 (S2, S3). The input impedance of the common-gate cascaded amplifier A1 (A2, A3, A4) as seen from junction nodes N11 (N12, N13, N14) is denoted as Z. a1 (Za2 Z a3 Z a4 The source impedance from the common-gate stacked amplifiers A1 (A2, A3, A4) to the junction node N11 (N12, N13, N14) is expressed as Z. s1 (Z s2 Z s3 Z s4 The input impedance looking towards input node N10 is represented as Z. i .

[0062] The value of the integer N is between 1 and N. max The value between N and N is used to determine the gain of the programmable gain amplifier 100. As shown in the aforementioned embodiment, the N of the programmable gain amplifier 100... max It can be 4. However, this disclosure is not limited to this, N max It can be any value greater than 1.

[0063] The primary objective of the programmable gain amplifier 100 is to provide gain, wherein this gain is determined by the output voltage V at output node N19. o The input voltage V at input node N10 i The gain is defined by the ratio between the two values ​​and can be precisely programmed by setting the value of an integer N. Specifically, only a single common-gate cascaded amplifier in the common-gate cascaded amplifier multiplexer 110 is selected to be turned on (while the remaining / unselected common-gate cascaded amplifiers are turned off), and the length of the programmable resistor ladder 120 is appropriately configured according to the value of the integer N. The length of the programmable resistor ladder 120 determines the attenuation factor of the internal voltage received by the individually selected common-gate cascaded amplifier. In this way, the gain can be programmed.

[0064] The second purpose of the programmable gain amplifier 100 is to provide impedance matching so that the input impedance Z i It is approximately equal to Z0, where Z0 is an impedance matching reference value independent of the integer N. Impedance matching can be achieved by appropriately selecting the input impedance of the individually turned-on common-gate cascaded amplifier and the resistance value of the programmable resistor step 120.

[0065] The third objective of the programmable gain amplifier 100 is to provide excellent reverse isolation so that the output node N19 has minimal interference to the input node N10, i.e., the output voltage V o For the input voltage V iIt has a small kickback. Since the topology of the common-gate stacked amplifier itself has good reverse isolation, the programmable gain amplifier 100 can achieve excellent reverse isolation by using common-gate stacked amplifiers A1, A2, A3, and A4.

[0066] The fourth objective of the programmable gain amplifier 100 is to allow all common-gate stacked amplifiers A1, A2, A3, and A4 to use the same amplification circuit and the same common bias generation circuit, regardless of the value of the integer N.

[0067] In one embodiment, the AC coupling capacitor C ac The impedance is almost less than the reference value for impedance matching, and therefore can be ignored.

[0068] When the resistor control signal S1 (S2, S3) is "1" (i.e., when it is established), the switch SW1 (SW2, SW3) is turned on, and the resistance value of the switch resistor circuit SR1 (SR2, SR3) is approximately equal to the resistance R. s1 (R s2 R s3 Conversely, when the resistor control signal S1 (S2, S3) is "0" (i.e., when it is deactivated), the switch SW1 (SW2, SW3) is closed, and the circuit is open.

[0069] When the amplifier control signals E1 (E2, E3, E4) are "1" (i.e., when established), the common-gate stacked amplifier A1 (A2, A3, A4) is turned on, and the input impedance Z... a1 (Z a2 Z a3 Z a4 Approximately equal to the on-resistance Z a Conversely, when the amplifier control signal E1 (E2, E3, E4) is "0" (i.e., when it is deactivated), the common-gate stacked amplifier A1 (A2, A3, A4) is turned off and presents an open circuit.

[0070] In one embodiment, amplifier control signals E1, E2, E3, and E4 can be encoded according to a multiplexing scheme so that at any given time only one of the amplifier control signals E1, E2, E3, and E4 is established, and different integer values ​​of N will result in different amplifier control signals being established. The multiplexing scheme can be represented by Equations 1 and 2.

[0071]

[0072] For i = 1, 2, 3, ..., N max ………………………(Equation 2)

[0073] In other words, when the integer N is 1 (2, 3, 4), the amplifier control signal E1 (E2, E3, E4) is "1", and the common-gate stacked amplifier A1 (A2, A3, A4) is turned on.

[0074] The resistance control signals S1, S2, and S3 can be encoded according to the thermometer-code scheme so that the total number of established resistance control signals is equal to N-1 (i.e., the integer N minus one). The thermometer-code scheme can be expressed by Equations 3 and 4.

[0075]

[0076] For i = 1, 2, 3, ..., N max …………………(Equation 4)

[0077] In other words, when the integer N is 1, all the switching resistor circuits (SR1, SR2, SR3, etc.) are turned off; when the integer N is 2, the switching resistor circuit SR1 is turned on and the remaining switching resistor circuits SR2 and SR3 are turned off; when the integer N is 3, the switching resistor circuits SR1 and SR2 are turned on and the remaining switching resistor circuit SR3 is turned off; when the integer N is 4, the switching resistor circuits SR1, SR2, and SR3 are all turned on.

[0078] In one embodiment, the parallel resistor R s0 Equal to 3Z0 / 2, series resistance R r1 R r2 R r3 Both are equal to 3Z0 / 2, resistance R s1 R s2 R s3 All are equal to 3Z0, and the on-resistance Z a It equals 3Z0.

[0079] When the integer N is 1, A1 is the only common-gate stacked amplifier that is turned on. The switched resistor circuits SR1, SR2, and SR3 are all turned off, and the source impedance Z seen from the common-gate stacked amplifier A1 is... s1 Equal to parallel resistance R s0 That is, 3Z0 / 2. Input impedance Z i Equal to "R" s0 ||Z a1"||" refers to the impedance matching reference value Z0. Here, "||" indicates a parallel connection. Those skilled in the art will understand that the effective impedance resulting from the parallel connection of the first and second impedances is equal to the product of the first and second impedances divided by the sum of the first and second impedances. That is, Z1||Z2=Z1Z2 / (Z1+Z2). Here, Z1 is the first impedance, and Z2 is the second impedance.

[0080] When the integer N is 2, A2 is the only common-gate cascaded amplifier that is turned on, SR1 is the only switched resistor circuit that is turned on, and the source impedance Z seen from the common-gate cascaded amplifier A2 is... s2 Equal to "R" s1 ||(R r1 +R s0 "), i.e., 3Z0 / 2. Input impedance Z i Equal to "R" s0 ||(R r1 +(R s1 ||Z a2 "))", which is the impedance matching reference value Z0. Furthermore, the series resistance R r1 Resistance R s1 and input impedance Z a2 Form a voltage divider so that the ratio between the internal voltage V2 and the internal voltage V1 is equal to "(R s1 ||Z a2 ) / (R r1 +(R s1 ||Z a2 The attenuation factor is 1 / 2. Thus, the common-gate cascaded amplifier A2 receives only half the input voltage received by the common-gate cascaded amplifier A1 when the integer N is 1 (as in the previous embodiment). In other words, when the integer N changes from 1 to 2, an attenuation factor of 1 / 2 can be achieved.

[0081] When the integer N is 3, A3 is the only common-gate stacked amplifier that is turned on. Switched resistor circuits SR1 and SR2 are turned on while switched resistor circuit SR3 is turned off, and the source impedance Z seen from the common-gate stacked amplifier A3 is... s3 Equal to "R" s2 ||(R r2 +(R s1 ||(R r1 +R s0 ")))", which is 3Z0 / 2. Input impedance Z i Equal to "R" s0 ||(R r1 +(R s1 ||(R r2 +(R s2 ||Z a3 "))))", which is the impedance matching reference value Z0. Furthermore, the series resistance Rr2 Resistance R s2 and input impedance Z a3 Form a voltage divider so that the ratio between the internal voltage V3 and the internal voltage V2 is equal to "(R s2 ||Z a3 ) / (R r2 +(R s2 ||Z a3 The attenuation factor is 1 / 2. Thus, the common-gate cascaded amplifier A3 receives only half the input voltage received by the common-gate cascaded amplifier A2 when the integer N is 2 (as in the previous embodiment). In other words, when the integer N changes from 2 to 3, an attenuation factor of 1 / 2 can be achieved.

[0082] When the integer N is 4, A4 is the only common-gate stacked amplifier that is turned on. Switched resistor circuits SR1, SR2, and SR3 are all turned on, and the source impedance Z seen from the common-gate stacked amplifier A4 is... s4 Equal to "R" s3 ||(R r3 +(R s2 ||(R r2 +(R s1 ||(R r1 +R s0 ")))))", which is 3Z0 / 2. Input impedance Z i Equal to "R" s0 ||(R r1 +(R s1 ||(R r2 +(R s2 ||(R r3 +(R s3 ||Z a4 "))))))", that is, the impedance matching reference value Z0. Furthermore, the series resistance R r3 Resistance R s3 and input impedance Z a4 A voltage divider is formed so that the ratio between the internal voltage V4 and the internal voltage V3 is equal to "(R s3 ||Z a4 ) / (R r3 +(R s3 ||Z a4 The attenuation factor is 1 / 2. Thus, the common-gate cascaded amplifier A4 receives only half the input voltage received by the common-gate cascaded amplifier A3 when the integer N is 3 (as in the previous embodiment). In other words, when the integer N changes from 3 to 4, an attenuation factor of 1 / 2 can be achieved.

[0083] As mentioned earlier, regardless of the integer N: First, the input impedance Z iFirst, the impedance is always equal to the impedance matching reference value Z0, thus achieving impedance matching. Second, when the integer N increases by one, the activated common-gate stacked amplifier receives an input voltage with an additional attenuation factor of 1 / 2, thus achieving precise programmable gain. Third, the same impedance value (i.e., 3Z0 / 2) can be obtained by looking at the programmable resistor step 120 from each activated common-gate stacked amplifier, thus achieving the use of the same common bias voltage generation circuit.

[0084] Reference Figure 2 This is a schematic diagram of a common-gate stacked amplifier A1 according to an embodiment of the present disclosure. Figure 2 This is an embodiment of the present disclosure. Figure 1 (A schematic diagram of the common-gate stacked amplifier A1 of the programmable gain amplifier 100). The common-gate stacked amplifier A1 includes two NMOS transistors 211 and 212 and four switches 221, 222, 223, and 224. The four switches 221, 222, 223, and 224 are controlled by S1 (resistor control signal), S2 (resistor control signal), and S3 (resistor control signal). 1B S1 (resistor control signal), S 1B Control. Among them, S 1B This is the logic inversion signal of the resistor control signal S1. The source, gate, and drain of NMOS transistor 211 are connected to nodes N11, N21, and N22, respectively. The source, gate, and drain of NMOS transistor 212 are connected to nodes N22, N23, and N19, respectively. Node N21 is connected to the first bias voltage V through switch 221. B1 And connected to reference ground via switch 222, so that when the resistor control signal S1 is established, the first gate voltage V of node N21 is G1 Equal to the first bias voltage V B1 Conversely, when the resistor control signal S1 is de-established, the first gate voltage V of node N21... G1 It is connected to the reference ground and has the same potential as the reference ground. Node N23 is connected to the second bias voltage V through switch 223. B2 And connected to reference ground via switch 224, so that when the resistor control signal S1 is established, the second gate voltage V of node N23 is... G2 Equal to the second bias voltage V B2 Conversely, when the resistor control signal S1 is de-established, the second gate voltage V of node N23... G2 The potential is equal to that of the reference ground. When the resistor control signal S1 is de-established, NMOS transistors 211 and 212 are both turned off because nodes N21 and N23 are both connected to the reference ground. When the resistor control signal S1 is established, NMOS transistors 211 and 212 are both turned on, and the input impedance Z... a1 It is based on the first bias voltage VB1 and the second bias voltage V B2 The NMOS transistors 211 and 212 are configured in a stacked structure to provide excellent reverse isolation. Since node N11 is isolated by the two NMOS transistors 211 and 212, the backlash from node N19 can be effectively suppressed. In some embodiments, the common-gate stacked amplifier A1 further includes a logic inversion signal S. 1B An additional switch 225 is used for control. Switch 225 is used to invert the logic signal S. 1B When the resistor control signal S1 is established (or de-established), node N22 is connected to the reference ground. Reverse isolation can be further improved by attempting to connect node N22 to the reference ground when the resistor control signal S1 is de-established.

[0085] By replacing node N11 with node N12 (nodes N13 and N14), replacing resistor control signal S1 with resistor control signal S2 (resistance control signal S3 and S4 (not shown in the figure)), and inverting the logic inversion signal S... 1B By replacing the logic inversion signal of resistor control signal S2 (the logic inversion signal of resistor control signal S3, the logic inversion signal of resistor control signal S4 (not shown in the figure)), the circuit of common-gate stacked amplifier A1 can be used to implement the circuit of common-gate stacked amplifier A2 (the circuit of common-gate stacked amplifier A3, the circuit of common-gate stacked amplifier A4).

[0086] Reference Figure 3 This is a schematic diagram of a bias voltage generating circuit 300 according to an embodiment of the present disclosure. Figure 3 For an embodiment of this disclosure, suitable for use by Figure 2 (Schematic diagram of the bias generation circuit 300 used in the common-gate stacked amplifier A1). The bias generation circuit 300 can generate two bias voltages V. B1 and V B2 The bias generation circuit 300 includes a source resistor 311, a first diode-connected NMOS transistor 321, a second diode-connected NMOS transistor 322, and a current source 331. The bias generation circuit 300 is widely used in the prior art and is well known to those skilled in the art; therefore, a detailed explanation is omitted here. When the gate and drain of an NMOS transistor are connected together, this NMOS transistor is called a diode-connected NMOS transistor.

[0087] In one embodiment, the load ZL is a resistor. In another embodiment, the load ZL is a resonant tank, which includes an inductor and a capacitor connected in parallel.

[0088] For example, but not limited to: the programmable gain amplifier 100 is fabricated on a silicon substrate using 55nm CMOS process technology; the impedance matching reference value Z0 is 50 Ohms; the power node V DD It is 1.5V; the load ZL is connected in parallel with a 1nH (nanohenry) inductor and a 500fF capacitor; the W / L (width / length) of NMOS transistors 211 and 212 is 80μm / 60nm; the output current of current source 331 is 200μA; the source resistor 311 is 750Ohm; the W / L of NMOS transistors 321 and 322 is 8μm / 60nm; and the AC coupling capacitor C ac It is 2pF.

[0089] Those skilled in the art will readily observe that many modifications and variations can be made to the apparatus and method while retaining the teachings of this disclosure. Therefore, the foregoing should not be construed as being defined solely by the statement of the appended claims.

Claims

1. A programmable gain amplifier, comprising: A programmable resistor ladder, configured in N max On each joint node, and subject to N max -1 resistor control signal, where N max It is an integer greater than 1; A total-gate stacked amplifier multiplexer, containing N max A common-gate stacked amplifier, the N max A common-grid stacked amplifier is used in this N max Each junction node receives N max An internal voltage, and according to N max The amplifier control signal will N max Each output current is output to an output node with a load; and An AC coupling capacitor is used to couple an input node to the N-type node. max A first junction node of N junction nodes, wherein the programmable resistance ladder comprises N max -1 series resistor, one parallel resistor, and N max -1 switched resistor circuit, N max -1 series resistor is used to connect in series with this N max At each junction node, the parallel resistor is used to connect N max The first junction node of the N junction nodes is connected in parallel to the reference ground. max -1 switched resistor circuit is used to determine the N max -1 resistor control signal, respectively, to the remaining N max -1 junction node is connected in parallel to the reference ground.

2. The programmable gain amplifier of claim 1 further includes an encoder for receiving an integer N and outputting the N. max -1 resistor control signal and N max Amplifier control signal, where N is a combination of 1 and N max Including 1 and N max Integers between [a certain range].

3. The programmable gain amplifier as described in claim 2, wherein, The N max The amplifier control signal is encoded by the encoder in a multiplexing scheme so that only the N amplifier control signal is used at any given time. max One of the amplifier control signals is established, and different N values ​​will result in different amplifier control signals being established.

4. The programmable gain amplifier as described in claim 3, wherein, The N max -1 resistance control signals are encoded by the encoder in a thermometer code scheme so that the total number of established resistance control signals is equal to N-1.

5. The programmable gain amplifier as described in claim 4, wherein, The parallel resistor and the N max -1 series resistors have the same impedance value 3Z0 / 2, where Z0 is the reference value for impedance matching.

6. The programmable gain amplifier as described in claim 5, wherein, The N max Each of the -1 switched resistor circuits is controlled by a corresponding resistor control signal, and the N... max Each of the -1 switched resistor circuits is turned on when its corresponding resistor control signal is established, to have an input impedance equal to 3Z0, and the N max Each of the -1 switched resistors is turned off and presents an open circuit when the corresponding resistor control signal is de-established.

7. The programmable gain amplifier as described in claim 6, wherein, The N max Each of the N common-gate stacked amplifiers is controlled by a corresponding amplifier control signal. max Each of the N common-gate stacked amplifiers is turned on when its corresponding amplifier control signal is established, to have an input impedance equal to 3Z0, and the N max Each of the common-gate stacked amplifiers is shut down and presents an open circuit when its corresponding amplifier control signal is de-established.

8. The programmable gain amplifier of claim 1, further comprising a bias generation circuit for generating a first bias voltage and a second bias voltage to the N max A common-gate stacked amplifier is biased.

9. The programmable gain amplifier as claimed in claim 8, wherein, The N max Each of the N common-gate stacked amplifiers is controlled by a corresponding amplifier control signal, and the N max Each of the common-gate stacked amplifiers includes a first N-type metal-oxide-semiconductor transistor and a second N-type metal-oxide-semiconductor transistor configured in a stacked structure. When the corresponding amplifier control signal is established, a gate of the first N-type metal-oxide-semiconductor transistor and a gate of the second N-type metal-oxide-semiconductor transistor are respectively connected to the first bias voltage and the second bias voltage. When the corresponding amplifier control signal is de-established, the gate of the first N-type metal-oxide-semiconductor transistor and the gate of the second N-type metal-oxide-semiconductor transistor are connected to reference ground.

10. The programmable gain amplifier as claimed in claim 9, wherein, When the corresponding amplifier control signal is de-established, an internal node between the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor is connected to the reference ground.

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