Scheduling 5g functions using network adapters

Abstract

The present disclosure relates to scheduling 5G functions using a network adapter. A network adapter includes an output coupled to a central processing unit (CPU) of a network device, a first clock coupled to the output and configured to synchronize with the CPU and a second clock external to the network adapter, and a circuit coupled to the first clock. The circuit is configured to generate a tick at a time offset from a slot of a radio schedule of a radio using the synchronized first clock and send the tick to the output.

Description

Technical Field

[0001] This disclosure generally pertains to systems, devices, and methods for scheduling 5G functionality using network adapters. Background Technology

[0002] 5G networks transmit and receive data over the air within discrete time slots scheduled for radio units used for transmitting and receiving data. Simultaneously, the network's baseband processing layer can schedule the transmission and reception operations of radio units based on these radio scheduling time slots. Summary of the Invention

[0003] In an illustrative embodiment, a network adapter includes: an output coupled to a central processing unit (CPU) of a network device; a first clock coupled to the output and configured to synchronize with a second clock external to the CPU and the network adapter; and circuitry coupled to the first clock and configured to: generate a tick at a time offset from a time slot of a radio scheduling of a radio unit using the synchronized first clock; and send the tick to the output.

[0004] In another illustrative embodiment, a network device includes: a CPU; and a network adapter including: an output coupled to the CPU; a first clock coupled to the output and configured to synchronize with a second clock external to the network adapter and the CPU; and circuitry coupled to the first clock and configured to: generate a tick at a time offset from a time slot of radio scheduling of a radio unit using the synchronized first clock; and send the tick to the CPU via the output to cause the CPU to initiate one or more scheduling operations for the time slot.

[0005] In another illustrative embodiment, a method includes: synchronizing a first clock of a network adapter with a second clock external to the network adapter; generating a tick by circuitry of the network adapter using the synchronized first clock at a time offset from a time slot of radio scheduling of a radio unit; and sending the tick to at least one CPU of a network device coupled to the network adapter by the circuitry.

[0006] This article describes additional features and advantages, which will be apparent from the following description and figures. Attached Figure Description

[0007] Figure 1 A system according to at least one exemplary embodiment is shown;

[0008] Figure 2 A diagram illustrating possible configurations of a 5G network according to at least one exemplary embodiment is shown;

[0009] Figure 3 An exemplary implementation of a disaggregated network according to at least one exemplary embodiment is shown;

[0010] Figure 4 The illustration shows at least one exemplary embodiment. Figure 1 Additional details about the system;

[0011] Figure 5A and Figure 5B Different embodiments of a tick handler according to at least one exemplary embodiment are shown;

[0012] Figure 6 Tick ​​generation according to at least one exemplary embodiment is shown; and

[0013] Figure 7 A method according to at least one exemplary embodiment is shown. Detailed Implementation

[0014] 5G networks utilize radio units (i.e., cell towers) that transmit and receive data in discrete time slots. These time slots determine various aspects of 5G baseband processing because the baseband processor, which schedules data transmission and reception on behalf of the radio units, needs precise knowledge of these time slots. For example, approximately one millisecond before a radio unit transmits data to a user equipment (UE), a scheduling layer within the baseband processor (e.g., with layer 2 functionality) schedules transmission for a specific time slot and requests the baseband processor's transport layer (e.g., with layer 1 functionality) to perform the necessary calculations to encode the data into physical symbols, which are then transmitted over the air by the radio unit.

[0015] Some technologies employ software-defined 5G baseband processing to notify the scheduler of elapsed time slots. For example, a Layer 2 work scheduler can periodically initiate necessary Layer 1 processing. This periodicity can be provided by Layer 1 generating notifications or ticks each time a time slot elapses and sending the ticks to Layer 2. One technique for accomplishing this within a device including a network adapter (e.g., a network interface controller (NIC)) involves running at least three threads on the central processing unit (CPU) of the network device connected to the network adapter: a first thread controls the synchronization of the network adapter with a reference time; a second thread synchronizes the internal CPU clock with the network adapter's clock; and a third thread determines when a scheduling cycle has elapsed, i.e., when a "tick" should be generated. Of these three threads, the third thread is the most resource-intensive and most sensitive to latency. For example, if the third thread is temporarily canceled from scheduling and misses the elapsed scheduling cycle, the "tick" generated by Layer 1 will be delayed, potentially resulting in too little time to perform the necessary operations (both in Layer 2 scheduling and the resulting Layer 1 computations). Consequently, transmissions may be delayed or incomplete, reducing network efficiency. To make ticks as accurate as possible, some systems sacrifice entire CPU cores just to check CPU time in a tight loop and generate a tick when the scheduling cycle has expired. This approach is wasteful in terms of consuming CPU resources available for other tasks and in terms of power consumption.

[0016] Furthermore, on some platforms, NIC-to-CPU clock synchronization (the second thread mentioned above) exhibits some inaccuracies and consumes significant resources. It's worth noting that this task involves background kernel threads in addition to the application managing the synchronization, further exacerbating resource usage issues.

[0017] The concept of this invention proposes to at least address the aforementioned problems by utilizing precise time information already available to the NIC (e.g., due to synchronization with the radio unit via Precision Time Protocol (PTP)). Specifically, an exemplary embodiment proposes using a network adapter (such as a NIC) to generate 5G scheduling ticks. In operation, an orchestration layer within a CPU with baseband processing capabilities requests periodic ticks from the NIC (or ticks for a specific time or a list of times). Upon this request, the NIC generates an interrupt for the CPU on each tick, and each tick can be generated and sent to the CPU at a time offset from the time slots used by the radio unit for transmitting and receiving data (e.g., a predetermined time or timing offset or a dynamically determined time offset). This tick interrupt is routed without delay to the CPU connected to the NIC in a dedicated routine (such as a tick handler). The tick handler can then spawn 5G Layer 2 scheduling tasks without involving the operating system scheduler and / or without switching the context to user space. It is understood that the concept of the present invention can eliminate the need for a dedicated CPU thread to continuously check the current CPU time to detect the elapsed scheduling cycle and / or eliminate the need for precise NIC-CPU clock synchronization, as these functions are offloaded to the NIC.

[0018] The following description provides only embodiments and is not intended to limit the scope, applicability, or configuration of the claims. Rather, it will provide those skilled in the art with an advantageous description for implementing the described embodiments. It will be understood that various changes can be made to the function and arrangement of the elements without departing from the spirit and scope of the appended claims.

[0019] As can be understood from the following description, and for computational efficiency reasons, the components of the system can be arranged in any appropriate location in the distributed network of components without affecting the operation of the system.

[0020] Furthermore, it should be understood that the various links connecting the elements can be wired, traced, or wireless links, or any suitable combination thereof, or any other suitable known or later-developed element capable of providing and / or communicating data with the connected element. For example, the transmission medium used as a link can be any suitable carrier of electrical signals, including coaxial cables, copper wires and optical fibers, electrical traces on a PCB, or the like.

[0021] As used in this article, the phrases “at least one,” “one or more,” “or,” and “and / or” are open-ended expressions that are both connective and disconnective in operation. For example, each of the expressions “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, and C,” “one or more of A, B, or C,” “A, B, and / or C,” and “A, B, or C” implies A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0022] The terms “determine,” “calculate,” and “compute,” as used herein, and their variations, are used interchangeably and include any appropriate type of method, process, operation, or technique.

[0023] This document will describe various aspects of the disclosure with reference to the accompanying drawings, which may be schematic diagrams of idealized configurations.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in common dictionaries) should be interpreted as having the same meaning as they have in the relevant technical field and in this disclosure.

[0025] As used herein, unless the context explicitly indicates otherwise, the singular forms of “a,” “an,” and “the” are intended to include the plural forms as well. It will be further understood that the terms “include,” “including,” “includes,” “comprise,” “comprises,” and / or “comprising,” when used in this specification, specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0026] Figure 1A system 100 according to at least one exemplary embodiment is illustrated. System 100 may correspond to a system for 5G cellular communication and includes one or more network devices 104, user equipment (UE) 106, communication networks 108 and 110, and radio units (RU) 112. In at least one exemplary embodiment, network device 104 may correspond to a network switch (e.g., an Ethernet switch), a collection of network switches, or other suitable devices or collections of devices for controlling data flow within system 100. Each network device 104 may be connected to one or more personal computers (PCs), laptops, tablets, smartphones, servers, server collections, etc. In a specific but non-limiting example, each network device 104 is connected to a server or server collection for sending and receiving data.

[0027] Examples of communication networks 108 and / or 110 that may be used within system 100 include Internet Protocol (IP) networks, Ethernet networks, InfiniBand (IB) networks, Fibre Channel networks, the Internet, cellular communication networks, wireless communication networks, combinations thereof (e.g., Fibre Channel over Ethernet), variations thereof, and / or the like. In a specific but non-limiting example, communication network 108 is a network capable of wired communication between network device 104 and RU 112 using electrical and / or optical signals, while communication network 110 is a network capable of wireless communication (e.g., according to 5G, LTE, 3G, and / or similar cellular protocols) between RU 112 and one or more UEs 106.

[0028] One or more network devices 104 may include or communicate with network adapters 116, such as network interface cards or network interface controllers (NICs). One or more network devices 104 may include or communicate with one or more CPUs 120. In a non-limiting example, one or more CPUs 120 at least partially act as baseband processors (also referred to as baseband units (BBUs)) that provide various functions for sending and receiving data within system 100. As described in more detail below, network adapters 116 may act as tick generators that notify CPUs 120 when to initiate scheduling operations. In addition to providing baseband processing functions, each CPU 120 may provide processing resources for one or more virtual machines (VMs) executing one or more applications. One or more CPUs 120 may correspond to ARM-based processors, while one or more CPUs 120 may correspond to x86-based processors.

[0029] Network adapter 116 and one or more CPUs 120 may include storage devices and / or processing circuitry for performing computational tasks, such as tasks associated with data flow within control system 100. This processing circuitry may include software, hardware, or a combination thereof. For example, the processing circuitry may include memory containing executable instructions and a processor (e.g., a microprocessor) that executes the instructions on the memory. The memory may correspond to any suitable memory device type or a collection of memory devices configured to store instructions. Non-limiting examples of suitable memory devices that may be used include flash memory, random access memory (RAM), read-only memory (ROM), variations thereof, combinations thereof, or the like. In some embodiments, the memory and processor may be integrated into a common device (e.g., a microprocessor may include integrated memory). Additionally or alternatively, the processing circuitry may include hardware such as application-specific integrated circuits (ASICs). Other non-limiting examples of processing circuitry include integrated circuit (IC) chips, central processing units (CPUs), general-purpose processing units (GPUs), microprocessors, field-programmable gate arrays (FPGAs), collections of logic gates or transistors, resistors, capacitors, inductors, diodes, or the like. Some or all of the processing circuitry may be provided on a printed circuit board (PCB) or a collection of PCBs. It should be understood that any suitable type of electrical component or collection of electrical components can be appropriately incorporated into the processing circuit.

[0030] Although not explicitly shown, it should be understood that network device 104 may include other processing devices, storage devices, and / or communication interfaces typically associated with computing tasks, such as sending, receiving, and processing data.

[0031] Figure 2 A diagram 200 is shown to illustrate possible configurations for 5G networks, while Figure 3An example implementation of the decomposed network 300 is illustrated. As can be understood from Figure 200, a logical node gNB within a 5G network can connect to the core network (CN) and includes multiple units arranged in one of configurations 204 or 208. Generally, these units can include centralized units (CUs), distributed units (DUs), and radio units (RUs), which perform various operations listed in options 1 to 8 for the logical node gNB. As shown, the configuration of the logical node gNB is defined by various layer functions marked in options 1 to 8. For example, in configurations 204 and 208, the CU can perform RRC, SDAP, and PDCP functions. In configurations 204 and 208, the DU can perform high RLC (Radio Link Control) functions, low RLC functions, high MAC functions, low MAC functions, and high physical layer (PHY) functions. As shown in configuration 204, the DU can further perform low PHY functions, while the RU can perform RF functions. Meanwhile, the RU in configuration 208 can perform both low PHY and RF functions. As also shown in the figure, the logical node gNB may also include a general public radio interface CPRI and / or eCPRI for performing radio access network (RAN) functions. Figure 200 further illustrates the various trade-offs between latency and capacity requirements of the CU-DU interface as the functionality of the logical node gNB becomes more distributed or more centralized.

[0032] Figure 3 The decomposition network 300 includes a core network (CN) 304, CU 308, Du 312, and RU 112. It can be understood that CU 308, Du 312, and RU 112 can be included in... Figure 2 In one or more logical nodes gNB.

[0033] Figure 4 Additional details of system 100 are shown, particularly those of network device 104 that enable it to generate ticks for 5G communication networks.

[0034] like Figure 4 As shown, network adapter 116, such as a NIC, may include outputs 124 coupled to one or more CPUs 120 (also referred to as CPU 120) of network device 104. Outputs 124 may be coupled to CPU 120 when network adapter 116 is connected to a slot (e.g., a PCIe slot) of network device 104. Although not shown, CPU 120 may be communicatively coupled to one or more servers, network switches, or other suitable devices to generate and / or route traffic within a cellular network. In at least one embodiment, CPU 120 executes one or more applications for virtual machines.

[0035] Network adapter 116 may include a first clock 128 coupled to output 124. The first clock 128 is configured to synchronize with a second clock 130 located outside network device 104. In at least one embodiment, the first clock 128 is initially synchronized with the second clock 130 to enable network adapter 116 to perform one or more functions on behalf of CPU 120 that are unrelated to tick generation. Therefore, at least one inventive concept proposes using the already synchronized clock 128 to generate ticks that trigger layer 2 scheduling operations within CPU 120 for scheduling signal transmission and reception operations of RU 112. As a result, CPU 120 avoids using processing resources to track CPU time to achieve the purpose of generating ticks to trigger scheduling cycles, which in turn frees up CPU resources for other tasks and / or reduces power consumption. As discussed in more detail below, scheduling cycles can be triggered based on receive ticks generated by circuitry 132 at time offsets from the time slots during which signals are transmitted and / or received at RU 112. Clocks 128 and 130 may be coupled to each other via suitable hardwired connections (e.g., electrical connections).

[0036] The second clock 130 may be external to the network adapter and CPU 120 and / or the network device 104. The second clock 130 is integrated with or otherwise communicates with the RU 112 and is used to control the timing of various functions of the RU 112 (e.g., signal transmission and / or signal reception functions of the RU 112). The first clock 128 and the second clock 130 may be synchronized with each other according to a suitable protocol, such as Precision Time Protocol (PTP) or Network Time Protocol (NTP). In at least one embodiment, the first clock 128 and the second clock 130 may be independently synchronized with a third clock, such as a Global Navigation Satellite System (GNSS) signal. Each clock may be generated in a suitable manner, for example, using a phase-locked loop (PLL) circuit.

[0037] Here, it should be understood that synchronizing two clocks can include matching the characteristics of the clock synchronized with the other clock. For example, when synchronizing clock 128 with clock 130, one or more of the duty cycle, period (or frequency), and / or amplitude of clock 128 can be controlled to match one or more of the duty cycle, period (or frequency), and / or minimum and maximum amplitude of clock 130. For example, in at least one embodiment, clock 128 may be controlled to have the same frequency as clock 130. In another example, the characteristics between the clocks (duty cycle, period, minimum / maximum amplitude, etc.) do not necessarily have to match, but can have some known relationship that allows each clock to know the characteristics of the other clock. For example, synchronizing clock 128 with clock 130 can include providing clock 128 with information about the characteristics of clock 130 (duty cycle, period, minimum / maximum amplitude), so that clock 128 knows its timing relative to clock 130, thereby effectively synchronizing clock 128 to clock 130. Network adapter 116 may further include circuitry 132 coupled to a first clock 128, which generates a tick at a time offset from at least one time slot and sends the tick to output 124. Circuitry 132 may generate the tick as an interrupt, prompting tick handler 148 to initiate a layer 2 scheduling task, potentially without involving the operating system scheduler and / or requiring a switch to user-space context. In other words, the tick acts as an interrupt for CPU 120, initiating one or more scheduling operations at CPU 120 to schedule data transmission or reception from and to RU 112. This interrupt may be a message signaling interrupt (e.g., an MSI or MSI-X interrupt) transmitted via channel 140, implemented via the PCIe bus to a specific core of CPU 120 (where the specific core is determined by an interrupt affinity mechanism in hardware). Therefore, circuitry 132 includes suitable hardware and / or software for generating this "tick interrupt" at a time slot offset. In at least one embodiment, the interrupt may correspond to an INTx interrupt sent via the PCI bus or another suitable interrupt sent via another suitable medium.

[0038] It is understood that interrupts typically do not carry auxiliary information. However, in one embodiment, a non-standard implementation of a tick may include auxiliary information within the interrupt itself. Alternatively or additionally, a mechanism other than an interrupt may be used to transfer the tick from circuit 132 to CPU 120, wherein such a mechanism is capable of transferring the tick along with auxiliary information. For example, an exemplary embodiment may employ a dedicated CPU instruction that suspends program execution on CPU 120 until a memory location changes its value. For example, x86 processors include a MONITOR / MWAIT instruction that “suspends” CPU 120 until the memory referenced by the address given to the MONITOR / MWAIT instruction changes its value. In this case, the tick is implemented as a write from the memory of circuit 132 that changes the value in the memory and resumes operation of CPU 120. In this case, the value written to the memory of CPU 120 by NIC 116 may carry some auxiliary information. The auxiliary information may include the time when the tick was generated or should have been generated and / or opaque data provided by CPU 120 to circuit 132 when a tick is requested. For example, CPU 120 can request two types of ticks—a set of ticks T with an interval of 500µs carrying the information "A". A And another set of ticks T, spaced 125µs apart, carrying the information "B". B So that the CPU 120 can distinguish the tick "T". A "and "T B ".

[0039] Understandably, MONITOR / MWAIT is a privileged instruction and kernel space solution. However, this instruction enables network adapter 116 to package auxiliary information with ticks while still conforming to transport standards (e.g., PCIe standards).

[0040] In at least one embodiment, the tick can be implemented using the UMONITOR / UMWAIT instruction, which achieves the same goal as the MONITOR / MWAIT instruction, except that the UMONITOR / UMWAIT instruction allows the application to request the CPU 120 to suspend instruction execution until the memory location value changes. In this case, the tick can be passed directly to the application on the CPU 120 via circuit 132, bypassing the kernel space. The following is an example of the operating modes of a 5G L2 scheduler.

[0041]

[0042] It is understood that the above-described UMONITOR / UMWAIT implementation of Tick is entirely contained within user space. In one example of the instruction-based Tick implementation, a tick is a non-published memory write to a pre-configured memory address. In another example, a tick is a published memory write to a pre-configured memory address. In any case, the value used for memory writes can be a pre-configured value (e.g., a randomly selected value), the actual time at which the tick is generated (e.g., within a clock time), and / or the sequence number of the tick in the tick sequence.

[0043] According to an exemplary embodiment, a time slot can be used to send or receive data and / or control signals from or to RU 112. Therefore, the duration of the time slot is based on a standard used for wireless communication. In at least one embodiment, this standard corresponds to one or more standards used for wireless communication in a 5G cellular network. It is understood that a time slot can be one of multiple time slots, and circuit 132 can generate ticks at time offsets from selected time slots among the multiple time slots. The duration of the time slot may depend on the timing scheme employed by the cellular 5G network. For example, each time slot may have a duration of 1 ms, 500 μs, 250 μs, 125 μs, 62.5 μs, or other suitable time slot durations for sending and receiving signals from RU 112. It is noteworthy that the clock frequencies of synchronization clocks 128 and 130 can be the same and have a known relationship with the time slot. For example, the switching period of clock 128 may have a duration matching the duration of the time slot or a duration several times the duration of that time slot, so that circuit 132 knows when to generate ticks based on the frequency of clock 128.

[0044] CPU 120 includes layers 152 and 156, implemented using appropriate hardware and / or software for performing layer 2 and layer 1 functions, respectively. For example, see reference... Figure 2-4 Layer 152 may be included in DU 312 and performs Layer 2 functions (or data link layer functions), which may include MAC functions, RLC functions, and / or similar functions. Meanwhile, Layer 156 may be included in DU 312 and performs Layer 1 functions (or physical layer PHY functions), which may include low PHY and / or RF functions (e.g., encoding functions). According to an exemplary embodiment, CPU 120 uses precise timing knowledge of the received ticks to trigger Layer 2 scheduling operations. Consider an example where the time slot duration is 500 μs, and CPU 120 needs 1 ms to schedule and encode data for transmission to UE 106. In this case, receiving a tick by tick handler 148 can trigger scheduling and encoding operations in Layers 152 and 156 so that data is scheduled, encoded, and transmitted over two time slots (or 1 ms) after the initial time slot.

[0045] Network adapter 116 may also include an input 136 configured to receive a request from one or more CPUs 120 for tick generation by prompting circuitry 132. In at least one exemplary embodiment, an orchestrator 144 of CPU 120 sends the request when input 136 is connected to CPU 120 (e.g., when network adapter 116 is installed into network device 104). Orchestrator 144 may include suitable hardware and / or software for managing, coordinating, and / or organizing the processing resources of CPU 120. The request may include information relating to tick generation, such as indications of when to send ticks and how frequently ticks are sent. In one embodiment, the request includes information identifying a time offset for sending ticks compared to a radio scheduling time slot of RU 112, a unique identifier for requesting CPU 120, and / or other information that circuitry 132 deems useful. In at least one embodiment, the request includes an indication of a start time for when circuitry 132 should begin sending ticks (circuitry 132 may use the start time as a reference time for time-aligned ticks). Generally, a single request from orchestrator 144 to circuit 132 is sufficient to ensure that circuit 132 sends ticks at the time offset of each time slot. However, if, for example, CPU 120 becomes aware that the duration of a time slot has changed, CPU 120 can send an additional request.

[0046] In at least one embodiment, orchestrator 144 and circuit 132 may perform appropriate authentication processes between each other to ensure that a specific CPU 120 is authorized to begin receiving ticks from circuit 132. For example, network adapter 116 receives a public key from a security entity (such as orchestrator 144, a hypervisor, or a suitable network node). The public key may be associated with or generated for a host communicating with orchestrator 144 (e.g., a physical host with CPU 120 or a virtual machine running on CPU 120), where the host is requesting ticks. The public key may be associated with a specific private key, and network adapter 116 may know the public-private key pair due to a previous registration process with the security entity. The host may provide its digital signature (e.g., a unique identifier) ​​as part of its request to orchestrator 144 to generate ticks. The host's digital signature may include a unique identifier for the host and a private key associated with the public key provided to network adapter 116. Orchestrator 144 may then provide the host's digital signature and private key to network adapter 116. Then, network adapter 116 (e.g., using circuitry 132) can verify whether the host's signature includes a private key corresponding to the public key received by network adapter 116 from orchestrator 144, or is signed with a private key corresponding to the public key received by network adapter 116 from orchestrator 144. If so, network adapter 116 determines that the host is authorized to receive ticks and begins sending ticks to the host at the requested intervals. If not, network adapter 116 determines that the host is not authorized to receive ticks and notifies orchestrator 144 of this. As a result, network adapter 116 does not provide ticks to the host because the host is not authorized.

[0047] In an example with two physical hosts (e.g., a multi-host scenario involving an ARM host and an x86 host, or two x86 hosts), such hosts can be identified based on their connection to the PCIe channels of network adapter 116. For example, in a scenario using both ARM and x86 hosts, it might be necessary to restrict tick requests to the ARM host only. It can be determined that the ARM host is connected to physical PCIe channels enumerated as 0...M-1, while the x86 host is connected to channels M...N-1 (the PCIe channels used by the ARM host may be simulated, but are still enumerated in some way from the perspective of network adapter 116). Network adapter 116 can be pre-configured to allow tick requests received through PCIe channels connected to the ARM host and reject tick requests received through PCIe channels connected to the x86 host. In other words, network adapter 116 authorizes tick requests received through certain PCIe channels while rejecting tick requests received through others. It should be understood here that the exemplary embodiments are not limited to PCIe implementation schemes, and other suitable host interconnect interfaces, such as CXL, NVLink and / or similar interfaces, may be used.

[0048] In another example where multiple virtual machines (VMs) are coupled to network adapter 116, orchestrator 144 or hypervisor may provide tick functionality to some VMs but not to others. A given VM can use a specific virtual function of network adapter 116 to interact with it. By checking whether the virtual function receiving the request at network adapter 116 is also authorized to receive ticks, the VM requesting a tick can be identified and authenticated. If so, network adapter 116 begins sending ticks to the authenticated VM; otherwise, the requesting VM is unauthenticated, and network adapter 116 does not send ticks.

[0049] It is understood that CPU 120 is coupled to network adapter 116 via channel 140, which transmits ticks from output 124 to CPU 120. Channel 140 may correspond to an electrical connection (e.g., a PCI or PCIe bus) or other suitable hardwired connection (e.g., an electrical or optical connection) between network adapter 116 and CPU 120, with the single purpose of transmitting ticks. However, exemplary embodiments are not limited thereto, and channel 140 may transmit other signals depending on design preferences (e.g., when the interrupt type is an in-band MSI-X interrupt). For example, in at least one embodiment, orchestrator 144 may provide the aforementioned tick request via channel 140 so that input 136 can be omitted or bypassed.

[0050] Although exemplary embodiments have been discussed with reference to network adapter 116 generating ticks for a single CPU 120, it should be understood that the output 124 of network adapter 116 can be coupled to one or more additional CPUs 120 to provide the same ticks to one or more additional CPUs 120, thereby triggering layer 2 and layer 1 scheduling and encoding operations of one or more additional CPUs 120 in the same manner as described above. In at least one exemplary embodiment, network adapter 116 provides one or more additional ticks to one or more additional CPUs 120. That is, each CPU 120 can request circuitry 132 to send a tick specific to a particular CPU 120 so that ticks are sent to all CPUs 120 according to its desired timing. For example, a first CPU 120 operates according to a 500μs time slot, while a second CPU 120 operates according to a 1ms time slot. Therefore, each CPU 120 can request circuit 132 to generate corresponding ticks according to different time slots, so that a tick is sent to the first CPU 120 within a 500μs time slot, and a tick is sent to the second CPU 120 within a 1ms time slot. In this case, each request received by circuit 132 from CPU 120 may include the identifier of CPU 120 (e.g., the identifier of the host mentioned above and / or a key, such as a universally unique identifier (UUID)), which enables circuit 132 to identify, (optionally) authenticate, CPU 120, and send the appropriate tick to CPU 120.

[0051] Figure 5A and Figure 5B Different implementations of the tick handler 148 according to an exemplary embodiment are shown. Figure 5A and Figure 5B In this context, the tick handler 148 can be implemented using an interrupt service routine (ISR). Figure 5A The kernel space implementation scheme used to make L2 scheduling decisions is shown. Figure 5B A userspace implementation scheme for making L2 scheduling decisions is shown. Figure 5A In this configuration, the ISR is integrated with layer 152, which makes L2 scheduling decisions. In this case, the ISR is "wake up" by a tick as an interrupt, received by the tick handler 148, and the scheduling decision is made as part of the interrupt handling process by the ISR. In other words, Figure 5A This demonstrates an example of scheduling decisions being made by CPU threads within the CPU 120 core space, which could potentially lead to faster scheduling. Meanwhile, Figure 5B An example is shown in which the tick handler 148, implemented as an ISR, is not integrated with layer 152, so that L2 scheduling decisions are made by the user-space thread of CPU 120, which saves kernel space processing resources.

[0052] Figure 6 The generation of ticks according to at least one exemplary embodiment is shown. Figure 6 Time slots 1-3 for radio scheduling are shown, and a “tick scheduling” is further shown, which indicates the time or timing offset of a tick in relation to a specific time slot of radio scheduling. In general, it can be said that for every N time slots of radio scheduling, circuit 132 generates ticks with some offset relative to the corresponding time slot (e.g., an offset relative to the start or end time of the time slot).

[0053] As can be understood, the time or timing offset can be predetermined (e.g., the timing offset is requested by the orchestrator 144) and / or dynamically determined by the circuit 132. In one embodiment, the timing offset of a tick with respect to a time slot takes into account one or more types of delay, such as delays associated with signal propagation from the circuit 132 to the tick handler 148 and / or network delays in cases where other traffic is passing through the same link as the tick. As long as the link length between the circuit 132 and the tick handler 142 remains relatively constant, the delay associated with signal propagation can be relatively static, and the circuit 132 can resolve static delays by sending each tick in a manner that resolves such static delays. Meanwhile, the delay associated with network traffic can vary based on the amount of traffic and can be periodically measured by the circuit 132 at regular or irregular intervals. In this case, the circuit 132 can send each tick in a manner that resolves the most recently measured delay.

[0054] Each time slot in the radio scheduling can correspond to a time period in the cellular network (e.g., a 5G network) for sending and receiving data from RU 112 and / or scheduling data for sending or receiving at CPU 120. In other words, RU 112 sends and receives data according to the radio scheduling, while CPU 120 schedules the send and receive operations from RU 112 according to the tick scheduling, and the tick scheduling has a known relationship with the radio scheduling (i.e., it is synchronized with the radio scheduling).

[0055] The time slots of the radio schedule shown can be determined according to clock 130, and clock 128 can be synchronized with the time slots of the radio schedule (as indicated by the dashed rectangle in the "tick schedule"). As described above, each time slot in the radio schedule can have a duration of 1 ms, 500 μs, 250 μs, 125 μs, 62.5 μs, or other suitable durations for transmitting and receiving operations from RU 112. In one example, each time slot in the radio schedule has the same duration. However, the exemplary embodiments are not limited to this, and the duration of the time slots can vary for the radio schedule according to design preferences. For example, the duration of every other time slot in the radio schedule may be longer than the middle time slot. Although three time slots are shown, additional time slots may exist as indicated by the horizontal ellipsis. As indicated by the vertical ellipsis, other radio schedules (e.g., 5G radio schedules) may also exist for a particular RU 112 or a particular set of RU 112, with corresponding sets of time slots having the same or different durations as time slots 1-3. Similarly, multiple tick schedules can exist so that each radio schedule has its own tick schedule.

[0056] Figure 6 In this context, tick scheduling refers to the timing offset of ticks relative to a specific time slot in the radio schedule. Specifically, Figure 6 An example is shown where ticks are generated by circuit 132 and sent to CPU 120 every other time slot for radio scheduling. For ease of explanation, Figure 6 The dashed rectangles in the tick scheduling correspond to time slots in 5G radio scheduling, where each time slot in the radio scheduling is assumed to have the same duration. As shown, circuit 132 generates and transmits tick 1 for time slot 1 at a timing offset from time slot 1. Figure 6 In the example, the timing offset corresponds to the time between the generation of tick 1 by circuit 132 and the start of time slot 1. According to an exemplary embodiment, tick 1 causes CPU 120 to initiate a scheduling operation (e.g., a layer 2 scheduling operation) for data transmission and / or reception of RU 112 during time slot 1. Similarly, circuit 132 generates and transmits tick 2 at a timing offset from time slot 3, and tick 2 causes CPU 120 to initiate a scheduling operation for data transmission and / or reception of RU 112 during time slot 3.

[0057] As can be understood, the timing offsets for tick 1 and tick 2 are the same; however, the exemplary embodiment is not limited thereto, and the timing offset between the tick and the start of the radio scheduling time slot can be configurable (e.g., the timing offset can vary within a particular radio schedule). The timing offset can be a design parameter set based on empirical evidence and / or preference. In one example, the timing offset of a tick associated with a relevant time slot of the radio schedule is set based on the known or estimated amount of time that CPU 120 spends scheduling transmit and / or receive operations for a specific time slot. In other words, CPU 120 spends at least a portion of the time period corresponding to the timing offset to schedule data transmit and / or receive operations for transmitting and / or receiving data during the time slot associated with the tick.

[0058] In at least one embodiment, CPU 120 notifies circuitry 132 of the frequency and / or timing of generating and sending ticks. In other words, CPU 120 may determine or otherwise have information about the length of the timing offset of the tick. For example, orchestrator 144 includes such information in a request sent via input 136 when network adapter 136 is connected to CPU 120. Orchestrator 144 may determine the periodicity of tick generation (e.g., stable or variable) based on one or more factors, such as the estimated time taken for CPU 120 to complete a scheduling operation for a specific time slot, available processing resources, and / or similar factors. In at least one example, ticks may be generated and sent to CPU 120 all at once. In this case, circuitry 132 may generate a single tick and send a single tick to CPU 120 to trigger one or more operations (not necessarily scheduling operations) at CPU 120.

[0059] As mentioned above, tick scheduling is associated with radio scheduling and indicates the timing offset of ticks related to specific time slots of the radio schedule. Although Figure 6 The timing offset of the tick is shown relative to the start time of a slot in the radio schedule, but the timing offset can be generated based on the end time of the slot and / or some known time between the start and end of the slot. As mentioned above, the radio schedule can contain slots with variable durations, such that, for example, every second slot is 1.35 times longer than the others.

[0060] Figure 7 A method 600 according to at least one exemplary embodiment is shown. Method 600 may be derived from the above-described embodiments. Figure 1-6 This is performed by one or more components. Therefore, refer to... Figure 1-6 Method 600 is discussed. One or more operations in method 600 may be omitted or performed in a different order than shown. Other operations not explicitly shown may also be part of method 600.

[0061] Operation 604 includes receiving a request from at least one CPU 120 by network adapter 116, the request prompting circuitry 132 to generate a tick at an offset from the time slot of radio scheduling of radio unit 112. This request may be generated by orchestrator 144 and received by circuitry 132 in the same manner as discussed above with reference to the other figures. The request may include information identifying when circuitry 132 should generate a tick and send a tick to CPU 120 and / or the frequency of generating and sending ticks to CPU 120. In at least one embodiment, the request includes information useful for authenticating CPU 120. For example, the request may include the digital signature discussed above, including the host identifier and / or the private key of the private-public key pair. Alternatively, the entity requesting the tick from network adapter 116 may be authenticated by network adapter 116 in another suitable manner (e.g., by determining whether the requesting entity is connected to certain PCIe channels of network adapter 116).

[0062] Operation 608 includes synchronizing a first clock 128 of network adapter 116 with a second clock 130 located external to network adapter 116 (and generally, external to at least one CPU 120). For example, according to Figures 1 to 5B The description states that clocks 128 and 130 are synchronized with each other using a suitable technology (e.g., PTP technology). Typically, there are three synchronization options: 1) clock 130 of RU 112 is synchronized with clock 128; 2) clock 128 is synchronized with clock 130 of RU 112; or 3) clocks 128 and 130 are synchronized with an external or third-party clock (…). Figure 4 (Not displayed in the text) Synchronization.

[0063] Operation 612 includes circuitry 132 of network adapter 116 generating ticks at time offsets from the time slots using a synchronized first clock. Generally, for each Nth time slot of the radio scheduling, circuitry 132 generates a tick offset from the corresponding time slot. For example, circuitry 132 monitors the synchronized first clock 128 to track the Nth time slot of the radio scheduling and outputs an electrical signal as a tick to output 124 at a time offset from the start of the Nth time slot. As described above, each time slot may correspond to the duration for which RU 112 transmits or receives data.

[0064] Operation 616 includes sending a tick to at least one CPU 120 via circuitry 132. For example, sending a tick via channel 140.

[0065] Operation 620 includes initiating one or more scheduling operations by at least one CPU 120 in response to receiving a tick, the scheduling operations scheduling the transmission or reception of data during a time slot. For example, tick handler 148 according to... Figure 5A and Figure 5B The kernel space implementation or user space implementation shown in the figure initiates one or more scheduling operations within layer 152.

[0066] As will be understood, the exemplary embodiments propose offloading tick generation, which typically consumes an entire CPU core, to a network adapter, such as a NIC, which, in some cases, already possesses precise timing knowledge due to clock synchronization with the radio unit for other reasons. The result is more reliable and accurate tick generation, which in turn improves system performance because the scheduling operations triggered by the ticks are also reliably and precisely timed. Furthermore, CPU processing resources can be saved and / or system power consumption can be reduced because the CPU does not need to dedicate all or part of its cores to timing for tick generation. Although exemplary embodiments have been shown and described with respect to 5G networks, the concepts of the present invention can be applied to other types of networks (e.g., 4G LTE networks, 3G networks, data center switching networks). These and other advantages and practical applications should be apparent to those skilled in the art.

[0067] Specific details are set forth in the specification to provide a thorough understanding of the embodiments. However, those skilled in the art will understand that embodiments of the invention can be practiced without these specific details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail to avoid obscuring the embodiments.

[0068] While exemplary embodiments of the present disclosure have been described in detail herein, it should be understood that the concepts of the invention may be embodied and employed in other ways, and the appended claims are intended to be construed as including such variations, unless limited by the prior art.

[0069] It should be understood that the inventive concept encompasses any embodiment combined with any or more other embodiments, any or more features disclosed herein, any or more features substantially disclosed herein, any or more features substantially disclosed herein combined with any or more other features substantially disclosed herein, any aspect / feature / embodiment disclosed herein combined with any or more other aspects / features / embodiments, and the use of any or more embodiments or features disclosed herein. It should be understood that any feature described herein may be combined with any other feature described herein to make a claim, regardless of whether such features are derived from the same described embodiment.

[0070] The exemplary embodiment is configured as follows:

[0071] (1) A network adapter, comprising

[0072] The output is coupled to the central processing unit (CPU) of the network device.

[0073] A first clock, coupled to the output and configured to be synchronized with a second clock external to the CPU and the network adapter; and

[0074] A circuit, coupled to the first clock, is configured as follows:

[0075] Using a synchronized first clock, in the time slot of the radio scheduling of the radio unit.

[0076] A tick is generated at the time offset; and

[0077] Send the tick to the output.

[0078] The network adapter described in (2)(1) also includes

[0079] The input is configured to receive a request from the CPU that prompts the circuit to generate the tick at the time offset.

[0080] (3) A network adapter of one or more of (1) to (2), wherein the input receives the request after the input is connected to the CPU.

[0081] (4) A network adapter of one or more of (1) to (3), wherein the duration of the time slot is based on a standard for wireless communication.

[0082] (5)(1) to (4) of a network adapter, wherein the first clock and the second clock are synchronized with a third clock other than the first clock and the second clock.

[0083] (6) A network adapter of one or more of (1) to (5), wherein the tick is implemented as an interrupt of the CPU.

[0084] (7) One or more of the network adapters in (1) to (6), wherein the interrupt initiates one or more scheduling operations at the CPU for scheduling the transmission or reception of data.

[0085] (8) A network adapter of one or more of (1) to (7), wherein the first clock is configured to synchronize with the second clock using the Precision Time Protocol (PTP).

[0086] A network adapter of one or more of (9)(1) to (8), wherein the time slot is one of a plurality of time slots of the radio scheduling, and wherein the circuit generates a tick at a time offset from a selected time slot of the plurality of time slots.

[0087] (10) A network adapter of one or more of (1) to (9), wherein the output is coupled to one or more additional CPUs to provide one or more additional ticks to the one or more additional CPUs.

[0088] (11) A network device, comprising:

[0089] CPU; and

[0090] Network adapter, including:

[0091] The output is coupled to the CPU;

[0092] A first clock, coupled to the output and configured to be synchronized with a second clock external to the network adapter and the CPU; and

[0093] A circuit, coupled to the first clock, is configured as follows:

[0094] Using a synchronized first clock, ticks are generated at the time offset from the radio scheduling time slot of the radio unit; and

[0095] The output sends the tick to the CPU, causing the CPU to initiate one or more scheduling operations for the time slot.

[0096] The network devices of (12)(11) also include:

[0097] A channel that transmits the ticks from the output to the CPU.

[0098] A network device comprising one or more of (13)(11) to (12), wherein the network adapter further comprises:

[0099] The input is configured to receive a request from the CPU that prompts the circuit to generate the tick at the time offset.

[0100] A network device of one or more of (14)(11) to (13), wherein the CPU is configured to generate the request when the CPU is connected to the input of the network device.

[0101] (15) (11) to (14) of a network device, wherein the duration of the time slot is based on one or more wireless communication standards of a 5G cellular network.

[0102] A network device comprising one or more of (16)(11) to (15), further comprising:

[0103] The radio unit includes the second clock and one or more antennas for wirelessly transmitting or receiving data.

[0104] One or more of the network devices in (17)(11) to (16), further comprising:

[0105] One or more additional CPUs, wherein the output of the network adapter provides the ticks to the certified CPU of the one or more additional CPUs.

[0106] (18) A method, including

[0107] Synchronize the first clock of the network adapter with a second clock external to the network adapter;

[0108] The network adapter's circuitry, using a synchronized first clock, generates ticks at time offsets from the radio scheduling time slots of the radio unit; and

[0109] The circuit sends the ticks to at least one CPU of the network device coupled to the network adapter.

[0110] The methods of (19)(18) also include:

[0111] The network adapter receives a request from the at least one CPU, the request prompting the circuit to generate the tick, wherein the request includes information identifying the time offset and information used by the network adapter to authenticate the at least one CPU.

[0112] The method of one or more of (20)(18) to (19) further includes:

[0113] In response to receiving the tick, the at least one CPU initiates one or more scheduling operations that schedule the transmission or reception of data during the time slot.

Claims

1. A network adapter, comprising: The output is coupled to the central processing unit (CPU) of the network device via a communication bus; A first clock, coupled to the output and configured to be synchronized with a second clock of a radio unit external to the CPU and the network adapter, the radio unit being configured to communicate wirelessly with the user equipment; Input, the input being used to receive a request from the CPU, the request including information identifying the time offset of a time slot in the radio scheduling of the radio unit; as well as A circuit, coupled to the first clock, is configured as follows: The ticks are generated using a synchronized first clock; as well as The tick is sent to the CPU via the output and via the communication bus at the time offset of the time slot of the radio scheduling, such that the tick causes the CPU to perform one or more scheduling operations between the time when the CPU receives the tick and the start of the time slot, wherein the one or more scheduling operations schedule data within the time slot for wireless transmission by the radio unit to the user equipment or wireless reception by the radio unit from the user equipment.

2. The network adapter of claim 1, wherein the request includes information used by the network adapter to authenticate to the CPU of the network adapter.

3. The network adapter of claim 1, wherein the input receives the request after the input is connected to the CPU.

4. The network adapter of claim 1, wherein the duration of the time slot is based on a standard for wireless communication.

5. The network adapter of claim 1, wherein the first clock and the second clock are synchronized with a third clock other than the first clock and the second clock.

6. The network adapter of claim 1, wherein the tick is implemented as an interrupt of the CPU.

7. The network adapter of claim 1, wherein the tick is implemented as an internal memory write.

8. The network adapter of claim 1, wherein the first clock is synchronized with the second clock using the Precision Time Protocol (PTP).

9. The network adapter of claim 1, wherein the time slot is one of a plurality of time slots of the radio scheduling, and wherein the circuitry generates and transmits ticks at a time offset from a selected time slot among the plurality of time slots.

10. The network adapter of claim 1, wherein the output is coupled to one or more additional CPUs to provide one or more additional ticks to the one or more additional CPUs.

11. A network device, comprising: Communication bus; CPU; as well as Network adapter, including: The output is coupled to the CPU via the communication bus; A first clock, coupled to the output and synchronized with a second clock of a radio unit external to the network adapter and the CPU, the radio unit being configured to communicate wirelessly with the user equipment; Input, the input being used to receive a request from the CPU, the request including information identifying the time offset of a time slot in the radio scheduling of the radio unit; and A circuit, coupled to the first clock, is configured as follows: The ticks are generated using a synchronized first clock; and The tick is sent to the CPU via the output and via the communication bus at the time offset of the time slot of the radio scheduling, such that the tick causes the CPU to perform one or more scheduling operations between the time when the CPU receives the tick and the start of the time slot, wherein the one or more scheduling operations schedule data within the time slot for wireless transmission by the radio unit to the user equipment or wireless reception by the radio unit from the user equipment.

12. The network device of claim 11, wherein the communication bus includes a dedicated channel for transmitting the tick from the output to the CPU.

13. The network device of claim 11, wherein the request includes information used by the network adapter to authenticate the CPU.

14. The network device of claim 11, wherein the CPU is configured to generate the request when the CPU is connected to the input of the network adapter.

15. The network device of claim 11, wherein the duration of the time slot is based on one or more wireless communication standards of a 5G cellular network.

16. The network device of claim 11, further comprising: The radio unit includes one or more antennas that wirelessly transmit or receive the data.

17. The network device of claim 16, further comprising: One or more additional CPUs, wherein the output of the network adapter provides the ticks to the certified CPU of the one or more additional CPUs.

18. A method for operating a network adapter, comprising: The first clock of the network adapter is synchronized with the second clock of a radio unit external to the network adapter, the radio unit being configured to communicate wirelessly with the user equipment; The network adapter receives a request from at least one CPU connected to the network adapter and the radio unit, the request including: Information identifying the time offset of the radio scheduling slots of the radio unit; and The network adapter is used to authenticate information about the at least one CPU; The network adapter circuitry generates ticks using a synchronized first clock; and At the time offset of the time slot of the radio scheduling, the circuit sends the tick to the at least one CPU via a communication bus, such that the tick causes the at least one CPU to perform one or more scheduling operations between the time when the at least one CPU receives the tick and the start of the time slot, wherein the one or more scheduling operations schedule data within the time slot for wireless transmission by the radio unit to the user equipment or wireless reception by the radio unit from the user equipment.

19. The method of claim 18, further comprising: The request is generated by the at least one CPU when it is connected to the network adapter.

20. The method of claim 18, further comprising: In response to receiving the tick, the at least one CPU initiates one or more scheduling operations.

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