Performing asynchronous memory clock changes on multi-display systems

CN116635929BActive Publication Date: 2026-08-28ATI TECHNOLOGIES ULC
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Patent Information

Application Number
CN202180086001.0
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2020-12-22
Filing Date
2021-12-16
Publication Date
2026-08-28
Estimated Expiration
2041-12-16

AI Technical Summary

Benefits of technology

[0005]在多个工作负载(例如，游戏渲染、视频处理)正在访问存储器子系统的场景中，存储器子系统可以以其最大可能频率进行时钟计时以确保存储器子系统可以处理大量的读和写。在一些情况下，当存储器子系统未过度紧张时，系统可能期望降低存储器时钟频率以便降低功率消耗。改变存储器时钟频率可能需要在存储器接口上执行训练会话、配置/模式改变或需要暂时停止访问的另一动作。然而，在多显示器系统中，每个显示器可具有与将像素驱动到显示器相关联的不同时序性质。当存储器接口需要被重新训练时或当需要执行其他类型的模式改变时，这使得难以或不可能找到足够的持续时间来停止所有存储器访问而不在任何显示器上引入视觉伪影。因此，在一些系统中，存储器时钟可能被迫保持在最大频率或其他预先确定的频率。因此，多个显示器的功率消耗可能是显著的。随着现代集成电路(IC)的功率消耗增加，利用更昂贵的冷却系统(诸如更大的风扇、更大的散热器和用于控制环境温度的系统)来去除多余的热量并防止IC故障。这还可能导致更响亮的声音，并且因此导致不愉快的客户体验。

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Abstract

Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. At times, a memory subsystem storing frame buffers for driving pixels to multiple displays requires a memory clock frequency change. For example, when real-time memory bandwidth requirements differ from the available memory bandwidth at an existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter a panel self refresh (PSR) mode. Once the PSR mode of the second display overlaps with the VBI of the first display, a memory clock frequency change including a memory training is initiated. After the memory clock frequency change, the displays are driven at an updated frequency by the frame buffers in the memory subsystem.
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Claims

1. An apparatus comprising: The tracking unit includes a circuit, wherein, in response to determining that a condition for changing the memory clock frequency of the memory subsystem is met, the tracking unit is configured to: Track the vertical blanking interval (VBI) timing of the first display device to detect the occurrence of VBI in the first display device; The second display device, which is different from the first display device, is switched to panel self-refresh (PSR) mode; and The circuit includes a frequency adjustment unit configured to adjust the memory clock frequency when the occurrence of the VBI of the first display device is detected and the second display device is in the PSR mode.

2. The device of claim 1, wherein the adjustment causes the memory clock frequency to change from a first frequency to a second frequency different from the first frequency.

3. The device of claim 1, wherein the condition for changing the memory clock frequency includes a memory bandwidth requirement that differs from the memory bandwidth available at the memory clock frequency by more than a threshold.

4. The device of claim 1, wherein the tracking unit is further configured to cause the second display device to exit PSR mode after the adjustment of the memory clock frequency.

5. The device according to claim 1, wherein the device is further configured to: To put the second display device into partial PSR mode; and When the refresh portion of the partial PSR mode of the second display device overlaps with the VBI of the first display device, the adjustment of the memory clock frequency is scheduled to occur.

6. The device of claim 1, wherein the device is further configured to perform memory training when the second display device is in PSR mode and the VBI occurs for the first display device.

7. The device of claim 1, wherein the frequency adjustment unit is further configured to: send a command to the phase-locked loop to adjust the memory clock frequency when the PSR mode of the second display device overlaps with the VBI of the first display device.

8. A method comprising: In response to determining that the conditions for changing the memory clock frequency of the memory subsystem are met, the control unit including the circuit tracks the vertical blanking interval (VBI) timing of the first display device to detect the occurrence of the VBI of the first display device. The second display device, which is different from the first display device, is switched to panel self-refresh (PSR) mode; as well as In response to the detection of the VBI occurrence of the first display device while the second display device is overlaid in the PSR mode, the memory clock frequency is adjusted.

9. The method of claim 8, wherein the adjustment changes the memory clock frequency from a first frequency to a second frequency different from the first frequency.

10. The method of claim 8, wherein the condition for changing the memory clock frequency includes a real-time memory bandwidth requirement that differs from the memory bandwidth available at the memory clock frequency by more than a threshold.

11. The method of claim 8, further comprising, after adjusting the memory clock frequency, causing the second display device to exit PSR mode.

12. The method according to claim 8, further comprising: This causes the second display device to enter a partial PSR mode; as well as When the refresh portion of the partial PSR mode of the second display device overlaps with the VBI of the first display device, the adjustment of the memory clock frequency is scheduled to occur.

13. The method of claim 8, further comprising performing memory training when the second display device is in PSR mode and the VBI occurs for the first display device.

14. The method of claim 8, further comprising, in response to determining that the PSR mode of the second display device overlaps with the VBI of the first display device, sending a command to the phase-locked loop to cause the adjustment of the memory clock frequency.

15. A system comprising: A timing controller configured to drive pixel data to a first display device; and The control unit, including the circuitry, is configured to: in response to determining that a condition for changing the memory clock frequency of the memory subsystem is met. The timing controller is switched to panel self-refresh (PSR) mode; Track the vertical blanking interval (VBI) timing of a second display device that is different from the first display device to detect the occurrence of VBI in the first display device; and In response to the detection of the VBI occurrence of the first display device while the second display device is in the PSR mode, the memory clock frequency is adjusted.

16. The system of claim 15, wherein the adjustment causes the memory clock frequency to change from a first frequency to a second frequency different from the first frequency.

17. The system of claim 15, wherein the condition for changing the memory clock frequency includes a real-time memory bandwidth requirement that differs from the memory bandwidth available at the memory clock frequency by more than a threshold.

18. The system of claim 15, wherein the control unit is further configured to cause the timing controller to exit PSR mode after the adjustment of the memory clock frequency.

19. The system of claim 15, wherein the control unit is further configured to: To put the timing controller into a partial PSR mode; and When the refresh portion of the PSR mode of the timing controller overlaps with the VBI of the second display device, the adjustment of the memory clock frequency is scheduled to occur.

20. The system of claim 15, wherein the control unit is further configured to perform memory training when the timing controller is in PSR mode and the VBI occurs for the second display device.

Citation Information

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