Method for heat treatment of semiconductor layers in semiconductor devices

Abstract

Methods for thermally processing semiconductor devices are disclosed. One method includes obtaining a pattern of processing regions having amorphous silicon; aligning a laser beam with a processing region, the laser beam being in a focused laser spot, the focused laser spot having a spot area equal to or greater than the processing region; and performing laser annealing on the processing region by emitting the laser beam toward the processing region for a processing period.

Description

Background Technology

[0001] This disclosure relates to a semiconductor manufacturing method.

[0002] Planar memory cells have been shrunk to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the memory density for planar memory cells is approaching its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0004] A method for thermally treating a semiconductor device is disclosed. The method includes: obtaining a pattern of a processing region having amorphous silicon; aligning a laser beam with the processing region, the laser beam being in a focused laser spot having a spot area equal to or larger than the processing region; and performing laser annealing on the processing region by continuously emitting the laser beam toward the processing region for a processing period.

[0005] Another method for thermally processing semiconductor devices is provided. The method includes obtaining a pattern of a processing region having amorphous silicon and aligning multiple laser beams with the processing region. Each laser beam is in a focused laser spot having multiple spot regions each smaller than or equal to the processing region. The method further includes performing laser annealing on the processing region by continuously emitting multiple laser beams toward the processing region for a processing period to convert the amorphous silicon into polycrystalline silicon.

[0006] A system for thermally processing a semiconductor device is disclosed. The system includes: a laser source configured to generate one or more laser beams; an optical module configured to provide one or more focused laser spots on a processing region; and a controller coupled to the optical module. The controller is configured to: (i) obtain the dimensions of the processing region, and (ii) at least control the optical module to perform laser annealing on the processing region by applying one or more focused laser spots on the processing region based on the processing region and the spot area of ​​each focused laser spot. Attached Figure Description

[0007] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate aspects of this disclosure and, together with the specification, further serve to explain this disclosure and enable those skilled in the art to make and use it.

[0008] Figure 1A cross-sectional view of a 3D memory device according to some aspects of this disclosure is shown.

[0009] Figure 2A A plan view of an exemplary wafer having multiple memory device chips according to some aspects of this disclosure is shown.

[0010] Figure 2B and Figure 2C Each shows a plan view of an exemplary irradiation field (shot) in a memory device chip according to some aspects of this disclosure.

[0011] Figure 3A and Figure 3B Each of these embodiments illustrates the energy distribution of a laser beam along the transverse direction according to some aspects of this disclosure.

[0012] Figure 4A and Figure 4B Each illustrates the relationship between the focused laser spot and the processing area according to some aspects of this disclosure.

[0013] Figure 4C The dimensions of certain portions of an exemplary 3D memory device according to some aspects of this disclosure are shown.

[0014] Figure 4D The overlap error between the focused laser spot and the processing area according to some aspects of this disclosure is shown.

[0015] Figure 5A The smallest repeating spot formed by multiple focused laser spots is shown according to some aspects of this disclosure.

[0016] Figure 5B , Figure 5C , Figure 6A and Figure 6B Each illustrates the relationship between the focused laser spot and the processing area according to some aspects of this disclosure.

[0017] Figure 7 A schematic diagram of an apparatus for performing laser annealing on a semiconductor device, according to some aspects of this disclosure, is shown.

[0018] Figure 8 A schematic diagram of a controller for controlling laser annealing according to some aspects of this disclosure is shown.

[0019] Figure 9 This is a flowchart of an exemplary method for performing laser annealing on a semiconductor device according to some aspects of this disclosure.

[0020] Aspects of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0021] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other configurations and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other, and in a manner not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications are within the scope of this disclosure.

[0022] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a” or “described” can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0023] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “above something” but also includes “above something” or “on top of something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0024] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and (or more) other elements or features as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0025] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0026] In 3D memory devices, peripheral circuitry and the memory cell array of the memory device are arranged vertically in different planes (levels, layers) (i.e., stacked on top of each other) to reduce the planar chip size of the peripheral circuitry and the overall chip size of the memory device. In 3D memory devices, memory cells are formed by the intersection of NAND memory strings and word lines. The NAND memory strings are formed to extend vertically within a memory stack (e.g., a conductive / dielectric layer pair), and the source ends of the NAND memory strings contact a semiconductor layer, which serves as a portion of the source contacts for applying source voltages to the NAND memory strings. This semiconductor layer is then conductively connected to one or more pads for interconnection purposes.

[0027] The formation of semiconductor layers typically involves thermal processing, which transforms amorphous silicon deposited in the processing region and in contact with the source ends of NAND memory strings into polycrystalline silicon. Thermal processing can also activate implants embedded in the amorphous silicon to enable electrical connections. To avoid affecting the metal structures (e.g., bonding contacts, interconnects, etc.) and to maintain the reliability of these metal structures, localized thermal processing (e.g., laser annealing) is used. However, thermal processing is generally not suitable for processing regions of various sizes, layouts, and locations. Therefore, annealing 3D memory devices with semiconductor layers of different sizes / dimensions using uniform laser energy is challenging.

[0028] To address one or more of the aforementioned problems, this disclosure provides methods and systems for converting amorphous silicon into polycrystalline silicon to form a semiconductor layer in a semiconductor device. The semiconductor layer can have any suitable function and / or location. In some embodiments, the semiconductor layer is electrically connected to pads in the semiconductor device for pad lead-out interconnects for pad lead-out purposes. In this disclosure, the processing region where the amorphous silicon is located can have any suitable size. This conversion is performed using laser annealing. To accommodate processing regions of various sizes / areas, the focused laser spot of the laser beam used to process the processing region can be adjusted such that the energy of one or more laser beams incident on the entire processing region is constant / uniform. The energy level incident on the processing region (e.g., amorphous silicon) is sufficiently high to facilitate annealing and implant activation. For example, based on the size / area of ​​the processing region, the energy distribution and / or number of laser beams incident on the processing region can be adjusted to form a spot / region that can apply uniform energy to the processing region. In an example, if the spot area of ​​a single focused laser spot is larger than or equal to the processing region, the entire processing region can be processed using a single focused laser spot. If the area of ​​the focused laser spot is smaller than or equal to the processing area, multiple focused laser spots can be used to form a minimum repeating spot. A minimum repeating spot with uniform energy can be applied to cover the entire processing area. Therefore, the methods and systems of this disclosure can simplify the fabrication of semiconductor layers, thereby allowing laser annealing to be more scalable. For example, large-scale production of semiconductor devices with semiconductor layers can be easier, and the control of laser annealing can be simplified.

[0029] Figure 1 A side view of a portion of an exemplary 3D memory device 100 according to the present disclosure is shown. The 3D memory device includes a first semiconductor structure 105 and a second semiconductor structure 107 bonded to each other at a bonding interface 109. The 3D memory device 100 may include a core array region and a non-core array region. The first semiconductor structure 105 includes a plurality of NAND memory strings 117, a plurality of interleaved gate conductive layers 139 and dielectric layers 140, a plurality of contact structures 115, a semiconductor layer 111, and a plurality of pad lead-out interconnects 119. The source ends of the NAND memory strings 117 located in the core array region are in contact with the semiconductor layer 111. The contact structures 115 (e.g., through-silicon vias, TSVs) may be located in the non-array region and are insulated from the semiconductor layer 111. The pad lead-out interconnects 119 may be electrically connected to the semiconductor layer 111 for pad lead-out purposes.

[0030] It should be noted that the accompanying drawings of this disclosure include... x axis, y shaft and zThe axis further illustrates the spatial relationships of the components of the semiconductor device. The substrate of the semiconductor device (e.g., 3D memory device 100) includes... x direction and y Two transverse surfaces (e.g., top and bottom surfaces) that extend laterally in the direction (i.e., the lateral or width direction). x The direction is the word line direction of the 3D memory device 100. y The direction is the bit line direction of the 3D memory device 100, and z Direction perpendicular to x - y Plane. In some implementations, z The direction is the NAND orientation, which is the vertical extension of the NAND memory string. As used in this article, when the substrate is... z When positioned in the lowest plane of a semiconductor device in the direction (vertical or thickness direction), z The orientation relative to the substrate of a semiconductor device determines whether one component (e.g., layer or device) of the semiconductor device is "on," "above," or "below" another component (e.g., layer or device). The same concepts used to describe spatial relationships apply throughout this disclosure.

[0031] like Figure 1As shown, the first semiconductor structure 105 and the second semiconductor structure 107 can be bonded to each other face-to-face at the bonding interface 109. The second semiconductor structure 107 may include a substrate and a device layer above and in contact with the substrate. The substrate may include silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor material. In some embodiments, the substrate includes single-crystal silicon. In some embodiments, the device layer includes peripheral circuitry (details not shown in the figures). The peripheral circuitry may include high-voltage (HV) circuitry (e.g., driver circuitry) and low-voltage (LV) circuitry (e.g., page buffer circuitry and logic circuitry). In some embodiments, the peripheral circuitry includes a plurality of transistors in contact with the substrate. The transistors may include any transistor disclosed herein, such as planar transistors and 3D transistors. In some embodiments, the second semiconductor structure 107 further includes an interconnect layer above the device layer to transmit electrical signals to or from peripheral circuitry in the device layer. The interconnect layer may include multiple interconnects, including lateral lines and vias. As used herein, the term "interconnect" may broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Interconnects may couple to transistors in the peripheral circuitry of the device layer. The interconnect layer may also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetallic dielectric (IMD) layers"), in which lateral lines and vias may be formed. That is, the interconnect layer may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in the device layer are coupled to each other via interconnects in the interconnect layer. Interconnects in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in the interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectric, or any combination thereof. In some embodiments, the interconnects in the interconnect layer include W, which, in a conductive metallic material, has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, e.g., voids).

[0032] like Figure 1As shown, the second semiconductor structure 107 may further include a bonding layer at the bonding interface 109 and above and in contact with the interconnect layer. The bonding layer may include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts of the bonding layer include Cu. The remaining area of ​​the bonding layer may be formed with a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layer and the surrounding dielectric may be used for hybrid bonding (also known as “metal / dielectric hybrid bonding”), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer (e.g., solder or bonding agent)) and can simultaneously achieve metal-to-metal (e.g., Cu to Cu) bonding and dielectric-to-dielectric (e.g., SiO2 to SiO2) bonding. For example, bonding interfaces can be distinguished based on the relative position (e.g., displacement) of the bonding contacts.

[0033] like Figure 1 As shown, the first semiconductor structure 105 may further include a bonding layer at a bonding interface 109, for example, on the side of the bonding interface opposite to the bonding layer in the second semiconductor structure 107. The bonding layer of the first semiconductor structure 105 may include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts may include a conductive material, such as Cu. The remaining regions of the bonding layer may be formed with a dielectric material, such as silicon oxide. The bonding contacts in the bonding layer and the surrounding dielectric may be used for mixed bonding. In some embodiments, the bonding interface 109 is the location where the bonding layers of the first semiconductor structure 105 and the second semiconductor structure 107 meet and bond.

[0034] The first semiconductor structure 105 may further include an interconnect layer above and in contact with the bonding layer for signal transmission. The interconnect layer in the first semiconductor structure 105 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer may also include one or more ILD layers, in which lateral lines and vias may be formed. The interconnects in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0035] like Figure 1As shown, the first semiconductor structure 105 may include an array of memory cells, such as an array of NAND memory strings 117, located above and in contact with the interconnect layer. The NAND memory strings 117 (e.g., an array of memory cells) may be formed in a core array region. According to some embodiments, each NAND memory string 117 extends vertically through multiple pairs of gate conductive layers 139 and dielectric layers 140. The stacked and interleaved gate conductive layers 139 and dielectric layers 140 are also referred to herein as a stacked structure, such as a memory stack of conductive layer / dielectric layer pairs. According to some embodiments, the interleaved gate conductive layers 139 and dielectric layers 140 in the memory stack alternate in the vertical direction. Each gate conductive layer 139 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The adhesive layer may include a conductive material (e.g., titanium nitride (TiN)) that can improve adhesion between the gate electrode and the gate dielectric layer. The gate electrode of the gate conductive layer 139 may extend laterally as a word line, terminating at one or more stepped structures of the memory stack. The stepped structure is located in the stepped region, which is part of the non-core array region. The stepped structure can contact multiple word line contacts to apply voltage to the gate conductive layer 139.

[0036] The number of pairs of gate conductive layers 139 and dielectric layers 140 in a memory stack can be one of the factors determining the number of memory cells in a memory cell array. Gate conductive layers 139 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 139 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 139 includes a doped polysilicon layer. Each gate conductive layer 139 may include a control gate surrounding a memory cell. Dielectric layers 140 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, dielectric layers 140 include silicon nitride.

[0037] like Figure 1As shown, each NAND memory string 117 includes a channel structure extending vertically through the memory stack. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a storage film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the storage film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). The channel structure may also include a channel plug on the drain terminal of the NAND memory string 117. The channel plug may include polysilicon and be in contact with the semiconductor channel. In some embodiments, each NAND memory string 117 is a "charge-trapping" type NAND memory. It should be understood that the NAND memory string 117 is not limited to a "charge-trapping" type NAND memory string, and in other examples may be a "floating-gate" type NAND memory string.

[0038] According to some embodiments, the NAND memory string 117 has no semiconductor plugs on its source terminals. Instead, the 3D memory device 100 includes a semiconductor layer 111 above and in contact with the NAND memory string 117. The semiconductor layer 111 may contact the sidewalls of the semiconductor channel of the channel structure at the source terminal of each NAND memory string 117. The semiconductor layer 111 may include a semiconductor material, such as doped polysilicon. In some embodiments, the semiconductor layer 111 is doped with an N-type dopant, such as phosphorus and / or arsenic. The thickness of the semiconductor layer 111 may range from 100 nm to 600 nm. In some embodiments, the semiconductor layer 111 and the source contacts in the slot structure (e.g., an array common source, “ACS”, not shown) may together serve as part of a source line (not shown) coupled to the source terminals of the NAND memory string 117, for example, for applying an erase voltage to the source terminals of the NAND memory string 117 during an erase operation.

[0039] Semiconductor layer 111 may be located wholly or partially within the core array region. The area of ​​semiconductor layer 111 may be large enough, for example, greater than or equal to the total area in which all NAND memory strings 117 are formed, to contact the source ends of all NAND memory strings 117. In various embodiments, semiconductor layer 111 may or may not extend into non-core array regions (e.g., stepped regions). The specific area / size of semiconductor layer 111 should not be limited by embodiments of this disclosure.

[0040] like Figure 1 As shown, the first semiconductor structure 105 may further include one or more contact structures 115 extending vertically within the 3D memory device 100. In some embodiments, the contact structures 115 couple interconnects in the interconnect layer to pads leading out interconnects 119 to facilitate electrical connections within the 3D memory device 100. The contact structures 115 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contact structures 115 include W. In some embodiments, each of the contact structures 115 may have a depth (e.g., along) on ​​the micrometer or tens of micrometer scale (e.g., between 1 µm and 100 µm). z TSV (length in the direction).

[0041] like Figure 1 As shown, the first semiconductor structure 105 may further include an interconnect layer with pads conductively connected to the semiconductor layer 111 above it. In some embodiments, the semiconductor layer 111 is vertical (in... z The pad-lead interconnect layer (oriented) is positioned between the pad-lead interconnect layer and the NAND memory string 117. The pad-lead interconnect layer may include one or more insulating layers above the semiconductor layer 111 and a plurality of pad-lead interconnects 119 conductively connected to the semiconductor layer 111 and / or contact structures 115. In some embodiments, the pad-lead interconnect layer includes a plurality of contacts above and in contact with the semiconductor layer 111 and / or one or more contact layers above and in contact with the contacts, and pad-lead interconnects 119. In some embodiments, the pad-lead interconnects 119 conductively connected to the contact structures 115 are used to drive transistors in peripheral circuitry within the device layer. In some embodiments, the pad-lead interconnects 119 conductively connected to the NAND memory string 117 are used to provide voltages for operations (e.g., erase, write, and read) of memory cells. The contacts, contact layers, and pad-lead interconnects 119 may each comprise tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the contacts, contact layers, and pads leading out interconnects 119 may each comprise tungsten. One or more insulating layers may comprise silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0042] A 3D memory device 100 can be formed by forming a semiconductor layer on top of a semiconductor structure and forming conductive pads connected to the semiconductor layer to lead out interconnects. For example... Figure 1 As shown, a semiconductor structure having a core array region and a non-core array region can be formed first. The semiconductor structure may include a portion of a first semiconductor structure 105 bonded to a second semiconductor structure 107 at a bonding interface 109. The second semiconductor structure may include a substrate, a device layer, corresponding interconnect layers, and corresponding bonding layers. A portion of the first semiconductor structure 105 may include corresponding bonding layers, corresponding interconnect layers, and a memory stack. The memory stack may include a plurality of staggered gate conductive layers 139 and a plurality of dielectric layers 140. The memory stack may also include an array of NAND memory strings 117 extending in the staggered gate conductive layers 139 and dielectric layers 140. A portion of the first semiconductor structure 105 may also include one or more first contact portions extending vertically and coupled to the corresponding interconnect layers. The first contact portions may then form the lower portion of a contact structure 115 (e.g., a TSV). The NAND memory strings 117 may be located in the core array region, and the first contact portions may be located in the non-core array region.

[0043] To form a portion of the first semiconductor structure 105, a stacked structure is formed on a first substrate, for example, a memory stack including staggered gate conductive layers and dielectric layers. To form the memory stack, in some embodiments, a dielectric stack (not shown) including staggered sacrificial layers (not shown) and dielectric layers is formed on a first substrate that may include silicon. In some embodiments, each sacrificial layer includes a silicon nitride layer, and each dielectric layer includes a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The dielectric stack can be repeatedly patterned to form multiple steps in a non-core array region. The memory stack can then be formed by a gate replacement process, for example, replacing the sacrificial layer with a conductive layer by wet / dry etching of a sacrificial layer selectively relative to the dielectric layer and filling the resulting recess with a conductive layer. In some embodiments, each conductive layer includes a metal layer, for example, a W layer. It should be understood that, in some examples, the memory stack can also be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without requiring a gate replacement process. In some embodiments, a pad oxide layer comprising silicon oxide (e.g., thermally grown local oxidation of silicon, LOCOS) is formed between the memory stack and the first substrate. Multiple vertically extending contact vias landing on the steps can be formed to create electrical connections between the gate conductive layer 139 and the corresponding interconnect layers to be formed.

[0044] NAND memory strings 117 can be formed over a first substrate. Each NAND memory string 117 extends vertically through a dielectric stack (or memory stack, depending on the fabrication process) to contact the first substrate. In some embodiments, the fabrication process for forming the NAND memory strings 117 includes forming channel vias through the dielectric stack (or memory stack) and into the first substrate using dry etching and / or wet etching (e.g., deep reactive-ion etching, DRIE) and then filling the channel vias with multiple layers (e.g., storage films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers) using thin film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof).

[0045] In some embodiments, an interconnect layer of a first semiconductor structure 105 is formed over an array of NAND memory strings 117 on a first substrate. The interconnect layer may include multiple interconnects in one or more ILD layers. The interconnects may be electrically connected to the NAND memory strings 117. The interconnects in the interconnect layer may include a conductive material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process forming the interconnects may also include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, the interconnects in the interconnect layer include W, which has a relatively high thermal budget in a conductive metal material to withstand subsequent high-temperature processes.

[0046] In some embodiments, a bonding layer of the first semiconductor structure 105 is formed over the respective interconnect layer. The bonding layer may include a plurality of bonding contacts surrounded by a dielectric in a dielectric layer. The dielectric may be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer are then formed by patterning the dielectric layer (e.g., photolithography of the dielectric material in the dielectric layer and dry / wet etching) and filling contact holes by depositing an adhesive (gluoride) layer, a barrier layer and / or a seed layer and a conductive material (e.g., W). The deposition of the conductive material may include CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.

[0047] To form the second semiconductor structure 107, a device layer is formed on a substrate (e.g., a second substrate). The device layer may include multiple transistors on the substrate. The substrate may be a silicon substrate having monocrystalline silicon. Transistors can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the substrate by ion implantation and / or thermal diffusion, and the doped regions serve, for example, as the well and source / drain regions of the transistors. In some embodiments, isolation regions (e.g., shallow trench isolation (STI)) are also formed in the substrate by wet / dry etching and thin film deposition. The transistors may serve as part or all of the peripheral circuitry for controlling the NAND memory string 117. It should be understood that the details of transistor fabrication may vary depending on the type of transistor and are therefore not described in detail for ease of description.

[0048] In some embodiments, an interconnect layer of the second semiconductor structure 107 is formed over the transistors on the substrate. The formation of the interconnect layer of the second semiconductor structure 107 can be similar to the formation of the interconnect layer of the first semiconductor structure 105, and will not be repeated here. In some embodiments, a first contact portion can be formed in a non-core array region and coupled to an interconnect in a corresponding interconnect layer of the second semiconductor structure 107. The formation of the first contact portion can include photolithography, etching, and deposition. For example, the first contact portion can include a conductive material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.

[0049] In some embodiments, a bonding layer of the second semiconductor structure 107 is formed over the respective interconnect layer. The bonding layer may include a plurality of bonding contacts surrounded by a dielectric in a dielectric layer. The formation of the bonding layer of the second semiconductor structure 107 may be similar to the formation of the bonding layer of the first semiconductor structure 105, and will not be repeated here.

[0050] like Figure 1 As shown, a portion of the first semiconductor structure 105 (e.g., the memory stack and the NAND memory string 117 formed through the memory stack) is flipped upside down. The bonding layer of the downward-facing first semiconductor structure 105 is bonded to the bonding layer of the upward-facing second semiconductor structure 107 (i.e., bonded face-to-face), thereby forming a bonding interface 109. That is, the bonding contacts in the two bonding layers are bonded at the bonding interface 109. In some embodiments, a processing technique, such as plasma treatment, wet processing, and / or localized heat treatment, is applied to the bonding surface prior to bonding. As a result of bonding (e.g., hybrid bonding), the bonding contacts on opposite sides of the bonding interface 109 can be mixed with each other. According to some embodiments, after bonding, the bonding contacts of the first semiconductor structure 105 and the second semiconductor structure 107 are aligned and contacted with each other, such that the memory stack and the NAND memory string 117 formed through the memory stack can be coupled to transistors across the bonding interface 109 via the bonded bonding contacts. The first substrate can then be partially or completely removed to expose the source ends of the NAND memory string 117. In some embodiments, the removal of the first substrate includes suitable etching processes (e.g., dry etching and / or wet etching) and / or planarization processes (e.g., chemical mechanical polishing or CMP). The bonded chip with the first substrate partially or completely removed can be referred to as a semiconductor structure.

[0051] A doped amorphous silicon layer can be deposited on the semiconductor structure on the exposed side / surface of the source ends of the NAND memory string 117. The doped amorphous silicon layer can be in contact with at least the source ends of multiple (e.g., all) NAND memory strings 117 in the core array region. In some embodiments, the doped amorphous silicon layer is deposited using a low-temperature deposition process (e.g., low-temperature chemical vapor deposition (CVD)). For example, the deposition temperature can be in the range of 400°C to 450°C. In-situ doping processes can be used to dope the silicon with dopants (e.g., phosphorus and / or arsenic). In some embodiments, the thickness of the doped amorphous silicon layer is in the range of 100 nm to 600 nm.

[0052] A doped amorphous silicon layer can be converted into a doped polycrystalline silicon layer. The doped amorphous silicon layer can cover any / all of the NAND memory strings 117 in the core array region. The conversion from doped amorphous silicon to doped polycrystalline silicon can include localized heat treatment, such as a laser annealing process. Localized heat treatment can be confined to a desired controlled region and will not affect other heat-sensitive structures, such as bonding contacts at bonding interface 109 and other metal structures / interconnects. The doped amorphous silicon layer can crystallize during laser annealing and form a doped polycrystalline silicon layer. In some embodiments, the temperature of the localized heat treatment can be in the range of 1300 degrees Celsius to 1700 degrees Celsius. In some embodiments, the laser annealing process includes multiple laser pulses in a laser beam, each laser pulse having a pulse duration of 100 ns (i.e., nanoseconds) to 300 ns. The doped polycrystalline silicon layer can refer to semiconductor layer 111, which extends at least in the core array region and contacts the NAND memory strings 117. Although not shown, the doped amorphous silicon layer can also have portions in non-core array regions. The portion(s) may or may not be converted to polycrystalline silicon. The specific layout of the amorphous silicon layer should not be limited to the embodiments of this disclosure.

[0053] One or more dielectric layers may be deposited and patterned on semiconductor layer 111, and one or more contact layers (if any), one or more contacts (if any), and one or more pads may be formed in the dielectric layers to provide interconnects 119 for conductive connection to semiconductor layer 111. The dielectric layers may include silicon oxide, silicon nitride, and / or silicon oxynitride. The dielectric layers may be formed by CVD, PVD, ALD, etc. The contact layers, contacts, and pads providing interconnects 119 may include tungsten and / or polysilicon, and may be formed by methods not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Patterning of the dielectric layers may include any suitable patterning means, such as photolithography and etching (e.g., dry and / or wet etching) processes.

[0054] The 3D memory device 100 may be an example of one of a plurality of 3D memory devices in a wafer, and undergoes laser annealing to form a corresponding semiconductor layer. In some implementations, the 3D memory device 100 can be in a 3D memory device chip. According to the size / area of the semiconductor layer 111, one or more laser beams can be controlled to process the doped amorphous silicon in one core array region. Each laser beam can be incident on the 3D memory device 100 as a focused laser spot. According to implementations of the present disclosure, a processing region (i.e., a region in which annealing is performed using one or more laser beams) can include one or more core array regions. For example, if the focused laser spot of a single laser beam is greater than or equal to the processing region, the single laser beam can be used to anneal the processing region. In another example, if the focused laser spot of a single laser beam is less than or equal to the processing region, more than one laser beam can be used to anneal the processing region. The energy distribution of the laser beams and / or the overlap of more than one laser beam can be adjusted to facilitate uniform laser energy incidence on the processing region. Figures 2A-2C illustrates an exemplary layout of core array regions and non-core array regions in a wafer according to some implementations. Figure 3A and Figure 3B each illustrate the energy distribution of a laser beam along a respective lateral direction according to some implementations. Figures 4A-4D , Figures 5A-5C , Figure 6A and Figure 6B illustrate different annealing scenarios in which the size / area of the processing region varies according to some implementations.

[0055] Figure 2A illustrates a plan view of an exemplary wafer 200 having a plurality of 3D memory device chips according to some aspects of the present disclosure. Figure 2B and Figure 2C each illustrate an example of an illumination field 202 according to some aspects of the present disclosure. The wafer 200 can include a plurality of illumination fields 202, and each illumination field 202 includes four dies, for example, four 3D memory device chips, such as Figure 2B the 3D memory device chip 204 in or Figure 2C the 3D memory device chip 203 in. The four 3D memory device chips can be separated by scribe lines 212 / 213. As shown in Figure 2B and Figure 2C , each 3D memory device chip 204 / 203 can include at least one stack structure. Each die (e.g., a 3D memory device chip) can be in yThe direction includes one or more planes. The stacked structure may include a memory stack with staggered conductive layers (e.g., gate lines / word lines) and dielectric layers (e.g., gate-to-gate dielectrics) rising from a surrounding lower region. Each conductive / dielectric layer pair is at a different height and is referred to as a stage. In some embodiments, the stacked structure includes a stepped structure on one or more sides of the stacked structure. The stepped structure may have a sloping profile that rises from a surrounding lower region outside the stacked structure to an inner region within the stacked structure. Based on the different heights of the structures in the 3D memory device chip 204 / 203, the 3D memory device chip 204 / 203 may be divided into a core array region (unfilled) and a non-core array region (patterned filled).

[0056] like Figure 2B As shown, in some embodiments, the 3D memory device chip 204 may include two stacked structures having two core array regions 206 and non-core array regions 208 between and surrounding the core array regions 206. A stepped region may be located in the non-core array regions 208 between the core array regions 206. The stepped structure of the stacked structure may be located in the stepped region between the core array regions 206. The memory cell array may be formed, for example, in the core array regions 206 as an array of NAND memory strings, wherein each NAND memory string extends vertically through the corresponding stacked structure.

[0057] Alternatively or otherwise, such as Figure 2C As shown, in some embodiments, the 3D memory device chip 203 may include a stacked structure having a core array region 207 and non-core array regions 205 on the sides of the core array region 207. A stepped structure of the stacked structure may be present in stepped regions on one or more sides of the stacked structure. The memory cell array may be formed, for example, in the core array region 207 as an array of NAND memory strings, wherein each NAND memory string extends vertically through the stacked structure.

[0058] Figure 3A The focused laser spot of the laser beam for laser annealing according to this disclosure is shown in... x Energy distribution in a direction. Figure 3B The focused laser spot according to this disclosure is shown in y Energy distribution in a specific direction. Figure 3A and Figure 3B Each shows the focused laser spot at... x direction and y The change of energy in a direction from one end to the other. For example... Figure 3A and Figure 3B As shown, the energy of the focused laser spot can gradually increase from zero to a stable / constant positive value, and then gradually decrease back to zero. For ease of explanation, the region where the energy of the focused laser spot is uniform and constant can be referred to as the central spot region, and the region where the energy of the focused laser spot increases / decreases can be referred to as the peripheral spot region. In some embodiments, the peripheral spot region surrounds the central spot region. Figure 3A As shown, along x The energy of a focused laser spot can increase from zero to a positive value in the outer region, remain positive in the central region, and decrease from a positive value to zero in the outer region. Assuming the focused laser spot is in... x If the size / dimension in the direction is F, then the central spot area is... x It can have a dimension E in the direction, and E is less than or equal to F. For example... Figure 3B As shown, along y The energy of a focused laser spot can increase from zero to a positive value in the outer region, remain positive in the central region, and decrease from a positive value to zero in the outer region. Assume the focused laser spot is in... y If the size / dimension in the direction is H, then the central spot area is... y It can have a dimension G in the direction, and G is less than or equal to H.

[0059] In some implementations, the energy in the peripheral spot region changes linearly with respect to distance (e.g., increases and decreases), such as... Figure 3A and Figure 3B As depicted in [the text]. In various other embodiments, the variation can be non-linear, such as parabolic, exponential, etc., depending on the laser beam configuration. The correlation between energy and the distance and / or size / area of ​​the central spot region can vary in different embodiments to meet manufacturing process requirements. For example, the slope of the energy / distance line of a focused laser spot can be flatter or steeper in the peripheral spot region to reduce or increase the central spot region. In another example, the slopes of the energy / distance lines of multiple focused laser spots can be adjusted individually such that the energy accumulation in the overlapping peripheral spot regions of the focused laser spots can form a minimal repeating spot with sufficiently high energy for annealing. In some embodiments, the energy distribution of the focused laser spot is respectively in [the text]. x direction and y Symmetrical in direction. In some implementations, the shape and size of the focused laser spot can be varied, for example, by using optics to adapt to the shape of the processing area to be annealed by the laser beam. See below for further details. Figures 4A-4D , Figures 5A-5C , Figure 6A and Figure 6B To provide details.

[0060] Figure 4A and Figure 4B This illustrates a case, according to some embodiments of the present disclosure, where the size / area of ​​the focused laser spot is greater than or equal to the size / area of ​​the processing region in the wafer. Figure 4A and Figure 4B In this process, a single focused laser spot is used to anneal one or more core array regions in processing region 402 of the wafer. Processing region 402 can be... x It has a lateral dimension M in the direction, and y It has a lateral dimension N in the direction. Figure 4C The dimensions of certain portions of an exemplary 3D memory device according to some aspects of this disclosure are shown. Figure 4D The overlap error between the focused laser spot and the processing area according to some aspects of this disclosure is shown.

[0061] like Figure 4C As shown, the 3D memory device 403 may include a core array region 407, a non-core array region 405, and scribe lines 413. The core array region 407, non-core array region 405, and scribe lines 413 may respectively represent core array regions 206 / 207, non-core array regions 208 / 205, and scribe lines 212 / 213. The core array region 407 may have... x Dimension A in the direction and in y Dimension B in the direction. Non-core array region 405 in... x The dimension in the direction can be equal to J, which is equal to (J1 + J2), where J1 and J2 are the non-core array region 405 and the core array region 407, respectively. x The dimensions on each side of the direction. The non-core array region 405 in... y The dimension in the direction can be equal to (Q1 + Q2) of Q, where Q1 and Q2 are the non-core array region 405 in the core array region 407, respectively. y The dimensions on each side of the direction. The values ​​of J1, J2, Q1, and Q2 can vary depending on the layout of the 3D memory device 403 (e.g., referring to 3D memory device chips 204 and 203). In some embodiments, the non-core array region 405 is... x direction and y The dimensions in the direction can be respectively related to the stepped area. x direction and y The dimensions are the same in all directions. SLW can represent the width of the scribe line 413 in the direction perpendicular to the extension direction of the scribe line 413. Figure 4C In the example shown, the scribbling line 413 is... y Extending in the direction, and SLW indicates that the scribe line 413 is in xWidth in the direction. The core array region 407 and the non-core array region 405 can each be depicted as having a rectangular shape. In various embodiments, the core array region 407 and the non-core array region 405 can have the same shape or different shapes, and each can have any other suitable shape, such as a circle, an irregular shape, etc.

[0062] Figure 4D The diagram illustrates the potential overlap error between the focused laser spot and the processing area. This overlap error can be represented by misalignment between the actual focused laser spot 422 and the target focused laser spot 423. In some embodiments, the actual focused laser spot 422 refers to the actual pattern formed by the laser beam on the processing area, the target focused laser spot 423 refers to the target pattern intended to be formed by the laser beam, and the overlap error refers to the misalignment between the actual focused laser spot 422 and the target focused laser spot 423. xy Any difference between the actual pattern and the target pattern in the plane. For example, overlap error can be included in... x Lateral overlap error OVL1 in the y-direction, lateral overlap error OVL2 in the y-direction, and / or in different directions x direction and y The diagonal overlap error OVL3 is defined in the lateral direction of the direction. In this disclosure, overlap errors OVL1, OVL2, and OVL3 can represent the overlap error between the actual focused laser spot 422 and the processing area. In this disclosure, the overlap error between the focused laser spot and the processing area can be represented by an OVL that can be determined based on one or more of OVL1, OVL2, and OVL3.

[0063] Return to reference Figure 4A and Figure 4B In some implementations, the processing region 402 may include a single core array region (e.g., 407). The core array region may have... x Dimension A in the direction and in y Dimension B in the direction, such as Figure 4C As shown in the diagram. That is, in this example, M equals A, and N equals B. In some implementations, the processing region includes a single core array region and does not include a stepped region. In some implementations, doped amorphous silicon is also formed in the stepped region, but the doped amorphous silicon is not annealed. The laser irradiation region 404 can represent having... x Dimension C in the direction and in yA single focused laser spot of size D in the direction. That is, C equals F, and D equals H. For ease of illustration, the processing area 402 and the laser irradiation area 404 can each be depicted as having a rectangular (e.g., square) shape. In various embodiments, the processing area 402 and the laser irradiation area 404 can each have any other suitable shape, such as circular, irregular, etc. The laser irradiation area 404 is large enough to completely surround / cover the processing area 402 during laser annealing, for example, in z In the direction (not shown). In some embodiments, C is greater than or equal to M (or A), and D is greater than or equal to N (or B). In some embodiments, E is greater than or equal to A, and G is greater than or equal to B. The energy distribution of the focused laser spot forming the laser irradiation area 404 can be controlled to irradiate the processing area 402 with uniform and constant energy light. For example, the lateral dimension of a single focused laser spot can be adjusted. Optionally or alternatively, the slope of the energy distribution of a single focused laser spot can also be adjusted. In some embodiments, F can be controlled to be greater than or equal to (A+(FE)+OVL) and less than or equal to (A+(FE)+SLW), i.e., (A-E+OVL)≤0≤(A-E+SLW). OVL can represent the overlap error between the focused laser spot and the processing area 402, and SLW can represent the width of the scribe line (e.g., 413). In some implementations, H can be controlled to be greater than or equal to (B+(HG)+OVL) and less than or equal to (B+(HG)+SLW), i.e. (B-G+OVL)≤0≤(B-G+SLW).

[0064] In some embodiments, the processing region 402 may include more than one core array region (e.g., 407). In some embodiments, the processing region includes multiple core array regions and at least one stepped region, the size / area of ​​which may be represented by the size / area of ​​the non-core array regions, see reference. Figure 4C The laser irradiation area 404 can represent a single focused laser spot, where C equals F and D equals H. For ease of illustration, the processing area 402 and the laser irradiation area 404 can each be depicted as having a rectangular (e.g., square) shape. In various embodiments, the processing area 402 and the laser irradiation area 404 can each have any other suitable shape, such as circular, irregular, etc. The laser irradiation area is large enough to completely surround / cover the processing area 402 during laser annealing, for example, in z Direction (not shown). In some embodiments, C is greater than or equal to M, and D is greater than or equal to N. In some embodiments, E is greater than or equal to M, and G is greater than or equal to N.

[0065] The energy distribution of the focused laser spot forming the laser irradiation area 404 can be controlled to irradiate the processing area 402, which may include one or more core areas and optionally one or more stepped areas, with uniform and constant energy. That is, in this example, M is equal to or greater than A, and N is equal to or greater than B. For example, the lateral dimension of a single focused laser spot can be adjusted. Optionally or alternatively, the slope of the energy distribution of a single focused laser spot can also be adjusted. In some embodiments, F can be controlled to be greater than or equal to (mA+jP+(FE)+OVL) and less than or equal to (mA+jP+(FE)+SLW), i.e., (mA+jP-E+OVL)≤0≤(mA+jP-E+SLW). OVL may represent the overlap error between the focused laser spot and the processing area 402, and SLW may represent the width of the scribe line (e.g., 413). In some implementations, H can be controlled to be greater than or equal to (nB+kQ+(HG)+OVL) and less than or equal to (nB+kQ+(HG)+SLW), i.e., (nB+kQ-G+OVL)≤0≤(nB+kQ-G+SLW). P and Q can each represent a stepped region (e.g., a non-core array region) in... x direction and y The dimension in the direction. In some implementations, m and n can represent the dimensions in the processing region, respectively. x direction and y The number of core array regions in the direction, m and n are both equal to or greater than 1. In some implementations, at least one of m and n is greater than or equal to 2. For example, m can be equal to or greater than 2. In some implementations, j and k can respectively represent the number of core array regions in the processing region. x direction and y The number of stepped sections in the direction, where j and k can both be non-negative integers.

[0066] In some embodiments, the processing region 402 includes all core array regions and stepped regions (e.g., non-core array regions) of the wafer's die. In some embodiments, the processing region 402 includes all core array regions and stepped regions (e.g., non-core array regions) in a plane of the wafer. In some embodiments, the processing region 402 includes all planes of the wafer. In some embodiments, the processing region 402 includes all dies in the irradiation field of the wafer. In various embodiments, based on the processing region 402, the values ​​of m, n, j, and k can be adjusted accordingly to ensure that the size / area of ​​the laser irradiation region 404 is large enough to cover the processing region 402 and irradiate the processing region 402 with constant / uniform energy.

[0067] Figures 5A-5CThe present disclosure illustrates a scenario in which the size / area of ​​the focused laser spot is less than or equal to the size / area of ​​the processing region in the wafer, according to some embodiments of the present disclosure. Figure 5A The diagram illustrates a minimal repeating spot formed by the overlap of multiple focused laser spots according to some embodiments of the present disclosure. Pattern 500, i.e., the laser irradiation area, can be formed by the overlap of multiple (e.g., four) focused laser spots over a processing area. For ease of illustration, pattern 500 can be depicted as irradiating multiple (e.g., nine) areas. Figure 5A As shown, a first focused laser spot can illuminate regions 1, 2, 4, and 5; a second focused laser spot can illuminate regions 2, 3, 5, and 6; a third focused laser spot can illuminate regions 4, 5, 7, and 8; and a fourth focused laser spot can illuminate regions 5, 6, 8, and 9. The energy distribution of each of the first, second, third, and fourth focused laser spots can be the same or different. For example, the slope and size of the focused laser spots can be the same or different. In various embodiments, the energy distribution of each focused laser spot can be adjusted individually to obtain a minimum repeating spot of desired size and / or energy. For ease of illustration, in this disclosure, multiple focused laser spots have the same energy distribution.

[0068] Region 5 can be the overlapping area of ​​all four focused laser spots, and therefore can be irradiated by all four focused laser spots. Therefore, region 5 is annealed using the energy of all four focused laser spots. In this disclosure, the overlapping portion of the four focused laser spots in region 5 is referred to as the minimum repeating spot, and is used to anneal the entire processing area. In some embodiments, the energy of the minimum repeating spot is formed by the overlap of the energies of the four focused laser spots in the peripheral spot region. Figure 5A As shown, the minimum repeating spot can have in x The lateral dimension L1 in the direction and in y The lateral dimension L2 in the direction. L1 can be equal to (FE) / 2, and L2 can be equal to (HG) / 2. In some embodiments, L1 is less than or equal to the processing area in the direction. x The lateral dimension in the direction, and L2 is less than or equal to the processing area in y Lateral dimension in the direction. In some implementations, multiple (e.g., four) focused laser spots can be controlled to move within the processing area, such that a uniform and constant energy of a minimum repeating spot is applied to the processing area.

[0069] like Figure 5B and Figure 5CAs shown, multiple focused laser spots are used to anneal one or more core array regions in processing region 502 of the wafer. Processing region 502 can be... x It has a lateral dimension M in the direction and y It has a lateral dimension N in the direction.

[0070] In some implementations, multiple focused laser spots are used to anneal a single core array region in the wafer. The core array region may have [a specific feature / function]. x Dimension A in the direction and in y Dimension B in the direction, such as Figure 4C As shown in the example. In this example, M equals A, and N equals B. In some embodiments, the processing region 502 includes a single core array region and does not include a stepped region. In some embodiments, doped amorphous silicon is also formed in the stepped region, but the doped amorphous silicon is not annealed. The laser irradiation region 504 may represent an area irradiated by multiple focused laser spots and has... x Dimension C in the direction and in y The dimension D in the direction, for example, pattern 500. For ease of illustration, the processing area 502 and the laser irradiation area 504 can each be depicted as having a rectangular (e.g., square) shape. In various embodiments, the processing area 502 and the laser irradiation area 504 can each have any other suitable shape, such as circular, irregular, etc. The laser irradiation area 504 is smaller than the processing area 502. In some embodiments, C is less than or equal to M (or A), and D is less than or equal to N (or B). Multiple focused laser spots forming the laser irradiation area 504 can be controlled to form a minimum repeating spot (e.g., as shown in the image). Figure 5A As shown in the diagram, the laser beam moves within the processing area 502 to apply a minimum repeating spot across the entire processing area 502. In some embodiments, the minimum repeating spot may be located at the central portion of the laser irradiation area 504, and the energy applied within the processing area 502 is uniform and constant. For example, the focused laser spot may be located in the central portion of the laser irradiation area 504, and the energy applied within the processing area 502 is uniform and constant. x direction and yThe laser beam is continuously moved to ensure that the same energy is applied to the processing area 502. The energy distribution of each focused laser spot can also be adjusted individually to form a minimum repeating spot of the desired size. For example, the lateral dimension of a single focused laser spot can be adjusted. Optionally or alternatively, the slope of the energy distribution of a single focused laser spot can also be adjusted. In some embodiments, C can be controlled to be greater than or equal to (mE+OVL) and less than or equal to (mE+SLW), i.e., (mE+OVL)≤C≤(mE+SLW). OVL can represent the overlap error between the focused laser spot and the processing area 502, and SLW can represent the width of the scribe line (e.g., 413). In some embodiments, D can be controlled to be greater than or equal to (nG+OVL) and less than or equal to (nG+SLW), i.e., (nG+OVL)≤D≤(nG+SLW). In some embodiments, m and n can respectively represent the position of the laser beam in the processing area. x direction and y The number of core array regions in the direction, and m and n can both be integers. For example, m and n can both be positive integers.

[0071] In some embodiments, the processing region 502 may include more than one core array region (e.g., 407). In some embodiments, the processing region includes multiple core array regions and at least one stepped region, the size / area of ​​which can be represented by the size / area of ​​non-core array regions, see reference. Figure 4C The description is as follows. In this example, M is greater than or equal to A, and N is greater than or equal to B. In some implementations, C is less than or equal to M, and D is less than or equal to N. Multiple focused laser spots forming the laser irradiation area 504 can be controlled to form a minimum repeating spot (e.g., as shown in the image). Figure 5A As shown in the diagram, the laser beam moves within the processing area 502 to apply a minimum repeating spot across the entire processing area 502. In some embodiments, the minimum repeating spot may be located at the central portion of the laser irradiation area 504, and the energy applied within the processing area 502 is uniform and constant. For example, the focused laser spot may be located in the central portion of the laser irradiation area 504, and the energy applied within the processing area 502 is uniform and constant. x direction and yThe laser beam moves continuously in the direction of motion to ensure that the same energy is applied to the processing area 502. The energy distribution of each focused laser spot can also be adjusted individually to form a minimum repeating spot of the desired size. For example, the lateral dimension of a single focused laser spot can be adjusted. Optionally or alternatively, the slope of the energy distribution of a single focused laser spot can also be adjusted. In some embodiments, C can be controlled to be greater than or equal to (mE+jP+OVL) and less than or equal to (mE+jP+SLW), i.e., (mE+jP+OVL)≤C≤(mE+jP+SLW). OVL can represent the overlap error between the focused laser spot and the processing area 502, and SLW can represent the width of the scribe line (e.g., 413). In some embodiments, D can be controlled to be greater than or equal to (nG+kQ+OVL) and less than or equal to (nG+kQ+SLW), i.e., (nG+kQ+OVL)≤D≤(nG+kQ+SLW). In some implementations, m and n can respectively represent the regions in the processing area. x direction and y The number of core array regions in the direction, and m and n can both be integers. For example, m and n can both be positive integers. P and Q can each represent a step region (e.g., a non-core array region) in the direction. x direction and y The dimension in the direction. In some implementations, m and n can represent the dimensions in the processing region, respectively. x direction and y The number of core array regions in the direction, m and n are both equal to or greater than 1. In some implementations, at least one of m and n is greater than or equal to 2. For example, m can be equal to or greater than 2. In some implementations, j and k can respectively represent the number of core array regions in the processing region. x direction and y The number of stepped sections in the direction, where j and k can both be non-negative integers.

[0072] In some embodiments, the processing region 502 includes all core array regions and stepped regions (e.g., non-core array regions) of the wafer's die. In some embodiments, the processing region 502 includes all core array regions and stepped regions (e.g., non-core array regions) in a plane of the wafer. In some embodiments, the processing region 502 includes all planes of the wafer. In some embodiments, the processing region 502 includes all dies in the irradiation field of the wafer. In various embodiments, based on the processing region 502, the values ​​of m, n, j, and k can be adjusted accordingly to ensure that the size / area of ​​the laser irradiation region 504 is large enough to cover the processing region 502 and irradiate the processing region 502 with constant / uniform energy.

[0073] Figure 6A and Figure 6BThis illustrates a case, according to some embodiments of the present disclosure, where the size / area of ​​the focused laser spot is greater than or equal to the size / area of ​​the wafer. Figure 6A and Figure 6B In this process, a single laser spot is used to anneal multiple core array regions and stepped regions within the processing area (e.g., wafer 602). Wafer 602 can... x It has a lateral dimension W in the direction and y It has a lateral dimension V in the direction.

[0074] In some embodiments, the laser irradiation area 604 may represent an area irradiated by a single focused laser spot, and has the following characteristics: x Dimension C in the direction and in y The dimension D in the direction. For ease of illustration, wafer 602 and laser irradiation area 604 can be depicted as having circular and rectangular (e.g., square) shapes, respectively. In various embodiments, wafer 602 and laser irradiation area 604 can each have any other suitable shape, such as an irregular shape. Laser irradiation area 604 can be larger than or equal to processing area 602. For a single focused laser spot, C equals F, and D equals H. In some embodiments, F is greater than or equal to W, and H is greater than or equal to V. In some embodiments, E is greater than or equal to W, and G is greater than or equal to V. The energy distribution of the focused laser spot can also be adjusted to apply uniform and constant energy to wafer 602. For example, the lateral dimension of a single focused laser spot can be adjusted. Optionally or alternatively, the slope of the energy distribution of a single focused laser spot can also be adjusted. In some embodiments, F can be controlled to be greater than or equal to (W+OVL), i.e., F≥(W+OVL). OVL can represent the overlap error between the focused laser spot and processing area 502. In some implementations, H can be controlled to be greater than or equal to (V+OVL), i.e., H≥(V+OVL).

[0075] Figure 7 A schematic diagram of an exemplary system 700 for laser annealing in a 3D memory device using a focused laser spot, according to some embodiments of the present disclosure, is shown. System 700 may include a laser source 702, an optical module 704, a support 706, and a controller 708. Laser source 702 may be any suitable type of laser source, including but not limited to fiber lasers, solid-state lasers, gas lasers, and semiconductor lasers. Laser source 702 may be configured to generate one or more laser beams at any suitable wavelength, such as 532nm lasers, 600-1000nm lasers, 1064nm lasers, 1550nm lasers, etc. The laser beams generated by laser source 702 can form a focused laser spot on a processing area for the laser annealing process. The focused laser spot may have, for example, […]. Figure 3Aand Figure 3B The energy distribution shown is illustrated.

[0076] Optical module 704 can be optically coupled to laser source 702 and includes scanning unit 712 and focusing unit 714. Optical module 704 can be configured to provide one or more focused laser spots on processing area 701 based on one or more laser beams generated by laser source 702. In some embodiments, optical module 704 is operatively coupled to controller 708 and receives control signals and instructions from controller 708. Scanning unit 712 can be configured to change the orientation of at least some laser beams emitted onto processing area 701 on support 706 based on control by controller 708. For example, controlled by controller 708, optical module 704 can direct one or more focused laser spots on processing area 701 in various directions (e.g., ...). x direction and y The scanning unit 712 moves in the direction of the laser beam, allowing uniform and constant energy to cover the processing area 701. In other words, the scanning unit 712 can scan the laser beam toward the processing area 701 within a scanning angle at a scanning rate controlled by the controller 708. In some embodiments, the scanning unit 712 includes a galvanometer and / or a polarizer. The scanning unit 712 may also include any other suitable scanning mirrors and scanning refractive optics.

[0077] Focusing unit 714 can be configured to focus each laser beam in the laser beam to form a corresponding focused laser spot. In some embodiments, the size of each focused laser spot (e.g., the values ​​of F and H) can be between 1 micrometer (µm) and 500µm, for example, 1µm, 2µm, 3µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm, 10µm, 20µm, 30µm, 40µm, 50µm, 60µm, 70µm, 80µm, 90µm, 100µm, 200µm, 300µm, 400µm, 500µm, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values. The shape of each focused laser spot can include, for example, a circle, a rectangle, a square, an irregular shape, or any suitable shape. It should be understood that the sizes of a series of focused laser spots can be substantially the same or different. By focusing the laser beam into a focused laser spot, the energy density can be significantly increased.

[0078] The support 706 can be configured to support the processing region 701. In some embodiments, the support 706 includes a wafer support for semiconductor manufacturing. In some embodiments, the support 706 is also configured to change the position and / or orientation of the processing region 701 during annealing based on the control of the controller 708.

[0079] Controller 708 is operably coupled to laser source 702, optical module 704, and / or support 706, and controls the operation of laser source 702, optical module 704, and / or support 706 via control signals and commands. In some embodiments, controller 708 is configured to control optical module 704 and / or support 706 to move a focused laser spot across processing area 701 to form a scanning pattern. Any relative movement between support 706 and optical module 704 supporting processing area 701 when optical module 704 scans a focused pulsed laser toward processing area 701 can cause movement of the focused laser spot across processing area 701, thereby forming a scanning pattern based on the relative movement. By controlling the relative movement (e.g., direction and speed) between support 706 and optical module 704, controller 708 can control the scanning pattern on processing area, such as the size and / or shape of the scanning pattern. For example, controller 708 can control optical module 704 to focus and overlap multiple laser beams on processing area 701, forming a minimally repeating spot on processing area 701. Furthermore, controller 708 can control the scanning pattern by adjusting the parameters of the laser beams generated by laser source 702 via operation of laser source 702. In some embodiments, the scanning pattern is manually determined by an operator (e.g., a technician) based on the design of the 3D memory device. In some embodiments, the scanning pattern is automatically or semi-automatically determined by controller 708 based on processing area 701.

[0080] In some embodiments, system 700 further includes a calibration unit (not shown) configured to calibrate the position of the focused laser spot on processing area 701. Controller 708 may be configured to control optical module 704 and / or support 706 based on calibration performed by the calibration unit to move the focused laser spot on processing area 701.

[0081] Figure 8 A schematic diagram of an exemplary controller 708 according to some embodiments of the present disclosure is shown. The controller 708 can control the operation of the laser source 702, the optical module 704, and / or the support 706 to, for example, generate, adjust, and move a focused laser spot on a processing area 701 to form a scanning pattern on the processing area 701. In some embodiments, the controller 708 receives data instructing the processing area 701 and provides control commands instructing the laser source 702, the optical module 704, and / or the support 706 to instruct the scanning pattern.

[0082] like Figure 8As shown, controller 708 may include communication interface 802, processor 804, memory 806, and storage 808. In some embodiments, controller 708 may have different modules in a single device (e.g., integrated circuit (IC) chips implemented as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs)) or separate devices with specialized functions. One or more components of controller 708 may be located as part of system 700 along with laser source 702 and / or optical module 704, or alternatively located in a standalone computing device, in the cloud, or at another remote location. Components of controller 708 may be in an integrated device or distributed in different locations but communicating with each other via a network (not shown). For example, processor 804 may be an on-board processor of laser source 702 and / or optical module 704, a processor within a standalone computing device, a cloud processor, or any combination thereof.

[0083] Communication interface 802 can be accessed via communication cable, Wireless Local Area Network (WLAN), Wide Area Network (WAN), wireless network (e.g., radio waves), nationwide cellular network and / or local wireless network (e.g., Bluetooth). TM The communication interface 802 can transmit or receive data from components (e.g., laser source 702, optical module 704, or bracket 706) via WiFi or other communication methods. In some embodiments, the communication interface 802 may be an Integrated Services Digital Network (ISDN) card, a cable modem, a satellite modem, or a modem that provides a data communication connection. As another example, the communication interface 802 may be a local area network (LAN) card to provide a data communication connection to a compatible LAN. A wireless link may also be implemented via the communication interface 802. In such embodiments, the communication interface 802 may transmit and receive electrical, electromagnetic, or optical signals carrying digital data streams representing various types of information via a network.

[0084] Processor 804 may include any suitable type of general-purpose or special-purpose microprocessor, digital signal processor, or microcontroller. Processor 804 may be configured as a separate processor module dedicated to controlling laser source 702, optical module 704, and bracket 706. Alternatively, processor 804 may be configured as a shared processor module for performing other functions unrelated to controlling laser source 702, optical module 704, and bracket 706.

[0085] like Figure 8 As shown, processor 804 may include multiple modules, such as a scan pattern determination unit 810, a laser source control unit 812, an optical module control unit 814, and a stage control unit 816. These modules (and any corresponding sub-modules or sub-units) may be hardware units (e.g., integrated circuit portions) of processor 804 designed to be used with other components or to execute programs. The program may be stored on a computer-readable medium, and when executed by processor 804, the program may perform one or more functions. Although Figure 8 The diagram shows that units 810-816 are all within a single processor 804, but it is conceivable that these units could be distributed across multiple processors that are close to or far from each other.

[0086] The scan pattern determination unit 810 can be configured to determine a scan pattern formed by a focused laser spot based on the area / size of the processing region 701. In some embodiments, the scan pattern determination unit 810 receives data indicating the size / area of ​​the processing region 701 and determines whether a single focused laser spot or a minimum repeating spot formed by multiple focused laser spots can be used. As described above, if the size / area of ​​the processing region 701 is less than or equal to the size / area of ​​a single focused laser spot, a single focused laser spot can be used to anneal the processing region 701. Otherwise, multiple focused laser spots can be used to form a minimum repeating spot for annealing the processing region 701. In some embodiments, the data indicating the area / size of the processing region 701 is stored in memory 806 and / or storage 808. In some embodiments, the data indicating the area / size of the processing region 701 can be updated to be adapted for different designs and manufactures of the 3D memory device. In some embodiments, the scan pattern determination unit 810 can determine the size and / or shape of the focused laser spot that can form a scan pattern with a desired size and / or shape.

[0087] Figure 9 This is a flowchart of an exemplary method 900 for annealing a processing region in an operating system 700 according to some aspects of this disclosure. It will be described together. Figures 4A-4D , Figures 5A-5C , Figure 6A , Figure 6B , Figure 8 and Figure 9 It should be understood that the operations shown in method 900 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 9 The different execution orders shown.

[0088] refer to Figure 9 Method 900 begins with operation 902, in which a pattern of processing regions with amorphous silicon is obtained.

[0089] Return to reference Figure 7 and Figure 8 The controller 708 (e.g., the scan pattern determination unit 810) can determine the pattern of the processing area, which may be a portion or the entire wafer positioned on the support 706. In some embodiments, data indicating the pattern of the processing area 701 (e.g., shape, area, and size) is stored in a memory 806 and / or storage 808 that can be accessed by the controller 708.

[0090] refer to Figure 9 Method 900 proceeds to operation 904, in which one or more laser beams are aligned with the processing area.

[0091] Return to reference Figures 4A-4D , Figures 5A-5C , Figure 6A , Figure 6B , Figure 7 and Figure 8 The controller 708 (e.g., the optical module control unit 814) can determine the number of laser beams to be emitted for laser annealing. If the area / size of the processing region 701 is less than or equal to the spot area of ​​the focused laser spot (which is also stored as data in the memory 806 and / or storage device 808), one laser beam can be emitted. If the area / size of the processing region 701 is greater than or equal to the spot area of ​​the focused laser spot, more than one laser beam can be emitted.

[0092] A controller 708 (e.g., a laser source control unit 812) can control a laser source 702 to emit a specific number of laser beams accordingly. A controller 708 (e.g., an optical module control unit 814) can control an optical module 704 to align (one or more) laser beams with and focus (one or more) laser beams onto the processing area 701. The controller 708 (e.g., the optical module control unit 814) can also control the optical module 704 to adjust the energy distribution and pattern, for example, the shape, size, and / or area of ​​(one or more) focused laser spots formed on the processing area 701. In some embodiments, the controller 708 (e.g., the optical module control unit 814) can also control the optical module 704 to align and overlap multiple focused laser spots on the processing area 701 to form a minimally repeating spot. The controller 708 (e.g., the optical module control unit 814) can also control the optical module 704 to move the laser beams / focused laser spots on the processing area 701 so that the annealing processing area 701 can be uniformly annealed. For a detailed description of annealing the processing area 701 using one or more focused laser spots, please refer to [reference needed]. Figures 4A-4D , Figures 5A-5C , Figure 6A and Figure 6B And will not be repeated here.

[0093] refer to Figure 9 Method 900 proceeds to operation 906, in which a laser annealing continuous processing period is performed on the processing area to convert amorphous silicon into polycrystalline silicon.

[0094] Return to reference Figures 4A-4D , Figures 5A-5C , Figure 6A , Figure 6B , Figure 7 and Figure 8 The controller 708 (e.g., laser source control unit 812) can control the laser source 702 to irradiate (one or more) laser beams for a continuous processing period (e.g., at each focused laser spot), enabling annealing of the area irradiated by the focused laser spot. A detailed description of annealing the processing area 701 using (one or more) focused laser spots can be found in [reference needed]. Figures 4A-4D , Figures 5A-5C , Figure 6A and Figure 6B And will not be repeated here.

[0095] In this disclosure, a method for thermally processing a semiconductor device is disclosed. The method includes: obtaining a pattern of a processing region having amorphous silicon; aligning a laser beam with the processing region, the laser beam being in a focused laser spot having a spot area equal to or larger than the processing region; and performing laser annealing on the processing region by continuously emitting the laser beam toward the processing region for a processing period.

[0096] In some implementations, laser annealing converts amorphous silicon into polycrystalline silicon.

[0097] In some implementations, the light spot area completely surrounds the processing area.

[0098] In some implementations, the spot region includes a central spot region and a peripheral spot region surrounding the central spot region; and the energy level of the laser beam is constant in the central spot region and decreases in the peripheral spot region.

[0099] In some implementations, the central spot area completely surrounds the processing area.

[0100] In some embodiments, the processing region covers a core array region in the semiconductor device, the core array region having a dimension A in a first lateral direction and a dimension B in a second lateral direction perpendicular to the first lateral direction, and the central spot region of the spot region having a dimension E in the first lateral direction and a dimension G in the second lateral direction. In some embodiments, (A-E+OVL)≤0 and (A-E+SLW)≥0, where OVL is the overlap error between the focused laser spot and the processing region, and SLW is the width of the scribe line, and (B-G+OVL)≤0 and (B-G+SLW)≥0.

[0101] In some embodiments, the processing region covers a core array region and a non-core array region in the semiconductor device. The core array region has a dimension A in a first lateral direction and a dimension B in a second lateral direction. P is the dimension of the non-core array region in the first lateral direction, and Q is the dimension of the non-core array region in the second lateral direction. The central spot region of the spot region has a dimension E in the first lateral direction and a dimension G in the second lateral direction. In some embodiments, (mA+jP-E+OVL)≤0 and (mA+jP-E+SLW)≥0, where m is a positive integer, OVL is the overlap error between the focused laser spot and the processing region, and SLW is the width of the scribe line. Furthermore, (nB+kQ-G+OVL)≤0 and (nB+kQ-G+SLW)≥0, where n is a positive integer, and j and k are both non-negative integers.

[0102] In some implementations, m is greater than or equal to 2.

[0103] In some implementations, the processing area covers all core array regions and non-core array regions of the semiconductor device die.

[0104] In some implementations, the processing area covers all planes of the die of the semiconductor device.

[0105] In some implementations, the processing area covers all the dies in the irradiation field of the semiconductor device.

[0106] In some embodiments, the processing region covers a wafer having a dimension W in a first lateral direction and a dimension V in a second lateral direction, and the spot region has a dimension F in the first lateral direction and a dimension H in the second lateral direction perpendicular to the first lateral direction. In some embodiments, F ≥ (W + OVL), where OVL is the overlap error between the focused laser spot and the processing region, and H ≥ (V + OVL).

[0107] In some implementations, the processing area is electrically connected to the pads of the semiconductor device to establish interconnections.

[0108] In another aspect of this disclosure, a method for thermally processing a semiconductor device is provided. The method includes obtaining a pattern of a processing region having amorphous silicon and aligning a plurality of laser beams with the processing region. Each laser beam is in a focused laser spot having a plurality of spot regions each smaller than or equal to the processing region. The method further includes performing laser annealing on the processing region by continuously emitting the plurality of laser beams toward the processing region for a processing period to convert the amorphous silicon into polycrystalline silicon.

[0109] In some embodiments, the spot region includes a central spot region and a peripheral spot region surrounding the central spot region, the spot region having a dimension F in a first lateral direction and a dimension H in a second lateral direction. In some embodiments, the energy level of the laser beam is constant in the central spot region and decreases in the peripheral spot region; and the central spot region has a dimension E in the first lateral direction and a dimension G in the second lateral direction, E being less than F and G being less than H.

[0110] In some embodiments, the method further includes: overlapping multiple spot regions to form a minimum repeating spot; and applying the minimum repeating spot multiple times to cover the processing area.

[0111] In some implementations, the minimum repeating spot induces a laser annealing process in the processing area during the processing period.

[0112] In some implementations, the number of multiple spot regions is four; the lateral dimension of the minimum repeating spot in the first lateral direction is equal to (FE) / 2; and the lateral dimension of the minimum repeating spot in the second lateral direction is equal to (HG) / 2.

[0113] In some embodiments, the processing region covers the core array region in the semiconductor device. The processing region has a dimension C in a first lateral direction and a dimension D in a second lateral direction, and the core array region has a dimension A in the first lateral direction and a dimension B in the second lateral direction. In some embodiments, (mE+OVL)≤C≤(mE+SLW), where OVL is the overlap error between the focused laser spot and the processing region, and SLW is the width of the scribe line. In some embodiments, (nG+OVL)≤D≤(nG+SLW), where m and n are both integers.

[0114] In some embodiments, the processing region covers both the core array region and the non-core array region in the semiconductor device. The processing region has a dimension C in a first lateral direction and a dimension D in a second lateral direction. The core array region has a dimension A in the first lateral direction and a dimension B in the second lateral direction. P is the dimension of the non-core array region in the first lateral direction, and Q is the dimension of the non-core array region in the second lateral direction. In some embodiments, (mE+jP+OVL)≤C≤(mE+jP+SLW), where m is a positive integer, OVL is the overlap error between the focused laser spot and the processing region, and SLW is the width of the scribe line. In some embodiments, (nG+kQ+OVL)≤D≤(nG+kQ+SLW), where n is a positive integer, and j and k are both non-negative integers.

[0115] In some implementations, the processing area covers all core array regions and non-core array regions of the semiconductor device die.

[0116] In some implementations, the processing area covers all planes of the die of the semiconductor device.

[0117] In some implementations, the processing area covers all the dies in the irradiation field of the semiconductor device.

[0118] In some implementations, the processing area is electrically connected to the pads of the semiconductor device to establish interconnections.

[0119] Another aspect of this disclosure provides a system for thermally processing a semiconductor device. The system includes: a laser source configured to generate one or more laser beams; an optical module configured to provide one or more focused laser spots on a processing region; and a controller coupled to the optical module. The controller is configured to: (i) obtain the dimensions of the processing region, and (ii) at least control the optical module to perform laser annealing on the processing region by applying one or more focused laser spots on the processing region based on the processing region and the spot area of ​​each focused laser spot.

[0120] In some implementations, in response to a spot area being equal to or larger than the processing area, the controller is configured to align the laser beam with the processing area and emit the laser beam toward the processing area for a continuous processing period.

[0121] In some implementations, the laser beam induces a laser annealing process on the processing area during the processing period.

[0122] In some implementations, the light spot area completely surrounds the processing area.

[0123] In some embodiments, the spot region includes a central spot region and a peripheral spot region surrounding the central spot region, the spot region having a dimension F in a first lateral direction and a dimension H in a second lateral direction perpendicular to the first lateral direction. The central spot region has a dimension E in the first lateral direction and a dimension G in the second lateral direction. In some embodiments, the energy level of the laser beam is constant in the central spot region and decreases in the peripheral spot region.

[0124] In some implementations, the central spot area completely surrounds the processing area.

[0125] In some embodiments, the processing region covers a core array region in the semiconductor device, the core array region having a dimension A in a first lateral direction and a dimension B in a second lateral direction. In some embodiments, (A-E+OVL)≤0≤(A-E+SLW), where OVL is the overlap error between the focused laser spot and the processing region, and SLW is the width of the scribe line. In some embodiments, (B-G+OVL)≤0≤(B-G+SLW).

[0126] In some embodiments, the processing region covers a core array region and a non-core array region in the semiconductor device. The core array region has a dimension A in a first lateral direction and a dimension B in a second lateral direction, P is the dimension of the non-core array region in the first lateral direction, and Q is the dimension of the non-core array region in the second lateral direction. In some embodiments, (mA+jP-E+OVL)≤0≤(mA+jP-E+SLW), where m is a positive integer, OVL is the overlap error between the focused laser spot and the processing region, and SLW is the width of the scribe line. In some embodiments, (nB+kQ-G+OVL)≤0≤(nB+kQ-G+SLW), where n is a positive integer, and j and k are both non-negative integers.

[0127] In some implementations, m is greater than or equal to 2.

[0128] In some implementations, the processing area covers all core array regions and non-core array regions of the semiconductor device die.

[0129] In some implementations, the processing area covers all planes of the die of the semiconductor device.

[0130] In some implementations, the processing area covers all the dies in the irradiation field of the semiconductor device.

[0131] In some embodiments, the processing region covers a wafer having a dimension W in a first lateral direction and a dimension V in a second lateral direction. In some embodiments, F ≥ (W + OVL), where OVL is the overlap error between the focused laser spot and the processing region, and H ≥ (V + OVL).

[0132] In some implementations, the laser annealing process transforms the amorphous silicon layer in the processing region into a polycrystalline silicon layer and activates the implants in the processing region.

[0133] In some implementations, in response to a spot area being equal to or smaller than the processing area, the controller is configured to align multiple laser beams with the processing area and emit multiple laser beams toward the processing area for a continuous processing period. Each laser beam is in a focused laser spot, which has multiple spot areas that are each smaller than or equal to the processing area.

[0134] In some embodiments, the spot region includes a central spot region and a peripheral spot region surrounding the central spot region, the spot region having a dimension F in a first lateral direction and a dimension H in a second lateral direction perpendicular to the first lateral direction. In some embodiments, the energy level of the laser beam is constant in the central spot region and decreases in the peripheral spot region; and the central spot region has a dimension E in the first lateral direction and a dimension G in the second lateral direction, E being less than F and G being less than H.

[0135] In some implementations, the system further includes: overlapping multiple spot regions to form a minimum repeating spot; and applying the minimum repeating spot multiple times to cover the processing area.

[0136] In some implementations, the minimum repeating spot induces a laser annealing process in the processing area during the processing period.

[0137] In some implementations, the number of multiple spot regions is four; the lateral dimension of the minimum repeating spot in the first lateral direction is equal to (FE) / 2; and the lateral dimension of the minimum repeating spot in the second lateral direction is equal to (HG) / 2.

[0138] In some embodiments, the processing region covers the core array region in the semiconductor device. The processing region has a dimension C in a first lateral direction and a dimension D in a second lateral direction, and the core array region has a dimension A in the first lateral direction and a dimension B in the second lateral direction. In some embodiments, (mE+OVL)≤C≤(mE+SLW), where OVL is the overlap error between the focused laser spot and the processing region, and SLW is the width of the scribe line. In some embodiments, (nG+OVL)≤D≤(nG+SLW), where m and n are both integers.

[0139] In some embodiments, the processing region covers both the core array region and the non-core array region in the semiconductor device. The processing region has a dimension C in a first lateral direction and a dimension D in a second lateral direction. The core array region has a dimension A in the first lateral direction and a dimension B in the second lateral direction. P is the dimension of the non-core array region in the first lateral direction, and Q is the dimension of the non-core array region in the second lateral direction. In some embodiments, (mE+jP+OVL)≤F≤(mE+jP+SLW), where m is a positive integer, OVL is the overlap error between the focused laser spot and the processing region, and SLW is the width of the scribe line. In some embodiments, (nG+kQ+OVL)≤H≤(nG+kQ+SLW), where n is a positive integer, and j and k are both non-negative integers.

[0140] In some implementations, the processing area covers all core array regions and non-core array regions of the semiconductor device die.

[0141] In some implementations, the processing area covers all planes of the die of the semiconductor device.

[0142] In some implementations, the processing area covers all the dies in the irradiation field of the semiconductor device.

[0143] In some implementations, the processing area is electrically connected to the pads of the semiconductor device to establish interconnections.

[0144] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalent variations of the disclosed embodiments.

[0145] The breadth and scope of this disclosure should not be limited to any of the exemplary embodiments described above, but should be defined only by the appended claims and their equivalents.

Claims

1. A method for heat-treating a semiconductor device, comprising: Obtain a pattern that includes the processed regions of amorphous silicon; Align the laser beam with the processing area, wherein the laser beam is in a focused laser spot, and the focused laser spot has a spot area equal to or larger than the processing area; as well as Laser annealing is performed on the processing area by continuously emitting the laser beam toward the processing area for a specified processing period. The light spot region includes a central light spot region and a peripheral light spot region surrounding the central light spot region; and The size of the light spot region is related to the size of the processing region, the size of the peripheral light spot region, and the overlap error between the focused laser spot and the processing region.

2. The method according to claim 1, wherein, The laser annealing transforms the amorphous silicon into polycrystalline silicon.

3. The method according to claim 1 or 2, wherein, The light spot area completely surrounds the processing area.

4. The method according to any one of claims 1-2, wherein: The energy level of the laser beam is constant in the central spot region and decreases in the peripheral spot region.

5. The method according to claim 4, wherein, The central light spot area completely surrounds the processing area.

6. The method according to claim 5, wherein, The processing region covers the core array region in the semiconductor device, the core array region having a dimension A in a first lateral direction and a dimension B in a second lateral direction perpendicular to the first lateral direction, the central spot region of the spot region having a dimension E in the first lateral direction and a dimension G in the second lateral direction, and wherein (A-E+OVL)≤0 and (A-E+SLW)≥0, where OVL is the overlap error between the focused laser spot and the processing area, and SLW is the width of the scribe line. (B-G+OVL)≤0 and (B-G+SLW)≥0.

7. The method according to claim 5, wherein, The processing region covers the core array region and non-core array region in the semiconductor device. The core array region has a dimension A in a first lateral direction and a dimension B in a second lateral direction. P is the dimension of the non-core array region in the first lateral direction, and Q is the dimension of the non-core array region in the second lateral direction. The central spot region of the spot region has a dimension E in the first lateral direction and a dimension G in the second lateral direction, and wherein... (mA+jP-E+OVL)≤0 and (mA+jP-E+SLW)≥0, where m is a positive integer, OVL is the overlap error between the focused laser spot and the processing area, and SLW is the width of the scribe line. (nB+kQ-G+OVL)≤0 and (nB+kQ-G+SLW)≥0, where n is a positive integer and j and k are both non-negative integers.

8. The method according to claim 7, wherein, m is greater than or equal to 2.

9. The method according to claim 7, wherein, The processing area covers all core array regions and non-core array regions in the die of the semiconductor device.

10. The method according to claim 7, wherein, The processing area covers all planes in the die of the semiconductor device.

11. The method according to claim 7, wherein, The processing area covers all the dies in the irradiation field of the semiconductor device.

12. The method according to claim 5, wherein, The processing area covers a wafer having a dimension W in a first lateral direction and a dimension V in a second lateral direction. The spot area has a dimension F in the first lateral direction and a dimension H in the second lateral direction perpendicular to the first lateral direction, and wherein: F≥(W+OVL), where OVL is the overlap error between the focused laser spot and the processing area, and H≥(V+OVL).

13. The method according to any one of claims 1-2, wherein, The processing area is electrically connected to the pads of the semiconductor device via interconnects.

14. A method for heat-treating a semiconductor device, comprising: Obtain a pattern that includes the processed regions of amorphous silicon; Multiple laser beams are aligned with the processing area, each laser beam being in a focused laser spot, and each focused laser spot having multiple spot areas smaller than or equal to the processing area. as well as Laser annealing is performed on the processing area by continuously emitting the plurality of laser beams toward the processing area for a processing period, thereby converting the amorphous silicon into polycrystalline silicon. The light spot region includes a central light spot region and a peripheral light spot region surrounding the central light spot region; and The size of the light spot region is related to the size of the processing region, the size of the peripheral light spot region, and the overlap error between the focused laser spot and the processing region.

15. The method of claim 14, wherein: The light spot region has a dimension F in a first lateral direction and a dimension H in a second lateral direction, wherein: The energy level of the laser beam is constant in the central spot region and decreases in the peripheral spot region; and The central light spot region has a size E in the first lateral direction and a size G in the second lateral direction, where E is less than F and G is less than H.

16. The method of claim 15, further comprising: The multiple light spot regions are overlapped to form a minimum repeating light spot; as well as The minimum repeating spot is applied multiple times to cover the processing area.

17. The method according to claim 16, wherein, The minimum repeating spot induces a laser annealing process in the processing area during the processing period.

18. The method according to claim 16 or 17, wherein: The number of the multiple light spot regions is four; The lateral dimension of the minimum repeating spot in the first lateral direction is equal to (FE) / 2; and The lateral dimension of the minimum repeating spot in the second lateral direction is equal to (HG) / 2.

19. The method according to any one of claims 16-17, wherein, The processing region covers the core array region in the semiconductor device, the processing region having a dimension C in the first lateral direction and a dimension D in the second lateral direction, the core array region having a dimension A in the first lateral direction and a dimension B in the second lateral direction, and wherein... (mE+OVL)≤C≤(mE+SLW), where OVL is the overlap error between the focused laser spot and the processing area, and SLW is the width of the scribe line. (nG+OVL)≤D≤(nG+SLW), where m and n are both integers.

20. The method according to any one of claims 16-17, wherein, The processing region covers the core array region and non-core array region in the semiconductor device. The processing region has a dimension C in the first lateral direction and a dimension D in the second lateral direction. The core array region has a dimension A in the first lateral direction and a dimension B in the second lateral direction. P is the dimension of the non-core array region in the first lateral direction, and Q is the dimension of the non-core array region in the second lateral direction. (mE+jP+OVL)≤C≤(mE+jP+SLW), where m is a positive integer, OVL is the overlap error between the focused laser spot and the processing area, and SLW is the width of the scribe line. (nG+kQ+OVL)≤D≤(nG+kQ+SLW), where n is a positive integer and j and k are both non-negative integers.

21. The method according to claim 20, wherein, The processing area covers all core array regions and non-core array regions in the die of the semiconductor device.

22. The method according to claim 20, wherein, The processing area covers all planes in the die of the semiconductor device.

23. The method of claim 20, wherein, The processing area covers all the dies in the irradiation field of the semiconductor device.

24. The method according to any one of claims 14-17, wherein, The processing area is electrically connected to the pads of the semiconductor device via interconnects.

25. A system for heat-treating a semiconductor device, comprising: A laser source configured to generate one or more laser beams; An optical module configured to provide one or more focused laser spots over a processing area; as well as A controller, coupled to the optical module and configured to: (i) obtain the dimensions of the processing region, and (ii) at least control the optical module to perform laser annealing on the processing region by applying one or more focused laser spots to the processing region based on the processing region and the spot area of ​​each of the focused laser spots. The light spot region includes a central light spot region and a peripheral light spot region surrounding the central light spot region; and The size of the light spot region is related to the size of the processing region, the size of the peripheral light spot region, and the overlap error between the focused laser spot and the processing region.

26. The system of claim 25, wherein in response to the spot area being equal to or greater than the processing area, the controller is configured to: Align the laser beam with the processing area, and The laser beam is emitted toward the processing area for a continuous processing period.

27. The system according to claim 26, wherein, The laser beam induces a laser annealing process on the processing area during the processing period.

28. The system according to claim 26 or 27, wherein, The light spot area completely surrounds the processing area.

29. The system according to any one of claims 26-27, wherein: The light spot region has a size F in the first lateral direction and a size H in the second lateral direction perpendicular to the first lateral direction. The central spot region of the spot region has a dimension E in the first lateral direction and a dimension G in the second lateral direction, wherein: The energy level of the laser beam is constant in the central spot region and decreases in the peripheral spot region.

30. The system according to claim 29, wherein, The central light spot area completely surrounds the processing area.

31. The system according to claim 30, wherein, The processing region covers the core array region in the semiconductor device, the core array region having a dimension A in the first lateral direction and a dimension B in the second lateral direction, and wherein... (A-E+OVL)≤0≤(A-E+SLW), where OVL is the overlap error between the focused laser spot and the processing area, and SLW is the width of the scribe line. (B-G+OVL)≤0≤(B-G+SLW).

32. The system according to claim 30, wherein, The processing region covers the core array region and non-core array region in the semiconductor device. The core array region has a dimension A in the first lateral direction and a dimension B in the second lateral direction. P is the dimension of the non-core array region in the first lateral direction, and Q is the dimension of the non-core array region in the second lateral direction. (mA+jP-E+OVL)≤0≤(mA+jP-E+SLW), where m is a positive integer, OVL is the overlap error between the focused laser spot and the processing area, and SLW is the width of the scribe line. (nB+kQ-G+OVL)≤0≤(nB+kQ-G+SLW), where n is a positive integer and j and k are both non-negative integers.

33. The system according to claim 32, wherein, m is greater than or equal to 2.

34. The system according to claim 32, wherein, The processing area covers all core array regions and non-core array regions in the die of the semiconductor device.

35. The system according to claim 32, wherein, The processing area covers all planes in the die of the semiconductor device.

36. The system according to claim 32, wherein, The processing area covers all the dies in the irradiation field of the semiconductor device.

37. The system according to claim 30, wherein, The processing area covers a wafer having a dimension W in the first lateral direction and a dimension V in the second lateral direction, wherein: F≥(W+OVL), where OVL is the overlap error between the focused laser spot and the processing area, and H≥(V+OVL).

38. The system according to any one of claims 26-27, wherein, The laser annealing process transforms the amorphous silicon layer in the processing region into a polycrystalline silicon layer and activates the implants in the processing region.

39. The system of claim 25, wherein in response to the spot area being equal to or smaller than the processing area, the controller is configured to: Multiple laser beams are aligned with the processing area, each laser beam being within a focused laser spot, and each focused laser spot having multiple spot areas smaller than or equal to the processing area; and The plurality of laser beams are emitted toward the processing area for a continuous processing period.

40. The system according to claim 39, wherein: The light spot region has a dimension F in a first lateral direction and a dimension H in a second lateral direction perpendicular to the first lateral direction, wherein: The energy level of the laser beam is constant in the central spot region and decreases in the peripheral spot region; and The central light spot region has a size E in the first lateral direction and a size G in the second lateral direction, where E is less than F and G is less than H.

41. The system of claim 40, further comprising: The multiple light spot regions are overlapped to form a minimum repeating light spot; as well as The minimum repeating spot is applied multiple times to cover the processing area.

42. The system according to claim 41, wherein, The minimum repeating spot induces a laser annealing process in the processing area during the processing period.

43. The system according to claim 41 or 42, wherein: The number of the multiple light spot regions is four; The lateral dimension of the minimum repeating spot in the first lateral direction is equal to (FE) / 2; and The lateral dimension of the minimum repeating spot in the second lateral direction is equal to (HG) / 2.

44. The system according to any one of claims 41-42, wherein, The processing region covers the core array region in the semiconductor device, the processing region having a dimension C in the first lateral direction and a dimension D in the second lateral direction, the core array region having a dimension A in the first lateral direction and a dimension B in the second lateral direction, and wherein... (mE+OVL)≤C≤(mE+SLW), where OVL is the overlap error between the focused laser spot and the processing area, and SLW is the width of the scribe line. (nG+OVL)≤D≤(nG+SLW), where m and n are both integers.

45. The system according to any one of claims 41-42, wherein, The processing region covers the core array region and non-core array region in the semiconductor device. The processing region has a dimension C in the first lateral direction and a dimension D in the second lateral direction. The core array region has a dimension A in the first lateral direction and a dimension B in the second lateral direction. P is the dimension of the non-core array region in the first lateral direction, and Q is the dimension of the non-core array region in the second lateral direction. (mE+jP+OVL)≤F≤(mE+jP+SLW), where m is a positive integer, OVL is the overlap error between the focused laser spot and the processing area, and SLW is the width of the scribe line. (nG+kQ+OVL)≤H≤(nG+kQ+SLW), where n is a positive integer and j and k are both non-negative integers.

46. ​​The system according to claim 45, wherein, The processing area covers all core array regions and non-core array regions in the die of the semiconductor device.

47. The system according to claim 45, wherein, The processing area covers all planes in the die of the semiconductor device.

48. The system according to claim 45, wherein, The processing area covers all the dies in the irradiation field of the semiconductor device.

49. The system according to any one of claims 25-27 and 39-42, wherein, The processing area is electrically connected to the pads of the semiconductor device via interconnects.

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