Multilayer structure with spacer disk configuration

Abstract

According to various embodiments, a multilayer electromagnetic device is provided. The device includes a first connection layer comprising a first conductive pad having a first capacitance, a feed line coupled between the first conductive pad and a transmission signal source, and a first isolation pad surrounding at least a portion of the first conductive pad, the first isolation pad enabling isolation of electromagnetic signals propagating through the first conductive pad. The first isolation pad has a resonance, which is a function of the first capacitance. The device also includes a second connection layer and a plurality of layers located between the first and second connection layers, the second connection layer including a second conductive pad, the second conductive layer enabling electrical connection with external devices. Depending on the capacitance of the conductive pad, the conductive pad has an isolation pad extending into an available area of ​​the layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 104,369, filed October 22, 2020, the entire contents of which are incorporated herein by reference. Background Technology

[0003] In multilayer semiconductor devices, transmission lines are routed through layers and between layers, forming complex mappings. Specific mappings can lead to undesirable interactions between transmission lines and layers. These effects impact device operation as these mappings are scaled down. Therefore, there is a need for improved methods and / or device configurations that address the challenges of manufacturing devices with increasingly smaller dimensions. Attached Figure Description

[0004] This application can be more fully understood in conjunction with the following detailed description taken in conjunction with the accompanying drawings, which are not drawn to scale, wherein the same reference numerals always refer to the same parts, and wherein:

[0005] Figure 1 An example configuration of an integrated circuit with multiple components is shown in top and perspective views;

[0006] Figure 2 The process of constructing a ball grid array (BGA) structure by directly soldering or connecting between the chip carrier package and the interconnect substrate is illustrated according to various embodiments;

[0007] Figure 3A , Figure 3B and Figure 3C Example multilayer devices incorporating an isolation disk construction according to various embodiments are shown;

[0008] Figure 4A , Figure 4B , Figure 4C and Figure 4D The layers of an example multilayer device having an isolation disk and conductive portions according to various embodiments are shown;

[0009] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E The various layers of an example multilayer device having specific isolation disks and conductive portions according to various embodiments are shown;

[0010] Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6EThe various layers of an example multilayer device with specific isolation disks and conductive portions in an example configuration according to various embodiments are shown;

[0011] Figure 7 and Figure 8 A multilayer device with an isolation disk extension is shown according to various embodiments;

[0012] Figures 9 to 10 A multilayer device with an isolation disk extension is shown according to various embodiments;

[0013] Figure 11A and Figure 11B A multilayer device with an isolation disk extension is shown according to various embodiments;

[0014] Figure 12 The process of developing an isolation disk extension in a multilayer device according to various embodiments is illustrated; and

[0015] Figure 13 Methods for constructing multilayer devices according to various embodiments are illustrated. Detailed Implementation

[0016] The specific embodiments described below are intended to depict various configurations of the subject matter, and not to represent the only configuration in which the subject matter can be practiced. The accompanying drawings are incorporated herein and form part of the specific embodiments. Specific details are included to provide a thorough understanding of the subject matter. However, the subject matter is not limited to the specific details set forth herein and can be practiced using one or more implementations. In one or more instances, structures and components are shown in block diagram form to avoid obscuring the concepts of the subject matter. In other instances, known methods and structures may not be described in detail to avoid unnecessarily obscuring the description of the examples. Furthermore, these examples can be combined with each other.

[0017] This disclosure provides apparatus and methods for implementing desired operations of an integrated circuit (IC), and specifically implements millimeter-wave operation incorporating antipad structures, shapes, and configurations within one or more layers of the IC. According to the various embodiments disclosed in this application, the IC can support any type of device, such as antenna-in-package (AiP) based devices.

[0018] This disclosure provides structures designed at millimeter-wave frequencies based on flip-chip ball grid array (fcBGA or flip-chip BTA) technology, where no existing solutions exist for ultra-wideband packaging designs for future communication systems, including 5G and beyond. These structures achieve the desired performance by implementing irregular isolation disk shapes in the design (e.g., in AiP), where they introduce resonance in the return loss of the structure and improve the operating bandwidth of the system. When determining the layers used to implement these structures, the goal is to design the isolation disks to modify the current distribution, which is achieved by modifying the equivalent capacitance corresponding to the isolation disk and according to the shape and structure of the isolation disk. The examples presented herein are provided for clear understanding and are not intended to be limiting; these examples optimize the shape of the isolation disk, the location and placement of voids, to achieve broadband matching at the frequency of interest. This disclosure is applicable to any conductive layer in the design and can take various shapes. This disclosure provides a means of modifying the current distribution to create broadband matching in any suitable IC and AiP-based device.

[0019] Figure 1 An example configuration of an integrated circuit (IC) 100 having multiple elements 102 is shown in top and perspective views. The IC 100 consists of multiple layers through which transmission lines or electrical conductors are configured. This configuration is called a mapping and can be quite complex, as shown in layer mapping 120 within the IC 100. Each block of a layer is defined by different parameters, such as material, conductor, opening, etc. Conductive portions are coupled between layers by connectors (e.g., connector 122). Depending on the design, the connector can be a conductive material, an open via, a via with conductive perimeter, etc. These mappings become very complex as functionality and operating frequency change.

[0020] Figure 2 A process 200 is illustrated for constructing a ball grid array (BGA) structure 230 by directly soldering or connecting between a chip carrier package and an interconnect substrate. These are also known as face bonding or controlled collapse bonding. They can be configured in various ways, such as peripheral arrays, staggered arrays, distributed arrays, or full-area arrays. BGAs are similar to flip-chip devices and are designed to increase the number and arrangement of input / output (I / O) connections because these connections are not limited to the periphery of the device. The BGA 230 is located on a substrate 202 and has conductive structures or solder balls 205 coupled between the flip chip 204 and the substrate 202.

[0021] The fabrication process begins on substrate 202, where a flip chip 204 is placed. The flip chip 204 includes chip pads 205 for electrical connections to couple with other components. Various structural components 214 are placed to support the flip chip 204. Filler 212 is added on top of the flip chip 204, and then an optional cover 220 can be added. Finally, a BGA 206 is located on the opposite side of substrate 202. The BGA structure or completed device 230 includes additional structures and fillers to complete the package, such as... Figure 2 As shown.

[0022] As referenced above Figure 1 and Figure 2 The BGA devices discussed here increase the number of leads by using a surface area larger than the peripheral side of the device. Furthermore, compared to traditional chip designs, the leads are inflexible because solder balls are used to form robust and non-deformable connections. These devices further reduce coplanarity issues, handling problems, and other issues associated with devices coupled to the board. During the process, the solder balls are self-centering, solving many arrangement problems of surface mount structures. These configurations improve manufacturing yield and operational performance, including thermal and electrical characteristics. The design of BGA devices enables high density in miniature packages.

[0023] This device, when used with flip chips (e.g., fcBGA), enables interconnection between the flip chip die and the substrate. The BGA package can be assembled on a high-density ceramic substrate or a multilayer metal stack. Various packages can be used to provide connectivity to the flip chip die or to protect the flip chip through packaging or other suitable structures. Figure 2 In this package, device 230 encapsulates flip chip 204 using filler 210, filler 212, and optional cover 220. Flip chip 204 includes chip pads 205 located near substrate 202, which is sandwiched between flip chip 204 and BGA 206. Various structural components 214 are present to complete package 230.

[0024] Figure 3A , Figure 3B and Figure 3C A multilayer device 300 incorporating an isolation disk structure is shown according to various embodiments. Figure 3AThe multilayer device 300 shown is an fcBGA device, which includes a layer with a flip chip 340. The flip chip 340 has bumps 330, 332, and 334 coupled to layer 326. Bumps 330, 332, and 334 are also referred to as chip pads 330, 332, and 334. The layers of the multilayer device 300 include: a flip chip layer 324, a BGA pad metal layer 312, a ground (metal) layer 320, a ground (metal) layer 316, a dielectric (insulating) layer 314, a dielectric (core) layer 318, a dielectric (insulating) layer 322, and a solder mask or substrate layer 310. The BGA structure located beneath the substrate (e.g., the layers of the fcBGA device / multilayer device 300) includes BGA solder balls 302, 304, 306, and 308. Figure 3A As shown, BGA 360 includes a BGA pad (metal) layer 312 and BGA solder balls 302, 304, 306, and 308.

[0025] The location and structure of each layer of the multilayer device 300 facilitate the circuitry and transport paths that support the functionality and operation of the flip chip 340. These layers are connected via conductive paths, vias, and other structures. Within each layer, conductive structures called pads provide conductive connections between layers. Layers also include openings or non-conductive regions called isolation pads.

[0026] The multilayer device 300 is a structure with a transition from flip chip to BGA solder balls in a multilayer stack, which in this case is a four (4) layer stack. Figure 3A As shown, flip chip 340 is located on the top layer 326 of the stack. In this disclosure, the transition from chip pads 330, 332, and 334 of flip chip 340 to flip chip layer 324 includes novel structures configured within flip chip layer 340. Depending on the device design and purpose, the flip chip can have any number of chip pads. Additionally, in this disclosure, the transition from the flip chip layer to BGA solder balls 302, 304, 306, and 308 includes novel structures configured within BGA pad layer 312. Various other implementable stacks exist, and device 300 is provided as an example.

[0027] for Figure 3A , Figure 3B and Figure 3CThe configuration of the multilayer device 300 shown includes layers whose parameters (e.g., but not limited to, dielectric constant, loss tangent, thickness, and roughness for each layer) are determined as part of the device's design, configuration, operation, manufacturability, application, cost, etc. BGA solder balls 302, 304, 306, and 308 connect the multilayer device 300 to a motherboard or other application structure. A core layer (e.g., layer 318) is sandwiched between metal layers 316 and 320. Solder mask layers 326 and 310 are located at opposite ends of the stack. Filler, such as underfill material, is used between solder mask layer 326 and the flip chip 340 (including in the area of ​​the chip pads). Open gaps exist between BGA solder balls 302, 304, 306, and 308. The BGA can have any kind of configuration, such as... Figure 1 The solder ball mapping is 120. In various embodiments, the BGA solder balls may have a uniform size and shape. In various embodiments, the BGA solder balls may have a non-uniform size and shape.

[0028] In the example of multilayer device 300, there are two transitions where signals transition from flip chip 340 to BGA solder balls 302, 304, 306, and 308, and are routed within flip chip layer 324. The first transition matches the output of the radio frequency (RF) channel from flip chip 340 to the microstrip line within flip chip layer 324. The second part of the transition matches the microstrip line to BGA solder balls 302, 304, 306, and 308.

[0029] The first transition (e.g., a flip-chip transition) transmits the RF output signal of the flip-chip 340 to the microstrip 350, such as... Figure 3A As shown. The stacked configuration is designed to reduce unwanted reflections and increase transmission gain over a frequency range of 78.5 GHz, with a bandwidth of 10 GHz in this application.

[0030] exist Figure 3B In the middle, the ports of the flip chip 340 are shown as gray circles 352 in layer 324. Figure 3B The transmission path shown includes, for example, a conductive pad 354 coupled to a microstrip 350, and a spacing 356 provided around the combination of the conductive pad 354 and the microstrip 350. Figure 3C The various ports in the (grounded metal) layer 320 are shown, as circle 358.

[0031] The second transition from flip chip layer 324 to BGA solder balls is designed to minimize reflection and insertion loss. See below for reference. Figure 4A , Figure 4B , Figure 4C and Figure 4D This will be described in further detail.

[0032] Figure 4A , Figure 4B , Figure 4C and Figure 4D The layers of an example multilayer device with isolation disks and conductive portions in an example configuration 400 according to various embodiments are shown. Specifically, Figure 4A , Figure 4B , Figure 4C and Figure 4D The transition structure and ports within the BGA pad layer 312 are shown, where the ports include waveguide ports 410 for driving microstrip lines 404 on the flip chip. The microstrip 404 is the path for transmission and is made of a conductive material. Figure 4A As shown, microstrip 404 is surrounded by spacer 402 to isolate the conductive transmission path provided by microstrip 404. Spacer 402 is a stripline gap relative to microstrip 404; this is an open area or discontinuous portion in the conductive layer. Conductive connections 406 are also present to couple to solder layer 310.

[0033] A top view of BGA pad layer 312 Figure 4B As shown in the diagram, a microstrip line 404 is coupled to a conductive pad 410, forming a transmission path. Other conductive connectors 406 are located around the periphery of the transmission path. Connector 406 is a micro-bonded via connecting layers with conductive material and may be a hollow via with a conductive liner or other conductive structure. Connector 406 is part of the complex circuitry and transmission path of the antenna package (AiP) layer.

[0034] exist Figure 4D In the example shown, the (irregularly shaped) isolation disk 428 includes a circular or annular portion and two extensions 422, 420. This shape is specific to the material, shape, size, operating frequency, etc., of a given application. The isolation disk 428 is a transitional structure composed of structures 420, 422, and 424, which are spacers used to separate the conductive portions of layer 312, such as... Figure 4D As shown. Structures 420, 422, and 424 are also irregularly shaped isolation pads. The transition structure (i.e., isolation pad 428) has a main circular portion 424. The transition extensions 420 and 422 are rectangular in this example, but can take various shapes. This results in a complex configuration because the BGA pad layer 312 includes numerous connections to other stacked layers. The BGA pad layer 312 is densely filled with structures for this configuration. The transition extensions 420 and 422 are located in the footprint area of ​​the layer that can be used to build the structure, such as... Figure 4B and4D As shown. The radiating element 410 is made of conductive material and connected to the microstrip line 404, which is used for signal transmission. The second excitation port 430 is located near the radiating element 410 and is a cross-section of the coaxial cable sheath. Additional vias include a core layer through-hole via 434 between layers, which in this example is a solid conductor. Figure 4C The layers shown include layer 440 and layer 444, each made of a conductive material, and a via is present between layer 440 and layer 444.

[0035] continue Figure 4C A conductive third metal layer 450 is located at the opposite end of via 436. A fourth metal layer 452 (i.e., the BGA pad layer) is located near the third metal layer 450, and a micro-bonding via 456 is located between the fourth metal layer 452 and the third metal layer 450. Another metal layer 454 is located near the BGA solder ball 460, as... Figure 4C As shown. The first excitation port 470 is located at the end of the transmission path and is the cross-section of a rectangular waveguide, as shown. Figure 4A As shown.

[0036] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E The illustration shows various layers of an example multilayer device in an example configuration having specific isolation disks and conductive portions according to various embodiments. Specifically, Figure 5A , Figure 5B , Figure 5C , Figure 5D The illustration shows several layers of an example fcBGA device 500 of this disclosure located near the top of the flip-chip device, and... Figure 5E It shows Figure 3A A schematic diagram of the multilayer device 300 is provided for reference. Figure 5A As shown, flip chip layer 540 (and) Figure 3A The multilayer device 300 (corresponding to the flip chip layer 324) has conductive traces or transmission paths 544 (or wiring paths) terminating at wiring pads 546. An isolation pad 548 is an open space surrounding the wiring path 544; this open space is a discontinuity around the wiring path 544. In this example, the isolation pad 548 is surrounded by a series of conductive vias, such as vias 542. Throughout the layer, various vias are implemented to conductively connect transmission paths and circuitry in different layers.

[0037] continue Figure 5B Grounding layer 530 (and) Figure 3AThe multilayer device 300, corresponding to layer 320, is a metal layer in which discontinuous portions 532 (e.g., gaps) are formed, having a shape corresponding to the perimeter of the isolation pad 548, and having an internal conductive portion 538. Structure 538 includes a wiring pad 536 aligned with the wiring pad 546 of layer 540 and another conductive pad 537, which is... Figure 4C The core via 436 is a pad in the structure. In a multilayer structure, the positions of conductive pads and vias are aligned and mated with components in other layers, where the connection between conductive pads and components forms part of a transport path through the device. BGA pad layer 530 includes conductive pad structures (e.g., pad 534) and vias (e.g., via 535).

[0038] Figure 5C The image shows ground plane 520 (and) Figure 3A The ground layer 316 of the multilayer device 300 is a metal layer, which has a discontinuity 522 similar to the discontinuity 532 of layer 530 and other similar structures. Figure 5D The underlying layer shown is a BGA pad layer 502, which has connection pads 508 to BGA solder balls (not shown) and transition pad structures 506 with transition extensions 504 and 510. The main part of the transition pad structure 506 is an annular discontinuous portion within the metal layer 502, similar to... Figure 3A Layer 312 of the multilayer device 300. For example... Figure 5A , Figure 5B , Figure 5C , Figure 5D As shown, the various parameters of these layers are provided in the tables below the illustration, and these tables include, for example, the linewidths of pads 534, 546, isolation pads 548, routing paths 544, structure 538, routing pads 536, routing pads 546, conductive pads 537, discontinuities 522, discontinuities 532, and various dimensions and parameters of features described regarding fcBGA devices 500, flip chip layers 540, ground planes 530, ground planes 520, etc. The layout shapes and dimensions of different features can be configured in various ways.

[0039] Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E The illustration shows various layers of an example multilayer device in an example configuration having specific isolation disks and conductive portions according to various embodiments. Specifically, Figure 5A , Figure 5B , Figure 5C , Figure 5DSeveral layers of an example device 600 in a transitional design are shown, the design being similar to Figure 3A The core layer of layer 318 in the multilayer device 300 is symmetrical. Figure 5E It shows Figure 3A A schematic diagram of the multilayer device 300 is provided for reference. The metal layers at the same distance from the core surface and... Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E The layers of the device 600 shown are largely the same. The flip-chip layer 640 is similar. Figure 5A Layer 540 has routing paths 644 and larger pad areas 646. Layers 630 and 620 are similar. Figure 5B Layer 530 and Figure 5C Layer 520. Layer 602 has a similar structure to... Figure 5D The shape and alignment of layer 502 are consistent; however, the size of the isolation pad 606 surrounding the pad 608 is smaller. The isolation pad structure 606 includes transition extensions 504 and 510, each of which is rectangular. Various shapes and configurations are possible for these transition structures.

[0040] Now for reference Figure 7In one embodiment, the multilayer design is shown by layer 700, which has a flip chip 740 located near flip chip layer 732. At the opposite end of the layered structure is a BGA layer 704 near BGA solder balls 750. The basic structure of layer 700 forming the device is similar to that of device 300, but with added layers and functionality. These additional layers allow designers to more easily design chip packages, route signals in a smaller package area, and reduce the overall package size by utilizing the opportunities provided by the extra layers. The layer stack from top to bottom includes a solder mask 734 located near the flip chip and electrically connected to the flip chip pads (or bumps) 742. The stack is sandwiched between flip chip layer 732 and RF power layer RF1 724 and includes an insulating layer 730, a ground layer 728, and an insulating layer 726. As in other examples presented herein, the isolation layers may incorporate a prepreg material or other materials with desired properties. A similar stack is sandwiched between isolation layer 714 and BGA layer 704, and includes RF power layer RF2 712, isolation layer 710, ground layer 708, and isolation layer 706. Between RF1 layer 724 and RF2 layer 712 is a stack including isolation layer 722, ground layer 720, core layer 718, ground layer 716, and isolation layer 714. Solder mask layer 702 is located near BGA layer 704 and BGA bump 750, where solder layer 702 is used to electrically connect BGA layer 704 to BGA bump 750. The layer structure of layer 700 is symmetrical about core layer 718. Layer 700 can be designed and configured using various materials, sizes, and scales. More or fewer layers can be implemented depending on the application's function, operating frequency range, cost, size, and other requirements.

[0041] like Figure 7 As shown, there are three transitions stacked on top of one another. The first transition is from flip chip 740 to RF1 layer 724, identified by block 760. The second transition is from RF1 layer 724 to RF2 layer 712, identified by block 762. The third transition is from RF2 layer 712 to BGA layer 704, identified by block 764. In this illustration, additional layers are incorporated into... Figure 3A The structure of the multilayer device 300 shown is used to implement additional routing of RF signals.

[0042] The first transition (block 760) from flip chip 740 to RF1 layer 724 is configured to transmit the RF signal output from flip chip 740 to RF1 layer 724 with reduced reflection and loss. Figure 8 The layout shape is further illustrated for each layer. For example... Figure 8As shown, in one embodiment, the flip chip layer 840 includes conductive pads 846 located within an isolation pad region 848. The conductive pads 846 are aligned with the chip pads of the flip chip. The shape of the isolation pad region 848 is such that the flip chip layer 840 (and...) Figure 7 The elliptical discontinuous portion within layer 732 (corresponding to layer 830). In ground layer 830 (and... Figure 7 In layer 728 (corresponding to layer 728), isolation pad 832 has a shape similar to that of isolation pad 838; within isolation pad 838, conductive pad 836 is configured to couple with conductive pad 846 and second conductive pad 837 of layer 840. The next layer 820 includes conductive pad 826 aligned with pad 837 of layer 830. Wiring lines 824 are connected to pad 826, and the isolation pad structure surrounds the wiring lines 824 and pad 826. Isolation pad 822 includes a straight portion therebetween having the wiring lines 824 and a circular portion surrounding the pad 826. Ground layer 802 has a via 804 located therein, such as... Figure 8 As shown.

[0043] According to various embodiments, for the second transition from RF1 layer to RF2 layer, in Figure 9 Several layers are shown for stack 900. Located in flip chip layer 940 are a series of vias 948 arranged in a semi-circular pattern, corresponding to isolation pads in other layers. In ground layer 930, vias 938 are similarly arranged in a semi-circular pattern, having extending vias 934 and 936 protruding into unused areas of layer 930, arranged around microstrip lines on 920. Isolation pads 932 are configured within vias 938 and their shape is defined by the vias 938. In RF1 layer 920, semi-circles similar to vias 928 are used to define isolation pads 922. Pads 927 are located at the ends of wiring lines 925. Isolation pads 922 have extensions 924 and 926 on each side of wiring lines 925. In the next ground layer 902, isolation pads 904 are located within vias 908. Pads 910 and 906 are located within isolation pad 904. These structures transmit signals across different layers.

[0044] Figure 10A third transition for passing routing signals on the RF2 layer to the BGA solder balls is illustrated according to various embodiments. In this example, one end of the third transition is a 50-ohm microstrip line 1072 on the RF2 layer 1070 (where the RF2 layer 1070 corresponds to layer 712 of the layer stack 700), and the other end is a 50-ohm microstrip line on the top layer of a reference motherboard 1002 excited using waveguide port 1004. In this example, for this part of the transition scheme, the transition is optimized to achieve minimum reflection and maximum transmission around 78.5 GHz with a 10 GHz bandwidth at -10 dB return loss.

[0045] Figure 10 The transition according to various embodiments and the location of the different layers of ports and packages are shown. In this transition, port 1 1073 is a rectangular waveport at the edge of microstrip line 1072 on RF2 layer 1070, and port 2 1004 is also a waveport (waveguide port) of microstrip line 1006 attached to motherboard 1002.

[0046] Ground layer 1080 includes an elliptical via 1088 located on a conductive material. RF2 layer 1070 has a similarly elliptical via 1078, within which is a conductive pad 1076 coupled to a microstrip line 1072. This ellipse is aligned with the ellipses of other layers 1080, 1060, and 1050. The conductive pad 1076 and the microstrip line 1072 form a wiring path 1074. The wiring path 1074 is surrounded by an isolation pad 1075. Ground layer 1060 includes an elliptical via 1068, within which is a pad region 1066 and an isolation pad ellipse 1065.

[0047] BGA layer 1050 includes vias 1058 forming an ellipse, within which pads 1056 are surrounded by isolation pads 1055. Stack 1000 is shown in a perspective view, and stack 1000 is located on motherboard 1002. Motherboard 1002 includes ports 1004 for driving microstrip 1006.

[0048] Another example of stacking 1100 in Figure 11A As shown in the image. Figure 11AAs shown, there are various layers, including RF1 layer 1124, RF2 layer 1112, flip chip layer 1132, and BGA layer 1104. There are three transitions, represented by boxes 1160, 1162, and 1164. The first transition 1160 is from flip chip layer 1132 to RF1 layer 1124; the second transition 1162 is from RF1 layer 1124 to RF2 layer 1112; and the third transition is from RF2 layer 1112 to BGA layer 1104. As shown, flip chip 1140 and chip pad 1142 are located on top of stack 1100. At the opposite end is BGA solder ball 1150. At the center of stack 1100 is core layer 1118. The RF layer is provided for radio signal and / or digital signal processing. In this example, core 1118 is a low-loss dielectric layer with a thickness of approximately 200 μm, sandwiched between metal layers 1120 and 1116. Power and ground planes can be used interchangeably in these and other designs.

[0049] Figure 11B Examples of layers in stack 1100 are shown, including a flip chip layer 1132 in which vias 1134 are disposed. The flip chip arrangement is identified by a rectangular region 1170 located at the top of stack 1100. The location of flip chip layer 1132 is electrically coupled to at least one chip pad of the flip chip at location 1172.

[0050] Figure 12A process 1200 for developing an isolation pad extension in a multilayer device according to various embodiments is illustrated. Process 1200 includes: at step 1210, determining a usable area in the flip-chip layer for the isolation pad extension. This is an area not used for conductive pads or other structures and can be used to isolate signals so that signals flow through the device without interfering with its operation. For each layer, there are operating criteria for the isolation pad, such as loss level, reflection level, etc., therefore process 1200 includes: at step 1220, determining the operating criteria for the isolation pad. Based on this information, a flip-chip layer isolation pad extension is designed within the usable area, which allows the isolation pad to be designed within the usable area of ​​the flip-chip layer in step 1230 of process 1200. The design is tested (e.g., by simulation) to meet the operating criteria, so process 1200 includes: at step 1240, evaluating whether the designed isolation pad meets the operating criteria via simulation. If the design fails, the process updates the design of the flip-chip layer isolation pad extension, which may involve size adjustments, shape changes, etc. Therefore, process 1200 includes updating the isolation pad design at step 1250 by changing one of the size, shape, or dimensions of the isolation pad. In various embodiments, a similar process 1260, similar to process 1200, applies to the BGA layer and the isolation pad extension formed therein. Therefore, process 1200 may also include optionally performing steps 1210, 1220, 1230, 1240, and / or step 1250 on the BGA layer and the isolation pad extension within the BGA layer, and / or any other suitable layer (e.g., ground layer, core layer, etc.) disclosed throughout this disclosure.

[0051] Figure 13 A method 1300 for constructing a multilayer device according to various embodiments is illustrated. Method 1300 includes: at step 1310, determining the arrangement of conductive pads on layers of the multilayer device; at step 1320, calculating the capacitance of the conductive pads; at step 1330, determining a region near the conductive pads where no integrated circuit construction exists, wherein the determined region may include isolation pads; and at step 1340, generating the shape and position of the isolation pads based on the capacitance of the conductive pads. In various embodiments, the isolation pads are located near the conductive pads and have an isolation pad extension away from the conductive pads.

[0052] In various embodiments and implementations, method 1300 may optionally include: at step 1350, verifying that the multilayer device is within millimeter-wave frequency operating parameters for electromagnetic transmission via conductive pads; and may optionally include: at step 1360, generating the shape and position of an isolation pad based on the verification.

[0053] In various embodiments and implementations, the layer of the multilayer device is a first layer, and method 1300 may optionally include: at step 1370, designing a condition region in a second layer of the multilayer device based on conductive pads. In some embodiments, method 1300 may include: designing a conductive region in the second layer of the multilayer device, wherein the conductive region may be coordinated with or correspond to the conductive pads.

[0054] According to various embodiments, a multilayer electromagnetic device is provided. The device includes a first connection layer comprising a first conductive pad having a first capacitance, a feed line coupled between the first conductive pad and a transmission signal source, and a first isolation pad surrounding at least a portion of the first conductive pad, the first isolation pad isolating electromagnetic signals propagating through the first conductive pad. In various embodiments, the first isolation pad has a resonance that is a function of the first capacitance. The device also includes a second connection layer and a plurality of layers located between the first and second connection layers, the second connection layer including a second conductive pad, the location of the second conductive layer being electrically connected to an external device. In various embodiments, depending on the capacitance of the conductive pad, the first and / or second conductive pads may have an isolation pad extension into the available area of ​​the layer.

[0055] According to various embodiments and implementations, a multilayer electromagnetic device is described. The multilayer electromagnetic device may include a first connection layer comprising a first conductive pad that provides an electrical connection to a transmission signal source, wherein the first conductive pad has a first capacitance. The multilayer electromagnetic device may further include a feed line coupled between the first conductive pad and the transmission signal source, and a first isolation pad surrounding at least a portion of the first conductive pad, the first isolation pad providing isolation for electromagnetic signals propagating through the first conductive pad. In various embodiments, the first isolation pad has a resonance, which is a function of the first capacitance. Furthermore, the multilayer electromagnetic device may include a second connection layer and a plurality of layers located between the first and second connection layers, the second connection layer having second conductive pads that provide electrical connections to external devices.

[0056] According to various embodiments, the second connection layer may further include a second isolation disk surrounding at least a portion of the second conductive pad, the second isolation disk providing isolation for electromagnetic signals propagating through the second conductive pad. In various implementations, the first connection layer also includes a microstrip line coupled to the first conductive pad and the input port. In various embodiments, the first isolation disk surrounds at least a portion of the microstrip line. In various embodiments, the first isolation disk and the microstrip line form a wiring path within the multilayer electromagnetic device.

[0057] In various embodiments, the first isolation pad may include a first isolation pad structure near a first conductive pad (wherein the first isolation pad structure is a discontinuous portion in the first interconnect layer) and a second isolation pad structure coupled to the first isolation pad structure and extending into the first interconnect layer. In some embodiments, the first isolation pad structure has a first shape, while the second isolation pad structure has a second shape different from the first shape. In various embodiments, the second isolation pad structure includes two structures connected in parallel. In various embodiments, the first shape and the second shape are functions of a first capacitance. In various embodiments, the first interconnect layer, the second interconnect layer, and the plurality of layers form an antenna package (AIP) device.

[0058] According to various embodiments, the multilayer electromagnetic device may include an integrated circuit mapped to an AIP device, the integrated circuit being configured to operate in the millimeter-wave frequency range of electromagnetic signals. In various embodiments, the first isolation disk is a discontinuity within the first interconnect layer.

[0059] According to various embodiments and implementations, a method for constructing a multilayer device is described. The method includes: determining the arrangement of conductive pads on layers of the multilayer device; calculating the capacitance of the conductive pads; determining a region near the conductive pads where no integrated circuit construction is present, wherein the determined region may include isolation pads; and generating the shape and location of the isolation pads based on the capacitance of the conductive pads, wherein the isolation pads are near the conductive pads and have an isolation pad extension away from the conductive pads.

[0060] In various embodiments, the method further includes: verifying that the multilayer device is within millimeter-wave frequency operating parameters for electromagnetic transmission via conductive pads; and generating the shape and position of the isolation pad based on the verification.

[0061] In various embodiments, the method further includes: designing an adjustment region in the second layer of the multilayer device based on conductive pads.

[0062] Antenna packages are described according to various embodiments and implementations. An antenna package includes: multiple layers including a ground plane; an isolation layer; a first conductive layer including a first pad and a first isolation pad, wherein the first pad having a first capacitance is coupled to a first signal transmission source, and the first isolation pad has a resonance that is a function of the first capacitance of the first pad; and a second conductive layer including a second pad configured to provide electrical contact to external devices.

[0063] In various embodiments, the first isolation pad is a discontinuity within the first conductive layer and surrounds at least a portion of the first pad, thereby isolating electromagnetic signals propagating through the first pad. In various embodiments, the first isolation pad includes a first isolation pad structure near the first pad, wherein the first isolation pad structure is a discontinuity within the first conductive layer. In various embodiments, the first isolation pad further includes a second isolation pad structure coupled to the first isolation pad structure and extending into the first conductive layer. In various embodiments, the first isolation pad structure has a first shape, while the second isolation pad structure has a second shape different from the first shape.

[0064] In the various embodiments and implementations disclosed herein, operating criteria include the resonant characteristics and capacitance or reactance values ​​of the resonant elements. This determines the shape of the isolation disk and its position relative to the radiating element. The design process is iterative in some examples, while in others, the calculations are part of an electromagnetic signal simulation. The design is also constrained by manufacturing process requirements, including materials, dimensions, the percentage of conductive material on the substrate or layer, etc. These requirements may limit the overall size, footprint, and / or cost of the device.

[0065] It should be understood that the prior description of the disclosed examples is provided to enable those skilled in the art to make or use this disclosure. Various modifications to these examples will be apparent to those skilled in the art, and the general principles defined herein may be applied to other examples without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments shown herein, but is accorded the broadest scope consistent with the principles and novel features disclosed herein.

[0066] As used herein, the phrase "at least one" preceding a series of items, separated by the terms "and" or "or," modifies the list as a whole, rather than each member of the list (i.e., each item). The phrase "at least one" does not require selection of at least one item; instead, it allows for meanings such as: at least one of any item, and / or at least one of any combination of items, and / or at least one of each item. As an example, the phrases "at least one of A, B, and C" or "at least one of A, B, or C" respectively refer to: only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.

[0067] Furthermore, with regard to the terms “comprising”, “having”, etc., used in the specification or claims, such terms are intended to include in a manner similar to how the term “comprising” is interpreted when used as a transitional word in the claims.

[0068] Unless otherwise specified, reference to elements in the singular is not intended to mean "one and only one," but rather "one or more." The term "some" refers to one or more. Underlined and / or italicized headings and subheadings are used for convenience only, do not limit the subject matter, and are not referenced in connection with the interpretation of the description of the subject matter. All structural and functional equivalents of the various configurations of elements described throughout this disclosure are known to or will be known hereafter by those skilled in the art, and these equivalents are expressly incorporated herein by reference and are intended to be covered by the subject matter. Furthermore, nothing disclosed herein is intended to be exclusive to the public, regardless of whether such disclosure is expressly stated in the foregoing description.

[0069] Although this specification contains numerous details, these details should not be construed as limiting the scope of the claims, but rather as descriptions of specific implementations of the subject matter. Certain features described in the context of individual implementations may also be implemented in combination within a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combinations may, in some cases, be removed from the combinations, and the claimed combinations may be for sub-combinations or variations thereof.

[0070] The subject matter of this specification has been described in light of specific aspects, but other aspects may be implemented and are within the scope of the appended claims. For example, although operations are described in a specific order in the drawings, this should not be construed as requiring such operations to be performed in the specific order shown or in sequence, or performing all of the shown operations to achieve the desired result. The actions cited in the claims may be performed in a different order and still achieve the desired result. As an example, the processes depicted in the drawings do not necessarily require the specific order shown or in sequence to achieve the desired result. Furthermore, the separation of the various system components in the aspects described above should not be construed as requiring such separation in all aspects, and it should be understood that the described program components and systems can generally be integrated together in a single hardware product or packaged into multiple hardware products. Other variations are within the scope of the appended claims.

Claims

1. A multilayer electromagnetic device, comprising: The first connection layer includes: A first conductive pad enables an electrical connection to a signal transmission source, and the first conductive pad has a first capacitor. A feeder line is coupled between the first conductive pad and the signal transmission source; and A first isolation disk surrounds at least a portion of the first conductive pad, the first isolation disk enabling the isolation of electromagnetic signals propagating through the first conductive pad, wherein the first isolation disk has a resonance that is a function of the first capacitance. The second connection layer includes a second conductive pad, the second conductive pad enabling electrical connection with an external device; and Multiple layers are located between the first connection layer and the second connection layer.

2. The multilayer electromagnetic device according to claim 1, wherein, The second connection layer further includes a second isolation disk that surrounds at least a portion of the second conductive pad, the second isolation disk enabling the isolation of electromagnetic signals propagating through the second conductive pad.

3. The multilayer electromagnetic device according to claim 1, wherein, The first connection layer also includes a microstrip line coupled to the first conductive pad and the input port.

4. The multilayer electromagnetic device according to claim 3, wherein, The first isolation disk surrounds at least a portion of the microstrip line.

5. The multilayer electromagnetic device according to claim 4, wherein, The first isolation disk and the microstrip line form a wiring path within the multilayer electromagnetic device.

6. The multilayer electromagnetic device according to claim 1, wherein, The first isolation disk includes: A first isolation pad structure near the first conductive pad, wherein the first isolation pad structure is a discontinuous portion in the first interconnect layer; and A second isolation disk structure is coupled to the first isolation disk structure and extends into the first connection layer.

7. The multilayer electromagnetic device according to claim 6, wherein, The first isolation disk structure has a first shape, and the second isolation disk structure has a second shape that is different from the first shape.

8. The multilayer electromagnetic device according to claim 7, wherein, The second isolation disk structure comprises two structures connected in parallel.

9. The multilayer electromagnetic device according to claim 7, wherein, The first shape and the second shape are functions of the first capacitor.

10. The multilayer electromagnetic device according to claim 1, wherein, The first connection layer, the second connection layer, and the plurality of layers form an antenna package (AIP) device.

11. The multilayer electromagnetic device according to claim 10, further comprising: An integrated circuit mapped to the AIP device, the integrated circuit being configured to operate in the millimeter-wave frequency range of electromagnetic signals.

12. The multilayer electromagnetic device according to claim 1, wherein, The first isolation disk is a discontinuous portion within the first connection layer.

13. A method for constructing a multilayer device, comprising: Determine the arrangement of conductive pads on the layers of the multilayer device; Calculate the capacitance of the conductive pad; Determine an area near the conductive pads where there is no integrated circuit construction, wherein the determined area includes isolation pads; and The shape and position of the isolation pad are generated based on the capacitance of the conductive pad, wherein the isolation pad is near the conductive pad and has an isolation pad extension away from the conductive pad.

14. The method of claim 13, further comprising: Verify that the multilayer device is within the millimeter-wave frequency operating parameters to enable electromagnetic transmission through the conductive pads; as well as The shape and position of the isolation disk are generated based on the verification.

15. The method according to claim 14, wherein, The layer of the multilayer device is the first layer, and the method further includes: An adjustment region is designed in the second layer of the multilayer device based on the conductive pads.

16. An antenna package, comprising: Multiple layers, including: Grounding layer; Isolation layer; The first conductive layer includes the first pad and the first isolation pad. Wherein, the first pad has a first capacitance, the first pad is coupled to a signal transmission source, and the first isolation pad has resonance, the resonance being a function of the first capacitance of the first pad; and A second conductive layer including a second pad, the second pad being configured to provide electrical contact to an external device.

17. The antenna package according to claim 16, wherein, The first isolation pad is a discontinuous portion within the first conductive layer and surrounds at least a portion of the first pad, the first isolation pad enabling the isolation of electromagnetic signals propagating through the first pad.

18. The antenna package according to claim 16, wherein, The first isolation pad includes a first isolation pad structure near the first pad, wherein the first isolation pad structure is a discontinuous portion in the first conductive layer.

19. The antenna package according to claim 18, wherein, The first isolation disk also includes a second isolation disk structure, which is coupled to the first isolation disk structure and extends into the first conductive layer.

20. The antenna package according to claim 19, wherein, The first isolation disk structure has a first shape, and the second isolation disk structure has a second shape that is different from the first shape.

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