Interface state test method and apparatus

Abstract

This disclosure provides a planar interface state testing method and apparatus for applications involving transistor interface state measurement. The interface state testing method includes: after testing the transistor under test using a capacitance-voltage testing method, acquiring the DC current output from the substrate of the transistor under test; calculating the integral of the DC current over time in the accumulation region to obtain the injected charge; extracting the oxide layer leakage current, which is linearly related to the test voltage, from the DC current in the accumulation region, and calculating the integral of the oxide layer leakage current over time to obtain the oxide layer leakage charge; and determining the interface state charge of the transistor under test based on the injected charge and the oxide layer leakage charge. This method couples interface state testing to capacitance-voltage testing, resulting in a simple and easy-to-implement testing method that saves testing resources and reduces testing costs.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor testing technology, and in particular to an interface state testing method and apparatus. Background Technology

[0002] With the rapid development of integrated circuits, the feature size of transistors is constantly shrinking, and the influence of the dielectric and substrate on transistor performance is becoming increasingly serious. The interface states of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are important factors affecting the flat-band voltage and threshold voltage of the device.

[0003] In related technologies, the charge pump (CP) method is commonly used to measure the interfacial density of states, and its schematic diagram is shown below. Figure 1 As shown, the source and drain of the transistor are shorted and reverse-biased to the substrate, which is grounded. A periodic pulse is applied to the transistor gate, and the interface state density is calculated by observing the change in the substrate current (i.e., the pump current). The charge pump method for interface state measurement requires the pulse rise and fall times to be less than the time constant of interface state emission, placing high demands on test parameters and making the test implementation difficult.

[0004] Therefore, there is an urgent need to provide a simple and easy-to-implement interface testing solution. Summary of the Invention

[0005] This disclosure provides an interface state testing method and apparatus that utilizes the traditional CV (Capacitance-Voltage) testing method for interface state testing. This eliminates the need for additional testing procedures, reduces testing costs, and makes the testing method easy to implement.

[0006] In a first aspect, embodiments of this disclosure provide an interface state testing method, the method comprising:

[0007] After testing the transistor under test according to the capacitor voltage test method, the DC current output by the substrate of the transistor under test is obtained;

[0008] The amount of injected charge is obtained by calculating the integral of the DC current over time in the accumulation region;

[0009] Extract the oxide layer leakage current that is linearly related to the test voltage from the DC current in the accumulation region, and calculate the integral of the oxide layer leakage current with time to obtain the oxide layer leakage charge.

[0010] The interface state charge of the transistor under test is determined based on the injected charge and the oxide layer leakage charge.

[0011] In some embodiments, the method further includes:

[0012] Obtain the ideal injected charge of the transistor under test, wherein the ideal injected charge is the injected charge of the transistor under test in the accumulation region when the transistor under test is considered to be an ideal transistor;

[0013] Determining the interface state charge of the transistor under test based on the injected charge and the oxide layer leakage charge includes:

[0014] The interface state charge is determined to be the difference between the injected charge, the oxide layer leakage charge, and the ideal injected charge.

[0015] In some implementations, obtaining the ideal injected charge of the transistor under test includes:

[0016] The ideal injected charge is determined based on the channel doping concentration and gate dielectric thickness of the transistor under test.

[0017] In some embodiments, after testing the transistor under test using a capacitance-voltage test method, obtaining the DC current output from the substrate of the transistor under test includes:

[0018] After testing the transistor under test according to the capacitance voltage test method, the output current of the substrate of the transistor under test is sampled;

[0019] The DC component of the output current is extracted to obtain the DC current.

[0020] In some embodiments, after testing the transistor under test using a capacitance-voltage test method, obtaining the DC current output from the substrate of the transistor under test includes:

[0021] After testing the transistor under test according to the capacitor voltage test method, a data file describing the relationship between the DC current, time and test voltage is obtained, and an integration operation is performed based on the data file.

[0022] In some embodiments, the method further includes:

[0023] Obtain the capacitance-voltage curve of the transistor under test, which is used to describe the change in capacitance of the transistor under test under the test voltage;

[0024] The accumulation region is determined based on the capacitor voltage curve.

[0025] In some embodiments, the method further includes:

[0026] Based on the capacitance of the transistor under test read under multiple test voltages, plot the capacitance-voltage curve of the transistor under test;

[0027] The accumulation region is determined based on the capacitor voltage curve.

[0028] In some implementations, determining the accumulation region based on the capacitor voltage curve includes:

[0029] Based on the capacitor voltage curve, determine the voltage range corresponding to the accumulation region;

[0030] Based on the voltage range corresponding to the accumulation zone, and the correspondence between the test voltage, time, and DC current, the time range corresponding to the accumulation zone is determined so that integration can be performed within the time range corresponding to the accumulation zone.

[0031] In some embodiments, extracting the oxide leakage current that is linearly related to the test voltage from the DC current located in the accumulation region includes:

[0032] The DC current is decomposed to obtain the oxide layer leakage current, which is linearly related to the test voltage;

[0033] Extract the oxide layer leakage current within the time range corresponding to the accumulation region.

[0034] In some embodiments, the method further includes:

[0035] Based on the capacitance of the transistor under test read at multiple test voltages, a capacitance-voltage curve of the transistor under test is plotted.

[0036] In some embodiments, the method further includes:

[0037] After shorting the source and drain of the transistor under test and grounding the substrate, a test voltage is applied to the gate of the transistor under test in a potential scanning manner to test the transistor under test in the manner of capacitance voltage test.

[0038] In some implementations, the potential scanning method of the test voltage is either scanning from the accumulation region to the inversion region or scanning from the inversion region to the accumulation region.

[0039] In some embodiments, the method further includes:

[0040] If the interface state charge of the transistor under test is higher than the preset charge, an interface defect warning message for the transistor under test is generated.

[0041] In some embodiments, the method further includes:

[0042] A test report is generated based on the interface state charge of each transistor under test.

[0043] Secondly, embodiments of this disclosure provide an interface state testing apparatus, comprising:

[0044] A DC current reading module is used to acquire the DC current output from the substrate of the transistor under test after testing the transistor under test in the manner of capacitor voltage testing.

[0045] The injected charge calculation module is used to calculate the integral of the DC current over time in the accumulation region to obtain the injected charge.

[0046] The oxide layer leakage current calculation module is used to extract the oxide layer leakage current that is linearly related to the test voltage in the DC current of the accumulation area, and calculate the integral of the oxide layer leakage current with time to obtain the oxide layer leakage current.

[0047] The interface state charge determination module is used to determine the interface state charge of the transistor under test based on the injected charge and the oxide layer leakage charge.

[0048] Thirdly, this disclosure also provides a testing device, including: a memory and at least one processor;

[0049] The memory stores computer-executed instructions;

[0050] The at least one processor executes computer execution instructions stored in the memory, causing the test device to implement the method provided in the first aspect.

[0051] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the method provided in the first aspect.

[0052] Fifthly, embodiments of this disclosure also provide a computer program product, including a computer program that, when executed by a processor, implements the method provided in the first aspect.

[0053] The interface state testing method and apparatus provided in this disclosure, targeting the application scenario of transistor interface state measurement, eliminates the need for additional test program design. It utilizes the traditional capacitor-voltage testing method to test the transistor under test. During the test, the DC current output from the substrate of the transistor under test is continuously acquired, and interface state measurement is performed based on this DC current and the charge conservation law. Since the interface state current is generated only in the accumulation region, interface state measurement can be performed based on the change in the DC current in the accumulation region. Specifically, the DC current is integrated along the accumulation region to obtain the injected charge, and the oxide leakage current, which is linearly related to the test voltage, is integrated along the accumulation region to obtain the oxide leakage charge. Based on the charge conservation law, the injected charge, and the oxide leakage charge, the interface state charge is determined, thus achieving interface state measurement. Because interface state measurement is coupled to the traditional capacitor-voltage testing method, separate interface state testing is unnecessary; interface state measurement can be achieved based on the substrate output current during capacitor-voltage testing, saving testing resources and reducing costs. Furthermore, the interface state testing structure is simple, and the testing scheme is easy to implement, reducing the difficulty of interface state testing. Attached Figure Description

[0054] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0055] Figure 1 This is a schematic diagram of a charge pump method for measuring interface states provided in an embodiment of this disclosure;

[0056] Figure 2 This is a flowchart illustrating an interface state testing method provided in an embodiment of this disclosure;

[0057] Figure 3A For this disclosure Figure 2 A schematic diagram of the test structure for capacitor voltage testing in the illustrated embodiment;

[0058] Figure 3B for Figure 3A A graph of the test voltage in the illustrated embodiment;

[0059] Figure 4A For this disclosure Figure 2 A schematic diagram of the relationship curves between DC current, time, and test voltage in the illustrated embodiment;

[0060] Figure 4B From Figure 4A I was extracted from the relationship curve shown. E A schematic diagram;

[0061] Figure 5A flowchart illustrating another interface state testing method provided in this embodiment of the present disclosure;

[0062] Figure 6 Oxide layer leakage current I provided in one embodiment of this disclosure E and displacement current I C A schematic diagram;

[0063] Figure 7 This is a schematic diagram of the structure of an interface state testing device provided in an embodiment of this disclosure;

[0064] Figure 8 This is a structural block diagram of a testing device provided in an embodiment of this disclosure;

[0065] Figure 9 This is a schematic diagram of the structure of a testing system provided in an embodiment of this disclosure.

[0066] The accompanying drawings have illustrated specific embodiments of the present disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0067] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this disclosure as detailed in the appended claims.

[0068] First, the terms used in this disclosure will be explained.

[0069] Interface states: Discrete or continuous electronic energy levels or bands within the silicon bandgap at the silicon-silicon dioxide interface can exchange charges with the substrate; these are also known as fast interface states. Interface states have a significant impact on the threshold voltage drift of devices.

[0070] Capacitance-to-Voltage (CV) test: Used to test the CV curve, which can be performed using a CV tester. After establishing the test loop, the CV curve of the transistor is plotted by applying a varying voltage to the transistor gate.

[0071] Figure 1 This is a schematic diagram of a charge pump method for measuring interface states provided in an embodiment of this disclosure, as shown below. Figure 1As shown, when measuring interface states based on the charge pump method, the source S and drain D of the transistor MOSFET need to be shorted and connected to a voltage source Vr that is reverse biased from the substrate. The substrate Bulk is grounded, and the gate G is connected to an external pulse generator to apply a periodic pulse signal to the gate G. The current output by the substrate Bulk, i.e., the substrate current (pump current), is read through a galvanometer, oscilloscope, etc. The interface state density is deduced from the change in the substrate current.

[0072] The charge pump method is essentially a transient test, meaning the channel needs to repeatedly switch between the accumulation and inversion regions. Furthermore, to ensure the substrate current originates entirely from the interface states and the majority carrier recombination process, the rise and fall times of the pulse signal applied to the gate (G) must be shorter than the time constant of interface state emission and longer than the time it takes for free carriers to return to the source (S) or drain (D). This places high demands on the pulse signal output from the pulse generator, making the test difficult to implement. Moreover, the charge pump method assumes the substrate current originates entirely from the interface states and the majority carrier recombination process, neglecting the recombination current of both majority and minority carriers, resulting in poor accuracy in interface state density measurement.

[0073] To address the aforementioned issues, this disclosure provides an interface state testing method that replaces the traditional charge pump testing method with a capacitance voltage test. Since capacitance voltage testing is an integral part of transistor performance testing, coupling interface state testing to capacitance voltage testing eliminates the need for a separate test procedure, thus saving testing costs. During transistor testing based on the capacitance voltage test method, the DC current output from the transistor substrate is continuously acquired, and the interface state charge is determined based on this DC current and the law of charge conservation. The testing scheme is easy to implement and overcomes the problem of poor test accuracy caused by neglecting the recombination current of majority and minority carriers in the charge pump testing method.

[0074] The specific process for determining the interface state charge is as follows: Integrate the DC current along the accumulation region to obtain the injected charge, and integrate the oxide leakage current in the DC current that is linearly related to the test voltage along the accumulation region to obtain the oxide leakage charge. Based on the law of conservation of charge, the injected charge, and the oxide leakage charge, determine the interface state charge.

[0075] Figure 2 This is a flowchart illustrating an interface state testing method provided in an embodiment of this disclosure. The interface state testing method provided in this embodiment can be executed by an electronic device with corresponding data processing capabilities, such as a testing device. Figure 2 As shown, the interface state testing method includes the following steps S201 to S204.

[0076] S201, after testing the transistor under test in accordance with the capacitor voltage test method, obtain the DC current output by the substrate of the transistor under test.

[0077] The transistor to be tested is a MOSFET, and there can be one or more of them.

[0078] The capacitor voltage test method for testing transistors specifically includes:

[0079] Connect the transistor under test according to the test structure of capacitor voltage test to form a test circuit, and apply the test voltage Vgs to the gate of the transistor under test.

[0080] During capacitor voltage testing, an optional test structure can be: short-circuiting the source and drain of the transistor under test and grounding the substrate.

[0081] A capacitance voltage tester can be used to test the capacitance voltage of the transistor under test and collect the current output from its substrate during the test.

[0082] When performing capacitor voltage testing, the test voltage Vgs can be obtained by potential scanning, such as linear potential scanning.

[0083] The method further includes:

[0084] After shorting the source and drain of the transistor under test and grounding the substrate, a test voltage Vgs is applied to the gate of the transistor under test in a potential scanning manner to test the transistor under test in the manner of capacitance voltage test.

[0085] The test voltage Vgs can be generated by a potentiostat and a pulse generator. The test voltage Vgs used in each round of testing is the voltage obtained by superimposing a constant potential with a pulse voltage. The voltage value of the constant potential is different in different rounds of testing.

[0086] The potential of the test voltage Vgs can be varied by a step potential from the scan start potential to the scan end potential. During the potential scan, an AC signal (disturbance voltage) can also be superimposed on each step potential.

[0087] For example, Figure 3A For this disclosure Figure 2 A schematic diagram of the test structure for capacitor voltage testing in the illustrated embodiment. Figure 3B for Figure 3A The curve of the test voltage in the illustrated embodiment is as follows: Figure 3A As shown, during the capacitance voltage test, the source (S) and drain (D) of the transistor under test are shorted, the substrate (Bulk) is grounded, and a test voltage Vgs is applied to the gate (G) and source (S) of the transistor under test. The variation curve of the applied test voltage Vgs is shown in the figure. Figure 3B As shown, the test voltage Vgs, at the same frequency, rises one step potential from an initial potential (scan start potential) to a final potential (scan end potential) each time. During each scan, the applied test voltage includes a constant voltage, which is maintained for a period of time, and then a perturbation voltage ΔVgs is superimposed on this constant voltage. Figure 3B The perturbation voltage ΔVgs is only present in the second scan. It is important to understand that the perturbation voltage ΔVgs exists in the remaining scans. The potential of the constant voltage corresponding to each scan is different, and the applied perturbation voltage ΔVgs can be the same.

[0088] The potential scanning method for the test voltage is either scanning from the accumulation region to the inversion region or scanning from the inversion region to the accumulation region.

[0089] The test voltage corresponding to the accumulation region is less than the flat-band voltage V of the transistor under test. FB The test voltage corresponding to the inversion region is greater than the threshold voltage V of the transistor under test. th .

[0090] In the scanning method from the accumulation region to the inversion region, the scan start potential is lower than the scan end potential. The scan start potential is a potential less than 0V, while the scan end potential is greater than the threshold voltage V of the transistor under test. th In the scanning method from the inversion region to the accumulation region, the scan start potential is greater than the scan end potential, and the scan start potential is greater than the threshold voltage V of the transistor under test. th The scanning endpoint potential is a potential less than 0V.

[0091] The charge pump-based testing method is a transient test, requiring control of the channel to repeatedly switch between accumulation and inversion. The potential scanning testing method provided in this disclosure is a steady-state test. Using the testing method provided in this disclosure more closely resembles the operating scenario of a transistor, improving the accuracy of interface surface testing.

[0092] In the capacitor-voltage test method, after testing the transistor under test, the DC current output by the substrate of the transistor under test is obtained during the test.

[0093] The DC current output from the substrate of the transistor under test during the test can be obtained from the capacitor voltage test equipment.

[0094] After testing the transistor under test using the capacitance-voltage test method, the DC current output from the substrate of the transistor under test is obtained, including:

[0095] After testing the transistor under test according to the capacitance-voltage test method, the output current of the substrate of the transistor under test is sampled; the DC component of the output current is extracted to obtain the DC current.

[0096] The capacitance voltage of the transistor under test can be tested using a capacitance voltage testing device, and the current output from the substrate of the transistor under test can be read and stored during the test.

[0097] When the test voltage includes both constant voltage and AC voltage, the current output from the substrate of the transistor under test includes both DC current and AC current. The DC current in the current output from the substrate can be extracted using a low-pass filter.

[0098] The test equipment used for interface state testing can obtain the current output from the substrate of the transistor under test in the capacitance voltage test equipment and extract the DC current therefrom.

[0099] S202, calculate the integral of the DC current over time in the accumulation region to obtain the injected charge.

[0100] After reading the DC current, the DC current is integrated along the accumulation region to obtain the total charge injected into the transistor under test when interface states exist and the interface states are not saturated. This is denoted as the injected charge.

[0101] The accumulation region can be determined based on the CV characteristic curve of the transistor under test. Specifically, the flat-band voltage is determined based on the CV characteristic curve, and then the time range corresponding to the accumulation region is determined based on the flat-band voltage and the scanning method. Within the time range corresponding to the accumulation region, the integral of DC current with time is calculated to obtain the injected charge.

[0102] S203, extract the oxide layer leakage current that is linearly related to the test voltage from the DC current in the accumulation region, and calculate the integral of the oxide layer leakage current with time to obtain the oxide layer leakage charge.

[0103] The current output from the substrate of the transistor under test during the test includes the displacement current I. C and oxide layer leakage current I E Based on Ohm's law, the oxide layer leakage current I... E The DC current exhibits a linear relationship with the test voltage Vgs. After obtaining the DC current, the portion of the DC current that shows a linear relationship with the test voltage can be extracted, thus yielding the oxide layer leakage current I. E In the accumulation region, calculate the oxide layer leakage current I. E The integral yields the oxide layer leakage current Q. E .

[0104] In some embodiments, the relationship curve between DC current, time, and test voltage can be read, based on the oxide leakage current I. E The linear relationship between the voltage and the test voltage Vgs is used to extract the oxide leakage current I from the curve. E .

[0105] For example, Figure 4A For this disclosure Figure 2 The diagram shown illustrates the relationship between DC current, time, and test voltage in the illustrated embodiment. Figure 4B From Figure 4A I was extracted from the relationship curve shown. E The diagram, combined with Figure 4A and Figure 4B During the voltage-capacitance test of the transistor under test, the relationship between the test voltage Vgs, time t, and DC current I is recorded to obtain the following results: Figure 4A The relationship curve is shown. During interface state testing, the oxide layer leakage current I is used as the basis. E The oxide leakage current I is obtained by intersecting the plane corresponding to the linear relationship between the test voltage Vgs and the curve of this relationship. E The curve showing the relationship between time t and the accumulation region. This allows us to observe the oxide layer leakage current I within the time range corresponding to the accumulation region. E Integrating the data, we obtain the oxide layer leakage current Q. E .

[0106] Steps S202 and S203 can be executed sequentially or in parallel. Step S203 can be executed first, followed by step S202, or vice versa. Figure 2 Take serial execution as an example.

[0107] S204, Based on the injected charge and the oxide layer leakage charge, determine the interface state charge of the transistor under test.

[0108] Based on the law of conservation of charge and the calculated injected charge Q 注入 And oxide layer leakage current Q E Determine the interface state charge Q of the transistor under test. Dit .

[0109] Multiple tests can be performed according to the interface state testing method provided in this embodiment to obtain multiple interface state charges of the transistor under test. Based on the multiple interface state charges corresponding to the transistor under test, an interface state test report for the transistor under test is generated.

[0110] Since the interface state changes during the use of a transistor, the interface state test can be performed on the transistor at multiple discrete time points during the use of the transistor, according to the aforementioned interface state test method, to obtain the interface state charge corresponding to each time point.

[0111] The interface state testing method provided in this embodiment is designed for transistor interface state measurement applications. It eliminates the need for additional test procedures, utilizing traditional capacitor-voltage testing to test the transistor under test. During the test, the DC current output from the transistor substrate is continuously acquired, and interface state measurements are performed based on this DC current and the law of charge conservation. Since the interface state current is generated only in the accumulation region, interface state measurements can be performed based on the changes in the DC current in the accumulation region. Specifically, the DC current is integrated along the accumulation region to obtain the injected charge, and the oxide leakage current (which is linearly related to the test voltage) in the DC current is integrated along the accumulation region to obtain the oxide leakage charge. Based on the law of charge conservation, the injected charge, and the oxide leakage charge, the interface state charge is determined, thus achieving interface state measurement. Because interface state measurement is coupled to the traditional capacitor-voltage testing method, separate interface state testing is unnecessary; interface state measurement can be achieved based on the substrate output current during capacitor-voltage testing, saving test resources and reducing costs. Furthermore, the interface state testing structure is simple, and the test scheme is easy to implement, reducing the difficulty of interface state testing.

[0112] The method further includes:

[0113] If the interface state charge of the transistor under test is higher than the preset charge, then the interface defect prompt information is generated.

[0114] When the interface state charge of the transistor under test is too high, such as exceeding a preset charge, it significantly impacts channel mobility and threshold voltage drift, leading to reduced device performance. A timely warning should be issued if the interface state charge of any test of the transistor under test exceeds the preset charge. This warning can be issued simultaneously by generating interface defect alerts to prevent devices with suboptimal interface states from continuing to be used.

[0115] The method further includes:

[0116] A test report is generated based on the interface state charge of each transistor under test.

[0117] When multiple transistors need to be tested for interface states, after obtaining the interface state charge of each transistor, a test report can be generated based on the interface state charge of each transistor.

[0118] Interface state testing can be performed on the transistor under test at multiple time points, such as N time points, so that each transistor under test corresponds to N interface state charges. Then, based on the transistor under test number, the test time point, and the measured interface state charges, a test report is generated.

[0119] Test reports can be presented in the form of tables, tree diagrams, line graphs, etc.

[0120] The test results are made more intuitive and visual by displaying the interface state charge of the transistor under test through a visual test report.

[0121] Figure 5 This is a flowchart illustrating another interface state testing method provided in this embodiment. Figure 2 Based on the illustrated embodiment, steps S203 and S204 are further refined, and steps related to determining the accumulation region are added before step S202, such as... Figure 5 As shown, the interface state testing method provided in this embodiment may include the following steps:

[0122] S501: After testing the transistor under test in accordance with the capacitor voltage test method, obtain the DC current output by the substrate of the transistor under test.

[0123] After testing the transistor under test using the capacitance-voltage test method, the DC current output from the substrate of the transistor under test is obtained, including:

[0124] After testing the transistor under test according to the capacitor voltage test method, a data file describing the relationship between the DC current, time and test voltage is obtained, and an integration operation is performed based on the data file.

[0125] The data file can be stored in the capacitor voltage test equipment. When the capacitor voltage test equipment performs a capacitor voltage test on the transistor under test, it forms a data file corresponding to the transistor under test based on the time corresponding to the read DC current and the test voltage. This allows the DC current to be integrated along the accumulation region based on the data file to obtain the injected charge, and the corresponding relationship between the test voltage, time and the DC current, such as the relationship curve, can be obtained based on the data file.

[0126] The method further includes:

[0127] Based on the capacitance of the transistor under test read at multiple test voltages, a capacitance-voltage curve of the transistor under test is plotted.

[0128] Since the capacitance-voltage test is performed on the transistor under test, the capacitance-voltage curve of the transistor under test can be plotted based on the capacitance of the transistor under test at each test voltage.

[0129] In some embodiments, the voltage-current curve of the transistor under test can also be plotted based on the current of the transistor under test at each test voltage, such as the current output from the substrate.

[0130] By plotting the capacitor-voltage curve, parameters such as the flat-band voltage and carrier concentration of the transistor can be determined based on the capacitor-voltage curve, so as to have a more comprehensive understanding of the characteristics of the transistor.

[0131] S502, Obtain the capacitance-voltage curve of the transistor under test, wherein the capacitance-voltage curve is used to describe the change in capacitance of the transistor under test under the test voltage.

[0132] The capacitance-voltage curve can be stored in the capacitance-voltage testing equipment. After the capacitance-voltage test is performed, the capacitance-voltage curve of the transistor under test is formed based on the capacitance of the transistor under test at each test voltage.

[0133] The test equipment used for interface state testing obtains the capacitance voltage curve from the capacitance voltage test equipment.

[0134] S503, Based on the capacitor voltage curve, determine the accumulation region.

[0135] Specifically, the flat-band voltage V of the transistor under test can be determined based on the capacitor-voltage curve. FB Based on flat-band voltage V FB And the potential of the test voltage during each scan, to determine the voltage range and time range corresponding to the accumulation region.

[0136] Taking the scanning method from the accumulation region to the inversion region as an example, the voltage during the i-th scan is less than the flat-band voltage V. FB The voltage during the (i+1)th scan is greater than the flat-band voltage V. FB The voltage range corresponding to the accumulation region is from the starting voltage of the scan to the voltage at the i-th scan, and the time range corresponding to the accumulation region is from the time when the starting voltage of the scan is applied to the time when the voltage at the i-th scan is applied.

[0137] Based on the capacitor voltage curve, the accumulation region is determined, including:

[0138] Based on the capacitor voltage curve, the voltage range corresponding to the accumulation region is determined; based on the voltage range corresponding to the accumulation region, and the correspondence between the test voltage, time, and DC current, the time range corresponding to the accumulation region is determined, so as to perform integration operation within the time range corresponding to the accumulation region.

[0139] Specifically, based on the capacitor-voltage curve, the flat-band voltage V of the transistor under test is determined. FBThen, by combining the scanning method of the test voltage, the voltage range corresponding to the accumulation region is determined. Based on this voltage range, and the correspondence between the test voltage, time, and DC current, the time range corresponding to this voltage range is obtained, that is, the time range corresponding to the accumulation region, so as to monitor the DC current and oxide layer leakage current I within this time range. E Perform the points calculation.

[0140] S504, calculate the integral of the DC current over time in the accumulation region to obtain the injected charge.

[0141] S505, the DC current is decomposed to obtain the oxide layer leakage current which is linearly related to the test voltage.

[0142] This step can be performed at any step after step S501 and before step S506. Figure 5 Taking the parallel execution of steps S505 and S504 as an example, in some embodiments, step S505 can also be executed in parallel with step S502.

[0143] Specifically, it can be based on the oxide leakage current I of the transistor under test. E The linear relationship between the voltage and the test voltage allows us to extract the leakage current I of the oxide layer from the DC current. E .

[0144] DC current I includes oxide layer leakage current I E and displacement current I C For an ideal MOSFET, its displacement current I C It is a constant.

[0145] For example, Figure 6 Oxide layer leakage current I provided in one embodiment of this disclosure E and displacement current I C A schematic diagram, such as Figure 6 As shown, the applied test voltage Vgs is plotted on the horizontal axis, and the absolute value of the DC current I output from the substrate is plotted on the vertical axis. The range of the test voltage corresponding to the accumulation region is from the scan start potential to the flat band voltage Vgs. FB The scan start potential is less than 0V. Based on Ohm's law, the oxide layer leakage current I... E Since the current I is linearly related to the test voltage Vgs, the oxide leakage current I, which is also linearly related to the test voltage Vgs, can be decomposed from the DC current I. E The remaining part is a displacement current I. C .

[0146] When the transistor under test is considered an ideal MOSFET, its displacement current I C It is a constant.

[0147] When a negative bias voltage is applied to the gate G, due to the presence of interface states, majority carriers begin to recombine with minority carriers trapped in the interface states, neutralizing the trapped minority carriers and resulting in a displacement current I. C The displacement current I decreases when the majority carriers are completely neutralized and the minority carriers are trapped. C Descending to the lowest point, that is Figure 6 At the location corresponding to the central star. As the gate-source voltage, i.e., the test voltage Vgs, increases, minority carriers and majority carriers separate, and the displacement current I... C Rise. When the test voltage Vgs reaches the flat band voltage V FB When the interface is saturated, the displacement current I... C It recovers to the constant value under ideal conditions and enters the depletion region; when the test voltage Vgs reaches the threshold voltage V... th At that time, it enters the inversion zone.

[0148] After obtaining the relationship curve between DC current I and test voltage Vgs, or the relationship curve between DC current I, test voltage Vgs, and time, the oxide leakage current I is used as the basis for further analysis. E The linear relationship with the test voltage Vgs allows for the decomposition of the oxide layer leakage current I from this DC current. E .

[0149] S506, extract the oxide layer leakage current within the time range corresponding to the accumulation region.

[0150] The time range corresponding to the accumulation zone can be determined by the range of the test voltage corresponding to the accumulation zone.

[0151] Specifically, the time range corresponding to the accumulation zone can be determined based on the time corresponding to each applied test voltage and the range of test voltages corresponding to the accumulation zone.

[0152] S507, calculate the integral of the oxide layer leakage current with time to obtain the oxide layer leakage charge.

[0153] Within the time range corresponding to the accumulation region, calculate the oxide layer leakage current I. E Integrating with time yields the oxide layer leakage current Q. E .

[0154] S508, obtain the ideal injected charge amount of the transistor under test.

[0155] Wherein, the ideal injected charge amount is the injected charge amount of the transistor under test in the accumulation region when the transistor under test is considered to be an ideal transistor.

[0156] This step can be executed at any step before step S509, such as in parallel with step S501, or after step S503.

[0157] Ideal injected charge Qideal The corresponding transistor under test is considered as an ideal device, that is, under the condition of no interface state and no gate dielectric leakage, the amount of charge injected into the transistor under test at the test voltage corresponding to the accumulation region.

[0158] Since the scanning method of the test voltage Vgs is known, the ideal injected charge Q of various types of transistors under test can be calculated in advance. ideal Furthermore, the ideal injected charge Q of the transistor under test can be obtained through simulation. ideal When performing interface state testing on the transistor under test, the pre-stored ideal injected charge Q is directly obtained. ideal .

[0159] Ideal injected charge Q ideal This includes the charge injected into the dielectric layer capacitor and the charge injected into the substrate depletion capacitor. Both the charge injected into the dielectric layer capacitor and the charge injected into the substrate depletion capacitor can be calculated based on the parameters of the transistor under test and the corresponding formulas, thus yielding the ideal injected charge Q. ideal .

[0160] Obtaining the ideal injected charge of the transistor under test includes:

[0161] The ideal injected charge is determined based on the channel doping concentration and gate dielectric thickness of the transistor under test.

[0162] The ideal injected charge Q can be calculated by substituting relevant parameters of the transistor under test, including channel doping concentration and gate dielectric thickness, into the calculation formula. ideal The ideal injected charge Q can also be obtained through simulation. ideal .

[0163] S509, the interface state charge is determined to be the difference between the injected charge amount minus the oxide layer leakage charge amount and the ideal injected charge amount.

[0164] Based on the law of conservation of charge, the following relationship can be obtained: Interface state charge Q Dit =Injected charge Q 注入 -Oxide layer leakage current Q E -Ideal injected charge Q ideal .

[0165] In calculating or obtaining the injected charge Q 注入 Oxide layer leakage current Q E and ideal injected charge Q ideal Then, substituting into the above relationship, we obtain the interface state charge Q. Dit .

[0166] S510, if the interface state charge of the transistor under test is higher than the preset charge, then an interface defect prompt message for the transistor under test is generated.

[0167] In some embodiments, if the interface state charge of the transistor under test is less than or equal to a preset charge, a test pass message for the transistor under test is generated.

[0168] The generated interface defect prompts, test pass messages, test reports, and other content can be sent to the user terminal, such as via email. The user terminal can be the terminal of the user performing the test on the transistor under test, or the terminal of the user using the transistor under test.

[0169] In this embodiment, after performing a CV test on the transistor under test, the injected charge Q is calculated based on the distribution of the DC current output from the substrate in the accumulation region. 注入 And oxide layer leakage current Q E Combined with the pre-calculated ideal injected charge Q ideal Based on the law of conservation of charge, the interface state charge Q is obtained. Dit The testing method is simple and easy to implement, and the measurement of interface state charge based on charge conservation is highly accurate. Determining the accumulation region using CV curves is both efficient and accurate; the injected charge Q is obtained by integrating the DC current and oxide layer leakage current within the accumulation region. 注入 And oxide layer leakage current Q E This improves the accuracy of charge calculation, which in turn improves the accuracy of interface state measurement.

[0170] Corresponding to the above method embodiments, Figure 7 This is a schematic diagram of the structure of an interface state testing device provided in an embodiment of this disclosure. Figure 7 As shown, the interface state testing device includes: a DC current reading module 710, an injected charge calculation module 720, an oxide layer leakage current calculation module 730, and an interface state charge determination module 740.

[0171] The DC current reading module 710 is used to acquire the DC current output by the substrate of the transistor under test after testing it in the manner of capacitor voltage testing; the injected charge calculation module 720 is used to calculate the integral of the DC current in the accumulation region with time to obtain the injected charge; the oxide leakage current calculation module 730 is used to extract the oxide leakage current that is linearly related to the test voltage in the DC current in the accumulation region, and calculate the integral of the oxide leakage current with time to obtain the oxide leakage current; the interface state charge determination module 740 is used to determine the interface state charge of the transistor under test based on the injected charge and the oxide leakage current.

[0172] In some embodiments, the apparatus further includes:

[0173] An ideal charge acquisition module is used to acquire the ideal injected charge of the transistor under test, wherein the ideal injected charge is the injected charge of the transistor under test in the accumulation region when the transistor under test is considered to be an ideal transistor.

[0174] Correspondingly, the interface-state power determination module 740 is specifically used for:

[0175] The interface state charge is determined to be the difference between the injected charge, the oxide layer leakage charge, and the ideal injected charge.

[0176] In some implementations, the ideal charge acquisition module is specifically used for:

[0177] The ideal injected charge is determined based on the channel doping concentration and gate dielectric thickness of the transistor under test.

[0178] In some implementations, the DC current reading module 710 is specifically used for:

[0179] After testing the transistor under test according to the capacitance-voltage test method, the output current of the substrate of the transistor under test is sampled; the DC component of the output current is extracted to obtain the DC current.

[0180] In some implementations, the DC current reading module 710 is specifically used for:

[0181] After testing the transistor under test according to the capacitor voltage test method, a data file describing the relationship between the DC current, time and test voltage is obtained, and an integration operation is performed based on the data file.

[0182] In some embodiments, the apparatus further includes:

[0183] The capacitor-voltage curve acquisition module is used to acquire the capacitor-voltage curve of the transistor under test, which describes the change in capacitance of the transistor under test under a test voltage; the accumulation region determination module is used to determine the accumulation region based on the capacitor-voltage curve.

[0184] In some implementations, the accumulation area determination module is specifically used for:

[0185] Based on the capacitor voltage curve, the voltage range corresponding to the accumulation region is determined; based on the voltage range corresponding to the accumulation region, and the correspondence between the test voltage, time, and DC current, the time range corresponding to the accumulation region is determined, so as to perform integration operation within the time range corresponding to the accumulation region.

[0186] In some embodiments, the oxide layer leakage current calculation module 730 is specifically used for:

[0187] The DC current is decomposed to obtain the oxide layer leakage current, which is linearly related to the test voltage; the oxide layer leakage current within the time range corresponding to the accumulation region is extracted.

[0188] In some embodiments, the apparatus further includes:

[0189] The capacitor-voltage curve plotting module is used to plot the capacitor-voltage curve of the transistor under test based on the capacitance read under multiple test voltages.

[0190] In some embodiments, the apparatus further includes:

[0191] The capacitance voltage test module is used to apply a test voltage to the gate of the transistor under test by means of potential scanning after shorting the source and drain of the transistor under test and grounding the substrate, so as to test the transistor under test in the manner of capacitance voltage test.

[0192] In some implementations, the potential scanning method of the test voltage is either scanning from the accumulation region to the inversion region or scanning from the inversion region to the accumulation region.

[0193] In some embodiments, the apparatus further includes:

[0194] The interface defect prompting module is used to generate interface defect prompting information for the transistor under test if the interface state charge of the transistor under test is higher than a preset charge.

[0195] In some embodiments, the apparatus further includes:

[0196] The test report generation module is used to generate a test report based on the interface state power of each of the transistors under test.

[0197] The above-described apparatus embodiment is an embodiment corresponding to the foregoing method embodiment, and has the same technical effects as the method embodiment. A detailed description of this apparatus embodiment can be found in the detailed description of the foregoing method embodiment, and will not be repeated here.

[0198] This disclosure also provides a test device, including at least one processor and a memory.

[0199] The memory stores computer-executable instructions. The at least one processor executes the computer-executable instructions stored in the memory, causing the test device to implement the above-described interface state test method.

[0200] Figure 8This is a structural block diagram of a test device provided in an embodiment of this disclosure. The test device includes a memory 810 and at least one processor 820.

[0201] Among them, the memory 810 stores computer-executed instructions.

[0202] At least one processor 820 executes computer execution instructions stored in memory 810, causing the test device to implement the interface state test method and / or defect point identification method provided in the foregoing embodiments.

[0203] The memory 810 and the processor 820 are connected via a bus 830.

[0204] Figure 9 This is a schematic diagram of the structure of a testing system provided in an embodiment of the present disclosure, such as... Figure 9 As shown, the test system includes a capacitor voltage test device, an interface state test device, and the transistor under test.

[0205] After forming a test circuit with the transistor under test, the capacitance voltage test equipment applies a test voltage to the transistor under test in the form of potential scanning and collects the current output from the substrate of the transistor under test to test the capacitance voltage characteristics of the transistor under test and obtain the capacitance voltage characteristic curve.

[0206] The interface state test equipment is connected to the capacitance voltage test equipment. It is used to acquire the current output from the substrate of the transistor under test, such as DC current, collected by the capacitance voltage test equipment. It is also used to acquire the capacitance voltage characteristic curve of the transistor under test generated by the capacitance voltage test equipment.

[0207] The interface state testing equipment is used to perform the interface state testing method provided in any embodiment of this disclosure to measure the interface state charge of the transistor under test.

[0208] Interface state testing equipment can provide Figure 8 The test equipment in the corresponding embodiment.

[0209] The capacitor voltage testing equipment can be a capacitor voltage characteristic tester.

[0210] In some embodiments, the capacitance voltage testing device includes a host computer and a signal source. The signal source includes a pulse generator and a constant potentiometer. The constant potentiometer is used to output a constant potential for a period of time under the control of the host computer, and the pulse generator is used to output a pulse signal under the control of the host computer.

[0211] This disclosure also provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, cause the processor to implement the method provided in any embodiment of this disclosure.

[0212] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the methods provided in any embodiment of this disclosure.

[0213] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0214] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0215] The above are merely preferred embodiments of the present disclosure and do not limit the patent scope of the present disclosure. Any equivalent structural or procedural transformations made based on the description and drawings of the present disclosure, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present disclosure.

Claims

1. A method for testing interface states, characterized in that, include: After testing the transistor under test according to the capacitor voltage test method, the DC current output by the substrate of the transistor under test is obtained; The amount of injected charge is obtained by calculating the integral of the DC current over time in the accumulation region; Extract the oxide layer leakage current that is linearly related to the test voltage from the DC current in the accumulation region, and calculate the integral of the oxide layer leakage current with time to obtain the oxide layer leakage charge. Based on the injected charge and the oxide layer leakage charge, the interface state charge of the transistor under test is determined; Obtain the ideal injected charge of the transistor under test, wherein the ideal injected charge is the injected charge of the transistor under test in the accumulation region when the transistor under test is considered to be an ideal transistor; The step of determining the interface state charge of the transistor under test based on the injected charge and the oxide layer leakage charge includes: The interface state charge is determined to be the difference between the injected charge, the oxide layer leakage charge, and the ideal injected charge.

2. The method according to claim 1, characterized in that, Obtaining the ideal injected charge of the transistor under test includes: The ideal injected charge is determined based on the channel doping concentration and gate dielectric thickness of the transistor under test.

3. The method according to claim 1, characterized in that, After testing the transistor under test using the capacitance-voltage test method, the DC current output from the substrate of the transistor under test is obtained, including: After testing the transistor under test according to the capacitance voltage test method, the output current of the substrate of the transistor under test is sampled; The DC component of the output current is extracted to obtain the DC current.

4. The method according to claim 1, characterized in that, After testing the transistor under test using the capacitance-voltage test method, the DC current output from the substrate of the transistor under test is obtained, including: After testing the transistor under test according to the capacitor voltage test method, a data file describing the relationship between the DC current, time and test voltage is obtained, and an integration operation is performed based on the data file.

5. The method according to claim 1, characterized in that, The method further includes: Based on the capacitance of the transistor under test read under multiple test voltages, plot the capacitance-voltage curve of the transistor under test; The accumulation region is determined based on the capacitor voltage curve.

6. The method according to claim 5, characterized in that, Based on the capacitor voltage curve, the accumulation region is determined, including: Based on the capacitor voltage curve, determine the voltage range corresponding to the accumulation region; Based on the voltage range corresponding to the accumulation zone, and the correspondence between the test voltage, time, and DC current, the time range corresponding to the accumulation zone is determined so that integration can be performed within the time range corresponding to the accumulation zone.

7. The method according to claim 5, characterized in that, Extracting the oxide leakage current from the DC current located in the accumulation region that is linearly related to the test voltage includes: The DC current is decomposed to obtain the oxide layer leakage current, which is linearly related to the test voltage; Extract the oxide layer leakage current within the time range corresponding to the accumulation region.

8. The method according to any one of claims 1-7, characterized in that, The method further includes: After shorting the source and drain of the transistor under test and grounding the substrate, a test voltage is applied to the gate of the transistor under test in a potential scanning manner to test the transistor under test in the manner of capacitance voltage test; wherein, the potential scanning method of the test voltage is scanning from the accumulation region to the inversion region, or scanning from the inversion region to the accumulation region.

9. An interface state testing device, characterized in that, include: A DC current reading module is used to acquire the DC current output from the substrate of the transistor under test after testing the transistor under test in the manner of capacitor voltage testing. The injected charge calculation module is used to calculate the integral of the DC current over time in the accumulation region to obtain the injected charge. The oxide layer leakage current calculation module is used to extract the oxide layer leakage current that is linearly related to the test voltage in the DC current of the accumulation area, and calculate the integral of the oxide layer leakage current with time to obtain the oxide layer leakage current. An interface state charge determination module is used to determine the interface state charge of the transistor under test based on the injected charge and the oxide layer leakage charge. An ideal charge acquisition module is used to acquire the ideal injected charge of the transistor under test, wherein the ideal injected charge is the injected charge of the transistor under test in the accumulation region when the transistor under test is considered to be an ideal transistor. The interface state charge determination module is used to determine the interface state charge of the transistor under test based on the injected charge and the oxide layer leakage charge, including: The interface state charge is determined to be the difference between the injected charge, the oxide layer leakage charge, and the ideal injected charge.

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