Current mirror circuit

Abstract

A circuit includes a first transistor having a first terminal, a second terminal, and a third terminal, and a second transistor having a first terminal, a second terminal, and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of a distance between the first transistor and the second transistor.

Description

Background Technology

[0001] Current mirror circuits are commonly used in semiconductor integrated circuits, such as semiconductor memories. They are widely used to replicate a reference current used in various circuits. A common application is providing bias current for operational amplifiers. A current mirror circuit typically includes a first transistor (sometimes called a "driver device") that conducts a known reference current and generates a bias voltage, which is applied to a second transistor (sometimes called a "mirror device") that conducts the "mirror current." By adjusting the ratio of the size of the driver device to the size of the mirror device, the resulting mirror current can be made proportional to the reference current.

[0002] In some cases, the distance between the driving device and the mirror device can be significant. If the driving device and the mirror device share a common power bus, the parasitic resistance in the power bus can cause errors in the resulting mirror current. Attached Figure Description

[0003] Components with similar numbers refer to common parts in different drawings.

[0004] Figure 1 It is a block diagram depicting one implementation of a memory system.

[0005] Figure 2 This is a block diagram of one implementation scheme for a memory die.

[0006] Figure 3 This is a perspective view of one implementation of a three-dimensional memory structure.

[0007] Figure 4A This is a diagram of a conventional current mirror circuit.

[0008] Figure 4B This is a diagram of another conventional current mirror circuit.

[0009] Figure 5A This is a diagram of one implementation scheme of a current mirror circuit.

[0010] Figure 5B This is a diagram of another implementation of the current mirror circuit.

[0011] Figure 6 This is a diagram of one implementation scheme for a memory die. Detailed Implementation

[0012] This invention describes a technique for using a current mirror circuit to generate mirrored currents in semiconductor integrated circuits, such as semiconductor memories.

[0013] Semiconductor memories can include non-volatile or volatile memories. Non-volatile memories allow information to be stored and retained even when not connected to a power source (e.g., a battery). Examples of non-volatile memories include flash memory (e.g., NAND and NOR flash memory).

[0014] In semiconductor memories, current mirror circuits are typically used to generate current to read and write selected memory cells. Semiconductor memories usually consist of memory arrays divided into subarrays; some memory chips have thousands of subarrays, each with its own read and write circuitry and current mirror devices.

[0015] In many implementations, the reference current generator and the current mirror driver are located outside the memory array. The driver generates a bias voltage that is distributed to the mirror device in each memory subarray. This results in a large and variable distance between the driver and the multiple mirror devices. If the driver and mirror devices share a common power bus, voltage differences along the power bus due to parasitic resistance in the power bus can cause errors in the resulting mirror currents.

[0016] Therefore, the current generated by mirrored devices in various memory subarrays can have unacceptably large errors compared to the desired current value. This invention describes a technique for providing a current mirror circuit that generates a mirrored current proportional to a reference current, substantially independent of the voltage difference along the power bus between the driver device and the mirrored device. Furthermore, the described current mirror circuit generates a mirrored current proportional to a reference current, substantially independent of the distance between the driver device and the mirrored device.

[0017] Figure 1 This is a block diagram of one embodiment of the memory system 100 implementing the described technology. In one embodiment, the memory system 100 is an SSD. The memory system 100 may also be a memory card, a USB drive, or other type of memory system. The technology of the present invention is not limited to any one type of memory system. The memory system 100 is connected to a host 102, which may be a computer, server, electronic device (e.g., a smartphone, tablet, or other mobile device), appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from but connected to the memory system 100. In other embodiments, the memory system 100 is embedded within the host 102.

[0018] Figure 1The components of the memory system 100 depicted are electronic circuits. The memory system 100 includes a controller 104 connected to one or more memory dies 106 and local high-speed volatile memory 108 (e.g., DRAM). Each of the one or more memory dies 106 includes a plurality of non-volatile memory cells. More information regarding the structure of each memory die 106 is provided below. The controller 104 uses the local high-speed volatile memory 108 to perform certain functions.

[0019] Controller 104 includes a host interface 110 that connects to and communicates with host 102. In one embodiment, host interface 110 provides a PCIe interface. Other interfaces, such as SCSI, SATA, etc., may also be used. Host interface 110 also connects to a network on-chip (NOC) 112, which is a communication subsystem on an integrated circuit. In other embodiments, NOC 112 may be replaced by a bus. Processor 114, ECC engine 116, memory interface 118, DRAM controller 120, and hardware accelerator 122 connect to and communicate with NOC 112.

[0020] Processor 114 performs various controller memory operations, such as programming, erasing, reading, and memory management procedures. In one embodiment, processor 114 is programmed by firmware. In other embodiments, processor 114 is a custom-designed dedicated hardware circuit without any software. In one embodiment, processor 114 may also implement a conversion module as a software / firmware process or as dedicated hardware circuitry.

[0021] In one implementation, ECC engine 116 performs error correction. For example, ECC engine 116 performs data encoding and decoding according to implemented ECC technology. In one implementation, ECC engine 116 is a software-programmable electronic circuit. For example, ECC engine 116 may be a programmable processor. In other implementations, ECC engine 116 is a custom-designed dedicated hardware circuit without any software. In yet another implementation, the functionality of ECC engine 116 is implemented by processor 114.

[0022] In one embodiment, memory interface 118 communicates with one or more memory dies 106. In one embodiment, memory interface 118 provides a mode-switching interface. Other interfaces may also be used. In some exemplary embodiments, memory interface 118 (or another part of controller 104) implements a scheduler and buffer for transferring data to and receiving data from one or more memory dies.

[0023] In one embodiment, the DRAM controller 120 is used to operate and communicate with a local high-speed volatile memory 108 (e.g., DRAM). In other embodiments, the local high-speed volatile memory 108 may be SRAM or another type of volatile memory.

[0024] Figure 2 This is a functional block diagram of one implementation scheme of the memory die 200. Figure 1 Each of the one or more memory dies 106 can be implemented as Figure 2 The memory die 200. Figure 2 The components depicted are electronic circuits. In one embodiment, each memory die 200 includes a memory structure 202, control circuitry 204, and read / write circuitry 206. The memory structure 202 is addressable by word lines via a row decoder 208 and by bit lines via a column decoder 210.

[0025] In one embodiment, the read / write circuitry 206 includes a plurality of sensing blocks 212 (including SB1, SB2, ..., SBp (sensing circuitry)) and allows one or more data pages of a plurality of memory cells to be read or programmed (written) in parallel. In one embodiment, each sensing block 212 includes a sensing amplifier and a set of latches connected to a bit line. The latches store data to be written and / or data already read. In one embodiment, the sensing amplifier of each sensing block 212 includes a bit line driver. In one embodiment, commands and data are transmitted between the controller 104 and the memory die 200 via line 214. In one embodiment, the memory die 200 includes a set of input and / or output (I / O) pins connected to line 214.

[0026] In one embodiment, control circuitry 204 cooperates with read / write circuitry 206 to perform memory operations (e.g., write, read, erase, etc.) on memory structure 202. In one embodiment, control circuitry 204 includes state machine 216, on-chip address decoder 218, and power control module 220.

[0027] In one embodiment, state machine 216 provides die-level control of memory operations. In one embodiment, state machine 216 may be software-programmable. In other embodiments, state machine 216 does not use software and is implemented entirely in hardware (e.g., electronic circuitry). In some embodiments, state machine 216 may be replaced by a microcontroller or microprocessor. In one embodiment, control circuitry 204 includes buffers such as registers, ROM fuses, and other storage devices for storing default values ​​(such as base voltage and other parameters).

[0028] The on-chip address decoder 218 provides an address interface between the addresses used by the controller 104 and the hardware addresses used by the row decoder 208 and column decoder 210. The power control module 220 controls the power and voltage supplied to the word lines and bit lines during memory operations. The power control module 220 may include a charge pump for generating voltage.

[0029] The power control module 220 may also include a current mirror drive circuit for generating a current mirror bias voltage to be supplied to other circuits on the memory die 200. For example, the power control module 220 may include a current mirror drive circuit that provides a current mirror bias voltage to one or more of the current mirror devices in the memory structure 202, control circuit 204, read / write circuit 206, row decoder 208, column decoder 210, sensing block 212, and / or other circuits on the memory die 200.

[0030] For the purposes of this document, control circuitry 204, read / write circuitry 206, row decoder 208, and column decoder 210 include control circuitry for memory structure 202. In other embodiments, other circuitry that supports and operates on memory structure 202 may be referred to as control circuitry. For example, in some embodiments, controller 104 may operate as control circuitry or may be part of control circuitry. Control circuitry may also be implemented as a microprocessor or other types of processors that are hardwired or programmed to perform the functions described herein.

[0031] In one embodiment, memory structure 202 is a three-dimensional memory array of non-volatile memory cells. In another embodiment, memory structure 202 is a monolithic three-dimensional memory array in which multiple memory stages are formed over a single substrate, such as a wafer. Memory structure 202 can be any type of non-volatile memory formed in one or more physical stages of an array of memory cells having active regions disposed over a silicon (or other type of) substrate. In one example, the non-volatile memory cells of memory structure 202 include vertical NAND strings having a charge-trapping material such as described above. The NAND strings include memory cells connected by channels.

[0032] In another embodiment, memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR flash memory) may also be used.

[0033] In another embodiment, memory structure 202 includes a memory array (two-dimensional or three-dimensional) comprising a plurality of memory subarrays, wherein each memory subarray comprises a plurality of non-volatile memory cells.

[0034] The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples above. Many different types of memory array architecture or memory cell technologies can be used to form memory structure 202. For the purposes of the new techniques described herein, no specific non-volatile memory technology is required.

[0035] Other examples of suitable technologies for the memory cells of memory structure 202 include ReRAM memory, magnetoresistive memory (MRAM), phase-change memory (PCM), etc. Examples of suitable technologies for the architecture of memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bitline arrays, etc.

[0036] One example of a crosspoint memory includes reversible resistor switching elements arranged in a crosspoint array accessed by X-line and Y-line (e.g., word line and bit line). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell.

[0037] Based on the physical repositioning of ions within a solid electrolyte, a conductive bridge memory element can be used as a state-changing element. In some cases, a conductive bridge memory element may comprise two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes.

[0038] MRAM uses magnetic storage elements to store data. A magnetic storage element is formed of two ferromagnetic plates separated by a thin insulating layer, each plate remaining magnetized. One of the plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of an external magnetic field to store memory. Memory devices are constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below. When current passes through them, an induced magnetic field is generated.

[0039] Phase-change memories (PCMs) utilize the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase transition by simply changing the coordination state of germanium atoms with a laser pulse (or a light pulse from another source). Therefore, the programming dose is the laser pulse. Programming of the memory cells can be suppressed by preventing them from receiving light.

[0040] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, but encompass many related memory structures within the scope of the techniques described herein and as understood by those skilled in the art.

[0041] Figure 3 This is a perspective view as part of one embodiment of a three-dimensional memory array including memory structure 202. In one embodiment, memory structure 202 includes a plurality of non-volatile memory cells. For example, Figure 3 A portion of a block of memory cells is shown. The depicted structure includes a set of bit lines BL, which lie above an alternating stack of dielectric and conductive layers. For example, one of the dielectric layers is labeled D, and one of the conductive layers (also called word line layers) is labeled W.

[0042] The number of alternating dielectric and conductive layers can vary depending on specific implementation requirements. One set of embodiments includes 10⁸-300 alternating dielectric and conductive layers. An exemplary embodiment includes 96 data word line layers, 8 select layers, 6 dummy word line layers, and 110 dielectric layers. More or fewer than 10⁸-300 layers may also be used. In one embodiment, the alternating dielectric and conductive layers are divided into four regions by local interconnects L1. Figure 3 Two regions and two local interconnects LI are shown.

[0043] The source line layer SL lies beneath alternating dielectric and word line layers. Memory vias are formed within this stack of alternating dielectric and conductive layers. For example, a memory via is labeled MH. Note that in... Figure 3 In the diagram, the dielectric layers are depicted as a perspective view, allowing the reader to see the memory holes positioned within the stack of alternating dielectric and conductive layers.

[0044] In one embodiment, a NAND string is formed by filling memory holes with a material including a charge-trapping material to create a vertical column (also called a memory column) of memory cells. In one embodiment, each memory cell may store one or more data bits. In one embodiment, each memory hole MH is associated with and coupled to a corresponding bit line BL. In one embodiment, each bit line BL is coupled to one or more memory holes MH.

[0045] Figure 4AA diagram depicts a conventional current mirror circuit 400a, which has an input terminal in1, an output terminal out1, a first transistor M1, and a second transistor M2. In the depicted example, the first transistor M1 and the second transistor M2 are each n-channel transistors. The first transistor M1 has a first (e.g., drain) terminal d1, a second (e.g., source) terminal s1, and a third (e.g., control or gate) terminal g1. The second transistor M2 has a first (e.g., drain) terminal d2, a second (e.g., source) terminal s2, and a third (e.g., control or gate) terminal g2.

[0046] For convenience, the first terminal d1, the second terminal s1, and the third terminal g1 of the first transistor M1 will be referred to herein as the drain d1, the source s1, and the gate g1 of the first transistor M1, respectively. Similarly, the first terminal d2, the second terminal s2, and the third terminal g2 of the second transistor M2 will be referred to herein as the drain d2, the source s2, and the gate g2 of the second transistor M2, respectively.

[0047] The drain d1 of the first transistor M1 is coupled to the input terminal in1, the gate g1 of the first transistor M1, and the gate g2 of the second transistor M2. The drain d2 of the second transistor M2 is coupled to the output terminal out1. The sources s1 of the first transistor M1 and s2 of the second transistor M2 are both coupled to a first power supply (e.g., GND). The input terminal in1 receives the input reference current I. REF This is described here as an ideal current source coupled to a second power source (e.g., VDD). Figure 4A The first transistor M1, with its drain d1 and gate g1 coupled together as shown, is typically referred to as a diode-connected transistor.

[0048] During operation, the reference current I REF A current flows through a diode connected to the first transistor M1. The drain d1 and gate g1 of the first transistor M1 are at the same voltage V. gs1 That is, the gate-source voltage V of the first transistor M1 gs1 The conductor that couples the gate g1 of the first transistor M1 to the gate g2 of the second transistor M2 is in... Figure 4A This is labeled B1. No current flows through conductor B1, therefore the gate g2 of the second transistor M2 is also at voltage V. gs1 Therefore, the gate-source voltage V of the second transistor M2 gs2 Equal to the gate-source voltage V of the first transistor M1 gs1 :

[0049] V gs2 =V gs1 (1)

[0050] If the first transistor M1 and the second transistor M2 have the same dimensions and the same gate-source voltage, then the conduction current of the second transistor M2 is equal to the (first-order) reference current I. REF Output current I M :

[0051] I M =I REF (2)

[0052] In this respect, the output current I M "Mirror" reference current I REF And in this paper it is also referred to as the mirror current I. M Therefore, the first transistor M1 is sometimes referred to as the "driving device," and the second transistor M2 is sometimes referred to as the "mirror device," and these terms will also be used in the remainder of the discussion.

[0053] By making the size of the mirror device M2 proportional to the size of the driving device M1, the output current I can be increased. M With reference current I REF Proportional. For example, if the driving device M1 has a width W1 and a length L, and the mirror device M2 has a width W2 and the same length L, then the output current I... M It can be represented as follows:

[0054]

[0055] For example, if W2 = W1, then I M =I REF Or, if W2 = 2W1, then I M =2I REF And so on.

[0056] In order to convert the mirror current I M Multiple circuits are replicated on the integrated circuit die. Bus B1 can be routed across the entire die to multiple instances of the mirror device M2. Each instance has a gate g2 coupled to bus B1 and a source s2 coupled to GND, and each instance is scaled as needed to provide a reference current I. REF A proportional mirror current. Since virtually no current flows through bus B1, the voltage on bus B1 remains essentially constant at V throughout the die. gs1 .

[0057] If the driving device M1 and the specific mirror device M2 are positioned close to each other, the current mirror circuit 400a performs well, and the mirrored current I... M With reference current I REFClose matching. However, if the driving device M1 and the specific mirror device M2 are not positioned close to each other, the ability to match the current may be compromised.

[0058] For example, a driving device M1 may be located in a driving circuit situated within a portion of an integrated circuit die (e.g., a memory die), and a particular mirror device M2 may be positioned relatively away from the driving device M1 (e.g., in a memory subarray relatively away from the driving circuit).

[0059] Figure 4B It depicts such a scene. Specifically, Figure 4B A diagram depicts the current mirror circuit 400b, which is similar to... Figure 4A The current mirror circuit 400a. However, in this embodiment, the driving device M1 drives multiple mirror devices M. 21 M 22 ... M 2n These mirror devices all share a common power bus (e.g., ground bus GB). Each mirror device M 21 M 22 ... M 2n Each has a corresponding source s that is coupled to the ground bus GB. 21 s 22 ... s 2n and the corresponding gates g coupled to bus B1 respectively. 21 g 22 ... g 2n And each provides its corresponding mirror current I. M1 I M2 ... I Mn .

[0060] In one implementation, each mirror device M 21 M 22 ... M 2n Located at different distances from the driving device M1. For example, a memory die typically includes a large number of memory subarrays, each located at a different distance from the driving circuit, and each memory subarray includes a corresponding mirror device (e.g., mirror device M). 21 M 22 ... M 2n (The corresponding one in the middle).

[0061] In such an implementation, some mirror devices (e.g., M) 21 The image is located near the driving device M1, while other mirrored devices (e.g., M1, M2, M3, M4, M5, M6, M7, M8, M9, M1, M1, M9, M1, M1, M2, M3, M4 ... 2n The source s2 of the driving device M1 is located relatively far from the driving device M1. Therefore, the source s2 of the driving device M1 is connected to each mirror device M1. 21M 22 ... M 2n The source of s 21 s 22 ... s 2n The resistors R1, R2, ..., R in the ground bus GB between them n This can be significant, especially for mirrored devices positioned at a relatively large distance from the driving device M1 (e.g., M). 2n As far as ) is concerned.

[0062] As mentioned above, the voltage of bus B1 is kept essentially constant at V through the die. gs1 However, as ground bus GB resistors R1, R2, ..., R n As a result, the driving device M1 and each mirror device M 21 M 22 ... M 2n The gate-source voltages are no longer equal. For example, V gs2n It can be represented as:

[0063] V gs2n =V gs1 –(I STRAY R T +I M1 R1+I M2 (R2+R1)+...+I Mn R T (4)

[0064] Where I Mn For mirror device M 2n The mirror current, I STRAY This represents any unrelated current flowing in the ground bus GB, and R T For the source s1 of the driving device M1 and the mirror device M 2n The source of s 2n The total resistance in the ground bus GB between them. For example, R T =R1+R2+...R n .

[0065] Therefore, V gs2n Less than V gs1 And in some cases V gs2n With V gs1 The difference between them can be approximately 100mV-200mV or greater. Therefore, the mirror current I... Mn Mismatched reference current I REF :

[0066] I Mn ≠I REF (5)

[0067] In fact, in some cases, the resulting mirror current I Mn The error in this process can be tens of percent. This level of error is unacceptable for many integrated circuit applications, such as memory circuit applications.

[0068] Furthermore, since the source s1 of the driving device M1 is connected to the corresponding mirror device M1, respectively 21 M 22 ... M 2n The source of s 21 s 22 ... s 2n The total ground bus resistor R between T They will be different from each other, and therefore the supposedly "matched" mirror currents I M1 I M2 ... I Mn Based on the driver device M1, each mirror device M will be connected to it. 21 M 22 ... M 2n The distances between them vary, which is unacceptable in many cases, such as in memory circuit applications.

[0069] This invention describes a technique for a current mirror circuit that can reduce the effect of power bus (e.g., GND, VDD, VSS or other similar power bus) resistance on the output current of the current mirror. Figure 5A This is an implementation of a current mirror circuit 500a, which has an input terminal in 1a Output terminal OUT 1a First transistor M 1a Second transistor M 2a Third transistor M 3a and the fourth transistor M 4a In the depicted example, the first transistor M 1a Second transistor M 2a Each is of the first polarity type (e.g., an n-channel transistor), and the third transistor M 3a and the fourth transistor M 4a Each is a second polarity type, different from the first polarity type (e.g., p-channel transistor).

[0070] First transistor M 1a Having a first (e.g., drain) terminal d 1a Second (e.g., source) terminal s 1a and the third (e.g., control or gate) terminal g 1a The second transistor M 2a Having a first (e.g., drain) terminal d 2aSecond (e.g., source) terminal s 2a and the third (e.g., control or gate) terminal g 2a The third transistor M 3a Having a first (e.g., drain) terminal d 3a Second (e.g., source) terminal s 3a and the third (e.g., control or gate) terminal g 3a The fourth transistor M 4a Having a first (e.g., drain) terminal d 4a Second (e.g., source) terminal s 4a and the third (e.g., control or gate) terminal g 4a .

[0071] For convenience, the first transistor M 1a First terminal d 1a Second terminal s 1a and the third terminal g 1a In this paper, they will also be referred to as the first transistor M. 1a drain d 1a 、Source poles s 1a and gate g 1a Similarly, the second transistor M 2a First terminal d 2a Second terminal s 2a and the third terminal g 2a In this paper, they will also be referred to as the second transistor M. 2a drain d 2a 、Source poles s 2a and gate g 2a Similarly, the third transistor M 3a First terminal d 3a Second terminal s 3a and the third terminal g 3a In this article, they will also be referred to as the third transistor M. 3a drain d 3a 、Source poles s 3a and gate g 3a Additionally, the fourth transistor M 4a First terminal d 4a Second terminal s 4a and the third terminal g 4a In this paper, the drain d4, source s4, and gate g4 of the fourth transistor M4 will be referred to as such, respectively.

[0072] First transistor M 1a drain d 1a Coupled to input terminal in 1a First transistor M 1a gate g 1aSecond transistor M 2a gate g 2a The second transistor M 2a drain d 2a Coupled to the output terminal out 1a .like Figure 5A The drain d configured as shown 1a and gate g 1a The first transistor M coupled together 1a This is commonly referred to as a diode-connected transistor.

[0073] Third transistor M 3a drain d 3a Coupled to the first power bus (e.g., ground bus GB), the third transistor M 3a gate g 3a and the fourth transistor M 4a gate g 4a The fourth transistor M 4a drain d 4a Coupled to the ground bus GB. For example... Figure 5A The drain d configured as shown 3a and gate g 3a The third transistor M is coupled together 3a This is commonly referred to as a diode-connected transistor. The resistance in the ground bus GB is represented as R. g In one implementation, the third transistor M 3a drain d 3a Coupled to the first position of the ground bus GB, and the fourth transistor M 4a drain d 4a It is coupled to a second position that is different from the first position of the ground bus GB.

[0074] First transistor M 1a The source of s 1a Coupled to the third transistor M 3a The source of s 3a And the second transistor M 2a The source of s 2a Coupled to the fourth transistor M 4a The source of s 4a Input terminal in 1a Receive input reference current I REF Here it is depicted as an ideal current source coupled to a second power source (e.g., VDD).

[0075] During operation, the reference current I REF The current flows through the diode connected to the first transistor M 1a The third transistor M is connected to the diode. 3a The third transistor M 3adrain d 3a and gate g 3a At the same voltage V g3a .exist Figure 5A In the implementation scheme, the third transistor M 3a drain d 3a and gate g 3a Coupled to the ground bus GB, therefore the voltage V g3a In GND (e.g., V) g3a =0V).

[0076] The third transistor M 3a gate g 3a Coupled to the fourth transistor M 4a gate g 4a The conductor in Figure 5A The Chinese character is marked as GB. Q Conductors GB Q Also referred to in this document as "silent ground bus" GB Q No current flows through the silent ground bus GB. Q Therefore, the fourth transistor M 4a gate g 4a In relation to the third transistor M 3a gate g 3a Voltage V at point g3a Basically the same voltage V g4a .exist Figure 5A In the implementation scheme, voltage V g4a In GND (e.g., V) g4a =0V).

[0077] Third transistor M 3a The source of s 3a At voltage V s3a This voltage can be expressed as:

[0078] V s3a =V ON3 +|V tp | (6)

[0079] Where V ON3 For the third transistor M 3a The on-state voltage, and V tp M is the third p-channel transistor 3a The threshold voltage. First transistor M 1a The source of s 1a At voltage V s1a And coupled to the third transistor M 3a The source of s 3a Therefore, the voltage V s1a Equal to voltage V s3a :

[0080] V s1a =V s3a (7)

[0081] As described above, the third transistor M 3a gate g 3a and the fourth transistor M 4a gate g 4a At essentially the same voltage V g3a Since the source voltage of a MOS transistor in saturation is a very weak function of the drain voltage, the fourth transistor M... 4a The source of s 4a In relation to the third transistor M 3a The source of s 3a Voltage V at point s3a Basically the same voltage V s4a :

[0082] V s4a ≈V s3a (8)

[0083] Not wishing to be bound by any particular theory, it is believed that even due to the ground bus GB resistor R g The fourth transistor M is caused by the voltage drop across its terminals. 4a drain d 4a With the third transistor M 3a drain d 3a The voltage difference of several hundred millivolts between them causes the source voltage V to... s3a and V s4a The very small difference is mainly due to the third transistor M. 3a and the fourth transistor M 4a Works in the saturation region.

[0084] Second transistor M 2a The source of s 2a At voltage V s2a And coupled to the fourth transistor M 4a The source of s 4a Therefore, the second transistor M 2a The source of s 2a Voltage V at point s2a Equal to the fourth transistor M 4a The source of s 4a Voltage V at point s4a :

[0085] V s2a =V s4a (9)

[0086] Therefore, according to formulas (7)–(9), the second transistor M2a The source of s 2a and the first transistor M 1a The source of s 1a At essentially the same voltage:

[0087] V s2a ≈V s1a (10)

[0088] In one implementation, although in the third transistor M 3a drain d 3a With the fourth transistor M 4a drain d 4a There is a voltage drop in the ground bus GB between them, but V s2a With V s1a The absolute value of the difference between them is less than about 5%. In another implementation, although in the third transistor M 3a drain d 3a With the fourth transistor M 4a drain d 4a There is a voltage drop in the ground bus GB between them, but V s2a With V s1a The absolute value of the difference between them is less than about 2%. In yet another implementation, although in the third transistor M 3a drain d 3a With the fourth transistor M 4a drain d 4a There is a voltage drop in the ground bus GB between them, but V s2a With V s1a The absolute value of the difference between them is less than approximately 1%.

[0089] The gate g of the first transistor 1a At voltage V g1a This voltage can be expressed as:

[0090] V g1a =V ON1 +V tn +V s3a (11)

[0091] Where V ON1 For the first transistor M 1a The on-state voltage, and V tn M is the first n-channel transistor. 1a The threshold voltage. Substituting formula (6) into formula (11), the voltage V g1a It can be represented as:

[0092] V g1a =V ON1 +V tn +V ON3+|V tp | (12)

[0093] The first transistor M 1a gate g 1a Coupled to the second transistor M 2a gate g 2a The conductor in Figure 5A The middle is marked as B a No current flows through conductor B. a Therefore, the second transistor M 2a gate g 2a Also at voltage V g1a Therefore, the first transistor M 1a Gate-source voltage V gs1a Basically equal to the second transistor M 2a Gate-source voltage V gs2a :

[0094] V gs1a =V gs2a (13)

[0095] Therefore, if the first transistor M 1a Second transistor M 2a If they have the same dimensions, then the second transistor M 2a The conduction current is essentially equal to the reference current I. REF Output current I Mn :

[0096] I Mn =I REF (14)

[0097] In this respect, the output current I Mn "Mirror" reference current I REF And in this paper it is also referred to as the mirror current I. Mn .

[0098] Following the above text about Figure 4A Similar terms to those used in the current mirror circuit 400a. Figure 5A The first transistor M of the 500A current mirror circuit 1a Second transistor M 2a Third transistor M 3a and the fourth transistor M 4a In this paper, they are also referred to as "the first driving device M". 1a "First mirror device M" 2a "Second driving device M" 3a "and the second mirror device M" 4a ".

[0099] By respectively making the first mirror device M 2a Second mirror device M 4a The size relative to the first driving device M 1a Second driving device M 3a The size is proportional, which can make the output current I... Mn With reference current I REF Proportional.

[0100] For example, if the first driving device M 1a The first mirror device M has a width W1 and a length L. 2a With a width W2 and a length L, the second driving device M 3a It has a width W3 and a length L, and a second mirror device M. 4a It has a width W4 and a length L, and if W2 / W1 = W4 / W3, then the output current I... Mn It can be represented as follows:

[0101]

[0102] For example, if W2 = W1, then I Mn =I REF Alternatively, if W2 = 2W1, then I Mn =2×I REF And so on.

[0103] In order to convert the mirror current I Mn Multiple circuits copied onto the integrated circuit die, bus B a and silent ground bus GB Q The first mirror device M can be inserted throughout the entire die. 2a Second mirror device M 4a Multiple instances, which are scaled as needed to provide current I REF A proportional mirror current. Since virtually no current flows through bus B. a Therefore, bus B a The voltage on the die remains essentially constant at V throughout the die. g1a In this respect, the first driving device M 1a On bus B a The first bias voltage V is provided. g1a Similarly, since virtually no current flows through the silent ground bus GB Q Therefore, the silent ground bus GB Q The voltage on the die remains essentially constant at V throughout the die. g3a In this respect, the second drive device M 3a In silent grounding bus GB Q Provides a different bias voltage V than the first bias voltage.g1a The second bias voltage V g3a .

[0104] Therefore, it is not desirable to be bound by any particular theory, as it is believed that despite the resistance R in the ground bus GB g This leads to the second mirror device M in the entire die. 4a Drain d on all instances 4a Voltage changes at the location, but the first mirror device M 2a The gate-source voltage will be substantially the same across the entire die in all instances (for a 1:1 mirror device), therefore, all mirror currents Id will be the same. Mn It will be substantially the same throughout the die (for a 1:1 scale mirror device), while with the first driver M 1a and the first mirror device M 2a The voltage difference along the power bus between them is irrelevant.

[0105] Furthermore, it is not desired to be bound by any particular theory, it is believed that although due to the resistance R in the ground bus GB g This leads to the second mirror device M in the entire die. 4a Drain d on all instances 4a Voltage changes at the location, but the first mirror device M 2a In this example, the gate-source voltage will be essentially the same across the entire die (for a 1:1 mirror device), therefore, all mirror currents I... Mn It will be substantially the same throughout the die (for a 1:1 scale mirror device), while with the first driver M 1a and the first mirror device M 2a The distance between them is irrelevant.

[0106] although Figure 5A An exemplary current mirror circuit 500a is configured with a second driver M coupled to the ground bus GB. 3a drain d 3a Second mirror device M 4a drain d 4a However, if the ground bus GB is alternatively coupled to a negative power supply bus (e.g., VSS = -1.7V), the same principle applies.

[0107] Figure 5B This is another implementation of a current mirror circuit that can reduce the impact of power bus resistance on the output current of the current mirror. Specifically, the current mirror circuit 500b has an input terminal in 1b Output terminal OUT 1b First transistor M 1b Second transistor M 2b Third transistor M3b and the fourth transistor M 4b In the depicted example, the first transistor M 1b Second transistor M 2b Each has a first conductivity type (e.g., a p-channel transistor), and the third transistor M 3b and the fourth transistor M 4b Each has a second conductivity type (e.g., an n-channel transistor) that is different from the first conductivity type.

[0108] First transistor M 1b Having a first (e.g., drain) terminal d 1b Second (e.g., source) terminal s 1b and the third (e.g., control or gate) terminal g 1b The second transistor M 2b Having a first (e.g., drain) terminal d 2b Second (e.g., source) terminal s 2b and the third (e.g., control or gate) terminal g 2b The third transistor M 3b Having a first (e.g., drain) terminal d 3b Second (e.g., source) terminal s 3b and the third (e.g., control or gate) terminal g 3b The fourth transistor M 4b Having a first (e.g., drain) terminal d 4b Second (e.g., source) terminal s 4b and the third (e.g., control or gate) terminal g 4b .

[0109] For convenience, the first transistor M 1b First terminal d 1b Second terminal s 1b and the third terminal g 1b In this paper, they will also be referred to as the first transistor M. 1b drain d 1b 、Source poles s 1b and gate g 1b Similarly, the second transistor M 2b First terminal d 2b Second terminal s 2b and the third terminal g 2b In this paper, they will also be referred to as the second transistor M. 2b drain d 2b 、Source poles s 2b and gate g 2b Similarly, the third transistor M 3b First terminal d 3bSecond terminal s 3b and the third terminal g 3b In this article, they will also be referred to as the third transistor M. 3b drain d 3b 、Source poles s 3b and gate g 3b Additionally, the fourth transistor M 4b First terminal d 4b Second terminal s 4b and the third terminal g 4b In this paper, the drain d4, source s4, and gate g4 of the fourth transistor M4 will be referred to as such, respectively.

[0110] First transistor M 1b drain d 1b Coupled to input terminal in 1b First transistor M 1b gate g 1b Second transistor M 2b gate g 2b The second transistor M 2b drain d 2b Coupled to the output terminal out 1b .like Figure 5B The drain d configured as shown 1b and gate g 1b The first transistor M coupled together 1b This is commonly referred to as a diode-connected transistor.

[0111] Third transistor M 3b drain d 3b Coupled to a second power supply bus (e.g., positive power supply bus PB), and a third transistor M 3b gate g 3b and the fourth transistor M 4b gate g 4b The fourth transistor M 4b drain d 4b It is coupled to the positive power supply bus PB, which is coupled to the second power supply VDD. For example... Figure 5B The drain d configured as shown 3b and gate g 3b The third transistor M is coupled together 3b This is commonly referred to as a diode-connected transistor. The resistance in the power bus PB is represented as R. p In one implementation, the third transistor M 3b drain d 3b Coupled to the first position of the positive power supply bus PB, and the fourth transistor M 4b drain d 4bIt is coupled to a second position that is different from the first position of the positive power supply bus PB.

[0112] First transistor M 1b The source of s 1b Coupled to the third transistor M 3b The source of s 3b And the second transistor M 2b The source of s 2b Coupled to the fourth transistor M 4b The source of s 4b Input terminal in 1b Receive input reference current I REF Here it is described as an ideal current source coupled to the first power supply GND.

[0113] During operation, the reference current I REF The current flows through the diode connected to the first transistor M 1b The third transistor M is connected to the diode. 3b The third transistor M 3b drain d 3b and gate g 3b At the same voltage V g3b .exist Figure 5B In the implementation scheme, the third transistor M 3b drain d 3b and gate g 3b Coupled to the positive power supply bus PB, therefore the voltage V g3b In VDD (e.g., V g3b =1.7V).

[0114] The third transistor M 3b gate g 3b Coupled to the fourth transistor M 4b gate g 4b The conductor in Figure 5B The middle label is PB Q Conductor PB Q Also referred to in this article as the "silent power bus" PB Q No current flows through the silent power bus PB. Q Therefore, the fourth transistor M 4b gate g 4b In relation to the third transistor M 3b gate g 3b Voltage V at point g3b Basically the same voltage V g4b .exist Figure 5B In the implementation scheme, voltage V g4b In VDD (e.g., V g4a =1.7V).

[0115] Third transistor M 3b The source of s 3b At voltage V s3b This voltage can be expressed as:

[0116] V s3b =VDD-(V ON3 +V tn (16) Where V ON3 For the third transistor M 3b The on-state voltage, and V tn M is an n-channel third transistor 3b The threshold voltage. First transistor M 1b The source of s 1b At voltage V s1b And coupled to the third transistor M 3b The source of s 3b Therefore, the voltage V s1b Equal to voltage V s3b :

[0117] V s1b =V s3b (17)

[0118] As described above, the third transistor M 3b gate g 3b and the fourth transistor M 4b gate g 4b At essentially the same voltage V g3b Since the source voltage of a MOS transistor in saturation is a very weak function of the drain voltage, the fourth transistor M... 4b The source of s 4b In relation to the third transistor M 3b The source of s 3b Voltage V at point s3b Basically the same voltage V s4b :

[0119] V s4b ≈V s3b (18)

[0120] Not wishing to be bound by any particular theory, it is believed that even due to the positive power supply bus PB resistor R... p The fourth transistor M is caused by the voltage drop across its terminals. 4b drain d 4b With the third transistor M 3b drain d 3b The voltage difference of several hundred millivolts between them causes the source voltage V to... s3b and V s4b The very small difference is mainly due to the third transistor M.3b and the fourth transistor M 4b Works in the saturation region.

[0121] Second transistor M 2b The source of s 2b At voltage V s2b And coupled to the fourth transistor M 4b The source of s 4b Therefore, the second transistor M 2b The source of s 2b Voltage V at point s2b Equal to the fourth transistor M 4b The source of s 4b Voltage V at point s4b :

[0122] V s2b =V s4b (19)

[0123] Therefore, according to formulas (17)–(19), the second transistor M 2b The source of s 2b and the first transistor M 1b The source of s 1b At essentially the same voltage:

[0124] V s2b ≈V s1b (20)

[0125] In one implementation, although in the third transistor M 3b drain d 3b With the fourth transistor M 4b drain d 4b There is a voltage drop in the positive power bus PB between them, but V s2b With V s1b The absolute value of the difference between them is less than about 5%. In another implementation, although in the third transistor M 3b drain d 3b With the fourth transistor M 4b drain d 4b There is a voltage drop in the positive power bus PB between them, but V s2b With V s1b The absolute value of the difference between them is less than about 2%. In yet another implementation, although in the third transistor M 3b drain d 3b With the fourth transistor M 4b drain d 4b There is a voltage drop in the positive power bus PB between them, but V s2b With V s1b The absolute value of the difference between them is less than approximately 1%.

[0126] The gate g of the first transistor 1b At voltage V g1b This voltage can be expressed as:

[0127] V g1b =V s1b -(V ON1 +|V tp |) (21)

[0128] Where V ON1 For the first transistor M 1b The on-state voltage, and V tp M is the first p-channel transistor. 1b The threshold voltage. Substituting formula (16) into formula (21), the voltage V g1b It can be represented as:

[0129] V g1b =VDD-(V ON3 +V tn +V ON1 +|V tp |) (22)

[0130] The first transistor M 1b gate g 1b Coupled to the second transistor M 2b gate g 2b The conductor in Figure 5B The middle is marked as B b No current flows through conductor B. b Therefore, the second transistor M 2b gate g 2b Also at voltage V g1b Therefore, the first transistor M 1b Source-gate voltage V sg1b Basically equal to the second transistor M 2b Source-gate voltage V sg2b :

[0131] V sg1b =V sg2b (twenty three)

[0132] If the first transistor M 1b Second transistor M 2b If they have the same dimensions, then the second transistor M 2b The conduction current is essentially equal to the reference current I. REF Output current I Mp :

[0133] I Mp =I REF (twenty four)

[0134] In this respect, the output current I Mp "Mirror" reference current I REF And in this paper it is also referred to as the mirror current I. Mp .

[0135] Following the above text about Figure 4A Similar terms to those used in the current mirror circuit 400a. Figure 5B The first transistor M of the 500b current mirror circuit 1b Second transistor M 2b Third transistor M 3b and the fourth transistor M 4b In this paper, they are also referred to as "the first driving device M". 1b "First mirror device M" 2b "Second driving device M" 3b "and the second mirror device M" 4b ".

[0136] By respectively making the first mirror device M 2b Second mirror device M 4b The size relative to the first driving device M 1b Second driving device M 3b The size is proportional, which can make the output current I... Mp With reference current I REF Proportional.

[0137] For example, if the first driving device M 1b The first mirror device M has a width W1 and a length L. 2b With a width W2 and a length L, the second driving device M 3b It has a width W3 and a length L, and a second mirror device M. 4b It has a width W4 and a length L, and if W2 / W1 = W4 / W3, then the output current I... Mp It can be represented as follows:

[0138]

[0139] For example, if W2 = W1, then I Mp =I REF If W2 = 2W1. Alternatively, if I... Mp =2×I REF And so on.

[0140] In order to convert the mirror current I Mp Multiple circuits copied onto the integrated circuit die, bus B b and silent power bus PB QThe first mirror device M can be inserted throughout the entire die. 2b Second mirror device M 4b Multiple instances, which are scaled as needed to provide a reference current I REF A proportional mirror current. Since virtually no current flows through bus B. b Therefore, bus B b The voltage on the die remains essentially constant at V throughout the die. g1b In this respect, the first driving device M 1b On bus B b The first bias voltage V is provided. g1b Similarly, since virtually no current flows through the silent power bus PB... Q Therefore, the silent power bus PB Q The voltage on the die remains essentially constant at V throughout the die. g3b In this respect, the second drive device M 3b In the silent power bus PB Q Provides a different bias voltage V than the first bias voltage. g1b The second bias voltage V g3b .

[0141] Therefore, it is not desirable to be bound by any particular theory, as it is believed that despite the resistance R in the positive power bus PB p This leads to the second mirror device M in the entire die. 4b Drain d on all instances 4b Voltage changes at the location, but the first mirror device M 2b The source-gate voltage will be substantially the same across the entire die in all instances (for a 1:1 mirror device), therefore, all mirror currents Id will be the same. Mp It will be substantially the same throughout the die (for a 1:1 scale mirror device), while with the first driver M 1b and the first mirror device M 2b The voltage difference along the power bus between them is irrelevant.

[0142] Furthermore, it is not desired to be bound by any particular theory, as it is believed that despite the resistance R in the positive power bus PB... p This leads to the second mirror device M in the entire die. 4b Drain d on all instances 4b Voltage changes at the location, but the first mirror device M 2b The source-gate voltage will be substantially the same across the entire die (for a 1:1 mirror device), therefore, all mirror currents Id will be the same. Mp It will be substantially the same throughout the die (for a 1:1 scale mirror device), while with the first driver M 1band the first mirror device M 2b The distance between them is irrelevant.

[0143] Figure 6 This is a diagram of one implementation of the memory die 600. Figure 1 Each of the one or more memory dies 106 can be implemented as Figure 6 The memory die 600 includes a current mirror drive circuit 602 and a memory array 604. The current mirror drive circuit 602 is coupled to a power bus (e.g., ground bus GB) and includes components configured to provide a first bias voltage VB. a The first driving device M 1a And configured to provide a voltage different from the first bias voltage VB a The second bias voltage VB Q The second driving device M 3a First driving device M 1a Second driving device M 3a Conducting the first current I REF .

[0144] In one embodiment, the memory array 604 includes multiple subarrays 6061, 6062, 6063, ..., 606 n Each subarray is 6061, 6062, 6063, ..., 606 n Including the corresponding first mirror device M, which is coupled to the first bias voltage. 2a1 M 2a2 M 2a3 ... M 2an And the corresponding second mirror device M, which is coupled to the second bias voltage and the ground bus GB respectively. 4a1 M 4a2 M 4a3 ... M 4an .

[0145] In one implementation, each first mirror device M 2a1 M 2a2 M 2a3 ... M 2an Second mirror device M 4a1 M 4a2 M 4a3 ... M 4an Conducting the corresponding second current I respectively Mn1 I Mn2 I Mn3 ... I Mnn In one implementation, subarrays 6061, 6062, 6063, ..., 606n The corresponding second current I Mn1 I Mn2 I Mn3 ... I Mnn They are basically equal.

[0146] One embodiment includes a circuit comprising a first transistor having a first terminal, a second terminal, and a third terminal, and a second transistor having a first terminal, a second terminal, and a third terminal. The first terminal of the first transistor includes an input terminal of the circuit, the second terminal of the first transistor is coupled to a power bus, and the first transistor conducts a first current. The first terminal of the first transistor also includes an output terminal of the circuit, the second terminal of the second transistor is coupled to the power bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current, substantially independent of the distance between the first and second transistors.

[0147] One embodiment includes a current mirror circuit comprising a diode-connected first transistor having a first conductivity type, a second transistor having a first conductivity type, a diode-connected third transistor having a second conductivity type different from the first conductivity type, and a fourth transistor having a second conductivity type. The diode-connected first transistor is coupled to the second transistor, and a control terminal of the first transistor is coupled to a control terminal of the second transistor. The diode-connected third transistor is coupled to the first diode-connected transistor and the fourth transistor, the fourth transistor is coupled to the second transistor, and a control terminal of the third transistor is coupled to a control terminal of the second transistor. The first and third transistors each conduct a first current, and the second and fourth transistors each conduct a second current substantially proportional to the first current.

[0148] One embodiment includes an apparatus comprising a memory die including a current mirror drive circuit and a memory array. The current mirror drive circuit is coupled to a power bus and includes a first drive device configured to provide a first bias voltage and a second drive device configured to provide a second bias voltage different from the first bias voltage. The first and second drive devices conduct a first current. The memory array includes a plurality of subarrays, each subarray including a corresponding first mirror device coupled to the first bias voltage and a corresponding second mirror device coupled to the second bias voltage and the power bus. The first and second mirror devices conduct corresponding second currents. The corresponding second currents of each of the plurality of subarrays are substantially equal.

[0149] For the purposes of this document, the terms “implementation scheme,” “one implementation scheme,” “some implementation schemes,” or “another implementation scheme” used in the specification may be used to describe different implementation schemes or the same implementation scheme.

[0150] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is mentioned as being connected or coupled to another element, that element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is mentioned as being directly connected to another element, there is no intermediary element between that element and the other element. If two devices are directly or indirectly connected, the two devices are “communicating”, enabling them to communicate electronic signals between them.

[0151] For the purposes of this document, the term “based on” may be understood as “at least partially based on”.

[0152] For the purposes of this document, the use of numerical terms such as “first” object, “second” object, and “third” object without additional context may not imply an ordering of objects, but may be used for identification purposes to distinguish different objects.

[0153] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0154] The detailed description above has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the precise forms disclosed in the invention. Many modifications and variations are possible based on the teachings above. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and various modifications suitable for the specific intended use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A circuit, the circuit comprising: A first transistor, comprising a first terminal, a second terminal and a third terminal, wherein the first terminal of the first transistor is an input terminal of the circuit, the second terminal of the first transistor is coupled to a power bus, and the first transistor conducts a first current. The second transistor includes a first terminal, a second terminal, and a third terminal. The first terminal of the second transistor includes the output terminal of the circuit. The second terminal of the second transistor is coupled to the power bus. The third terminal of the second transistor is coupled to the third terminal of the first transistor. A third transistor, comprising a first terminal, a second terminal, and a third terminal, wherein the first terminal of the third transistor is coupled to the power bus, and the second terminal of the third transistor is coupled to the second terminal of the first transistor to conduct the first current; and A fourth transistor, the fourth transistor including a first terminal, a second terminal and a third terminal, the first terminal of the fourth transistor being coupled to the power bus, the second terminal of the fourth transistor being coupled to the second terminal of the second transistor, and the third terminal of the third transistor being coupled to the third terminal of the fourth transistor; The second transistor conducts a second current that is proportional to the first current, and is independent of the resistance in the power bus between the first transistor and the second transistor; as well as The first transistor and the second transistor have a first conductivity type, and the third transistor and the fourth transistor have a second conductivity type different from the first conductivity type.

2. The circuit according to claim 1, wherein the first terminal of the first transistor is coupled to the third terminal of the first transistor.

3. The circuit according to claim 1, wherein the second current is equal to the first current.

4. The circuit of claim 1, wherein the voltage at the second terminal of the second transistor is equal to the voltage at the second terminal of the first transistor, and is independent of the distance between the first transistor and the second transistor.

5. The circuit according to claim 1, wherein: The second terminal of the first transistor is coupled to a first position on the power bus; and The second terminal of the second transistor is coupled to a second position on the power bus that is different from the first position.

6. The circuit of claim 5, wherein the first voltage at the first location of the power bus is different from the second voltage at the second location of the power bus.

7. The circuit of claim 1, wherein the first terminal of the third transistor is coupled to the third terminal of the third transistor.

8. The circuit of claim 1, wherein the power bus includes any one of a ground bus, a positive power bus, or a negative power bus.

9. The circuit according to claim 1, wherein the circuit includes a current mirror circuit.

10. A current mirror circuit, the current mirror circuit comprising: A diode having a first conductivity type is connected to a first transistor, the diode being coupled to a second transistor having the first conductivity type, and the control terminal of the first transistor being coupled to the control terminal of the second transistor. and A diode having a second conductivity type different from the first conductivity type is connected to a third transistor. This third transistor is coupled to the diode-connected first transistor and a fourth transistor having the second conductivity type. The fourth transistor is coupled to the second transistor. The control terminal of the third transistor is coupled to the control terminal of the fourth transistor. The first transistor and the third transistor each conduct a first current, and the second transistor and the fourth transistor each conduct a second current proportional to the first current; and The third transistor and the fourth transistor are each coupled to a power bus, the power bus including a voltage difference along the length of the power bus between the third transistor and the fourth transistor.

11. The current mirror circuit of claim 10, wherein the second current is proportional to the first current and is independent of the distance between the first transistor and the second transistor and between the third transistor and the fourth transistor.

12. The current mirror circuit of claim 10, wherein the second current is equal to the first current.

13. The current mirror circuit of claim 10, wherein the power bus includes any one of a ground bus, a positive power bus, or a negative power bus.

14. An apparatus comprising: Memory die, the memory die comprising: A current mirror drive circuit, coupled to a power bus and including a first driver configured to provide a first bias voltage and a second driver configured to provide a second bias voltage different from the first bias voltage, the first driver and the second driver conducting a first current; and The memory array includes multiple sub-arrays, each sub-array including a first mirror device coupled to a first bias voltage and a second mirror device coupled to a second bias voltage and the power bus, wherein the first mirror device and the second mirror device conduct corresponding second currents. The corresponding second current of each of the plurality of subarrays is equal and is independent of the resistance in the power bus.

15. The apparatus of claim 14, wherein each of the corresponding second currents is proportional to the first current.

16. The apparatus of claim 14, wherein the first driving device has a first conductivity type, and the second driving device has a second conductivity type different from the first conductivity type.

17. The apparatus of claim 14, wherein the power bus comprises any one of a ground bus, a positive power bus, or a negative power bus.

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