Instruction processing method and apparatus, computer readable medium, processor

Abstract

The present disclosure specifically relates to the technical field of computer, and specifically relates to an instruction processing method, an instruction processing device, a computer readable medium and a processor. The method comprises: receiving, by a task triggering module, a calling request of a current task of a business system, and storing task attribute information corresponding to the current task; and waking up a micro control unit, and reading the calling request and the task attribute information from the task triggering module, so as to determine a target computing engine corresponding to the current task according to the calling request and the task attribute information; and waking up the target computing engine to execute the current task. The technical scheme of the present disclosure can realize fine management of NPU power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, specifically to an instruction processing method, an instruction processing apparatus, a computer-readable medium, and a processor. Background Technology

[0002] With the widespread adoption of artificial intelligence (AI) applications, AI processors are being deployed on an increasing number of terminal devices, leading to higher demands on performance and power consumption. Reducing power consumption while maintaining operational performance has become a key research area. Unlike traditional processors, neural network processing units (NPUs) typically process data at the level of multi-dimensional tensors, requiring numerous computational units. Furthermore, the large volume of data transmitted during data transfer also contributes to power consumption. However, current power management strategies for NPU systems generally employ large-granularity power-on and power-off operations; for example, when the NPU is idle, it can be powered off to save power. However, such power management cannot achieve fine-grained control.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides an instruction processing method, an instruction processing apparatus, a computer-readable medium, and a processor capable of fine-grained management of NPU power consumption.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of this disclosure.

[0006] According to a first aspect of this disclosure, an instruction processing method is provided, applied to a processor, the method comprising:

[0007] The task triggering module receives the call request for the current task from the business system and stores the task attribute information corresponding to the current task; and

[0008] The microcontroller unit is woken up, and the call request and task attribute information are read from the task triggering module to determine the target computing engine corresponding to the current task based on the call request and task attribute information.

[0009] The target computing engine is awakened to execute the current task.

[0010] According to a second aspect of this disclosure, an instruction processing apparatus is provided for use with a processor, the apparatus comprising:

[0011] The triggering module is used to receive a call request from the business system for the current task through the task triggering module, and to store the task attribute information corresponding to the current task; and

[0012] The first wake-up control module is used to wake up the microcontroller unit and read the call request and task attribute information from the task triggering module, so as to determine the target computing engine corresponding to the current task based on the call request and task attribute information.

[0013] The second wake-up control module is used to wake up the target computing engine to execute the current task.

[0014] According to a third aspect of this disclosure, a computer-readable medium is provided having a computer program stored thereon, which, when executed by a processor, implements the instruction processing method described above.

[0015] According to a fourth aspect of this disclosure, a processor is provided, comprising:

[0016] The task triggering module is used to receive the call request for the current task from the business system and store the task attribute information corresponding to the current task.

[0017] The microcontroller unit is used to read the call request and task attribute information from the task triggering module after being woken up, so as to determine the target computing engine corresponding to the current task based on the call request and task attribute information;

[0018] The computing engine is used to execute the current task after being awakened.

[0019] One embodiment of this disclosure provides an instruction processing method that configures a task triggering module in a neural network processor to receive call requests from external business systems and store corresponding task attribute information. A power management module then wakes up the microcontroller unit (MCU), which reads the call request and task attribute information from the task triggering module to determine the target computing engine required for the current task. The power management module then wakes up the target computing engine to execute the current task and obtain its result data. This method achieves a gradual, batch wake-up of the MCU and computing engines, enabling a fine-grained management mechanism and thus more precise power consumption management. Furthermore, by determining and waking up only the necessary number of computing engines based on task attribute information, power consumption can be minimized.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0022] Figure 1 This schematic diagram illustrates the configuration of a neural network processor according to an exemplary embodiment of the present disclosure;

[0023] Figure 2 The illustration shows a schematic diagram of an instruction processing method in an exemplary embodiment of the present disclosure;

[0024] Figure 3 The illustration shows a schematic diagram of an instruction processing method in an exemplary embodiment of the present disclosure;

[0025] Figure 4 The illustration shows a schematic diagram of an instruction processing method in an exemplary embodiment of the present disclosure;

[0026] Figure 5 This schematic diagram illustrates a method for a microcontroller unit to enter a holding mode according to an exemplary embodiment of the present disclosure;

[0027] Figure 6 This schematic diagram illustrates the composition of an instruction processing apparatus according to an exemplary embodiment of the present disclosure;

[0028] Figure 7 This schematic diagram illustrates the composition of a processor according to an exemplary embodiment of the present disclosure;

[0029] Figure 8 The schematic diagram illustrates the composition of a processor in an exemplary embodiment of the present disclosure. Detailed Implementation

[0030] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0031] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0032] In related technologies, the typical power management strategy for NPUs is often a coarse-grained power-on and power-off operation. For example, when the NPU is idle, it can be powered off to save power. Although this is relatively simple in chip design, it may have a certain impact on the overall system performance. For instance, it takes about 100µs for the NPU to go from complete power-off to power-on in hardware, and several hundredµs for software to initialize and configure the NPU. In addition, waking the NPU from sleep mode also consumes some power. Therefore, this NPU wake-up management strategy does not achieve fine-grained management.

[0033] To address the shortcomings and deficiencies of the prior art described above, this exemplary embodiment provides an instruction processing method. (Reference) Figure 2 As shown, the above-described instruction processing method may include:

[0034] Step S11: Receive the call request for the current task from the business system through the task triggering module, and store the task attribute information corresponding to the current task; and

[0035] Step S12: Wake up the microcontroller unit and read the call request and task attribute information from the task triggering module, so as to determine the target computing engine corresponding to the current task based on the call request and task attribute information;

[0036] Step S13: Wake up the target computing engine to execute the current task.

[0037] The instruction processing method provided in this example implementation configures a task triggering module in the neural network processor to receive call requests from external business systems and store corresponding task attribute information. Then, a power management module wakes up the microcontroller unit (MCU), which reads the call request and task attribute information from the task triggering module to determine the target computing engine required for the current task. Finally, the power management module wakes up the target computing engine to execute the current task and obtain its result data. This achieves a gradual, batch wake-up of the MCU and computing engines, enabling a fine-grained management mechanism and thus more precise power consumption management. Furthermore, by determining and waking up only the necessary number of computing engines based on task attribute information, power consumption can be minimized.

[0038] The steps of the instruction processing method in this exemplary embodiment will now be described in more detail with reference to the accompanying drawings and embodiments.

[0039] In this example implementation, the instruction processing method described above can be applied to a neural network processor (NPU). (See reference...) Figure 1 As shown, the basic structure of the neural network processor 12 may include a microcontroller unit 124, an interrupt control module 125, a digital signal processing engine 123, a tensor vector processing engine 122, a task triggering module 126, an internal bus 128, and a power management module 121. The microcontroller unit (MCU) is responsible for coordinating the overall operation of the NPU and allocating tasks to each processing engine. The tensor vector processing engine (DSP) can have a multi-core architecture and is responsible for parts of the artificial intelligence algorithm network that are suitable for acceleration using dedicated circuits, such as convolution operators, pooling operators, and scaling operators. For operators that are not suitable for acceleration using dedicated circuits, the MCU can allocate them to the digital signal processing engine (DSP) for execution. A data path 131 is configured between the digital signal processing engine 123 and the tensor vector processing engine 122 to facilitate data interaction between the two engines. An on-chip memory 127 is configured on the slave end of the NPU internal bus 128, which can be used by the processing engines to read source data and write back result data. The task triggering module 126 may include two register groups; the first register 1261 may be a voting register, used to receive and store call requests from other modules or external business systems; for example, receiving call requests from external audio subsystem 111, video subsystem 112, and display system 113. The second register 1262 may be a task register group, used to write task attribute data.

[0040] In step S11, the task triggering module receives the call request for the current task from the business system and stores the task attribute information corresponding to the current task.

[0041] In this example implementation, refer to Figure 1 As shown, the task triggering module 126 includes a first register 1261 and a second register 1262. Step S11 specifically includes: receiving the call request of the current task through the first register of the task triggering module; and writing the task attribute information corresponding to the current task into the second register of the task triggering module.

[0042] Specifically, in the initial state, all parts of the NPU, except for the task triggering module, are in a dormant state. When a business system needs to call the neural network processor to execute algorithms for computation to obtain the result data of a computation task, the metadata that needs to be processed by the NPU can first be stored in a file such as... Figure 1 The system memory 114 or system cache 115 shown is used. The system content can be, for example, DDR (Double Data Rate) memory. For instance, if the current task is feature map calculation in image recognition, the source data can be the corresponding feature image data.

[0043] Simultaneously, the business system can utilize the direct communication path with the first register to notify the system of any NPU invocation requests; that is, sending the current computation task invocation request to the first register. Furthermore, it can write the task attribute information of the current computation task to the second register. This task attribute information may include: the task size, the source data address, and the storage address of the processed result data. Additionally, it may include the type of data computation and the type of computation engine required; specifically, the tensor vector computation engine and / or digital signal computation engine required for the current task.

[0044] In some exemplary embodiments, a data path can be established between each external business system and the task triggering module, facilitating the business system to write data into the first register and the second register. Alternatively, a direct path can be established between the first register and the business system; the business system sends the call request to the first register of the task triggering module through the direct path.

[0045] In step S12, the microcontroller unit is woken up, and the call request and task attribute information are read from the task triggering module to determine the target computing engine corresponding to the current task based on the call request and task attribute information.

[0046] In this example implementation, refer to Figure 1 As shown, the power management module 121 can be an internal power management module of the NPU, used to provide power to the various modules within the NPU. Alternatively, in other exemplary embodiments of this disclosure, the power management module 121 can also be an external power management module of the NPU, used to provide power to the various service subsystems and the NPU. Each service subsystem can connect to the power management module 121 and perform data interaction and command transmission.

[0047] Specifically, when the business system writes data to the first and second registers, it can also send an NPU wake-up control / start command to the power management module. Upon receiving the NPU wake-up command, the power management module can power on the microcontroller unit 124. Furthermore, as... Figure 1 As shown, an interrupt control module 125 can also be provided between the microcontroller unit 124 and the power management module 121. The power management module can first pass the interrupt control module through the power-on and power-off operations of the microcontroller unit to avoid accidental damage to the microcontroller unit due to frequent power control operations. For example, when the microcontroller unit is in the working state, the interrupt control module blocks the power-on operation when it receives the power-on operation from the power control module. Or, when the microcontroller unit is in the sleep state, if the interrupt control module receives the power-off operation from the power control module, it blocks the power-off operation. That is, the interrupt control module can check the status of the microcontroller unit before power-on and power-off.

[0048] After being woken up, the microcontroller first reads the call request from the first register to determine the initiator of the current call request; simultaneously, it reads task attribute data from the second register, and determines which computing engines to use and the corresponding number of computing engines based on the size of the task data and the required computing engine type, i.e., determining the target computing engines. The aforementioned target computing engines can be one or more, or one or more types of computing engines.

[0049] In step S13, the target computing engine is awakened to execute the current task.

[0050] In this example implementation, specifically, waking up the target computing engine may include: the microcontroller sending a wake-up command to the power management module, so that the power management module executes the wake-up command and wakes up the target computing engine.

[0051] For example, the aforementioned wake-up command is a computing engine wake-up command, which may include the identification information of the computing engine. When the power management module receives this computing engine wake-up command, it can wake up the specified target computing engine.

[0052] Specifically, the execution of the current task may include: the target engine reading task attribute information from the second register of the task triggering module, reading source data corresponding to the current task from the system cache according to the task attribute information, and writing the source data into the on-chip memory for calculation based on the source data; and the target computing engine writing the result data of the current task back to the on-chip memory.

[0053] For example, after the computing engine is awakened, it can read task attribute information from the second register to determine the specific calculation content, read source data, and perform calculations. Outside the NPU, the DDR memory or system cache on the system bus slave can be accessed via system bus 116. For example, a data path for data interaction is set up between the digital signal processing computing engine and the tensor vector computing engine; for instance, during the calculation process, the convolutional layer uses the tensor engine for calculation, and the activation function is completed using the DSP computing engine. After the convolutional layer data processing is complete, the intermediate result data can be directly sent to the DSP computing engine for processing via the data path. In this way, the intermediate result data does not need to be sent back to the OCM (on-chip memory), avoiding frequent writing and reading of intermediate data on the OCM, effectively saving computation time.

[0054] After generating the result data, it is written back to the on-chip memory; then the result data is written from the on-chip memory to the specified result data storage address.

[0055] Furthermore, in other exemplary embodiments of this disclosure, based on the above content, reference is made to... Figure 3 As shown, the above method may further include:

[0056] Step S14: After the current task is completed, when the microcontroller reads the task triggering module and determines that the current task triggering module is empty, it sends a computing engine hibernation control command to the power management module so that the power management module cuts off the power to the target computing engine.

[0057] Specifically, after the calculation result of the current task is written to the designated result data storage address, the MCU can read the first register again. If the first register contains an unexecuted calculation task, the above method is executed to complete the calculation task. Alternatively, if the first register and / or the second register are empty, a computing engine sleep control instruction is generated and sent to the power control module. Upon receiving the instruction, the power control module will power down the already started computing engine, putting it into sleep mode.

[0058] Furthermore, in some exemplary embodiments of this disclosure, reference is made to Figure 4As shown, the above method may further include:

[0059] Step S15: When the task triggering module is empty within a preset time period, the microcontroller reads the task triggering module and sends a microcontroller management command to the power management module so that the power management module cuts off the power to the microcontroller and puts the microcontroller into sleep mode or hold mode.

[0060] Specifically, if there are no new computing tasks within a certain period of time, the MCU will notify the power management module to allow the MCU to enter sleep mode or hold mode. If the MCU needs to enter sleep mode, the power management module needs to cut off the power supply to the MCU, and the MCU needs to be powered on again upon restarting.

[0061] In some exemplary embodiments, reference Figure 5 As shown, when the microcontroller enters the hold mode, the method further includes:

[0062] Step S151: Save the wake-up data of the microcontroller to the backup register;

[0063] Step S152: When waking up the microcontroller in hold mode, the wake-up data is written to the working register using the data path between the backup register and the working register to wake up the microcontroller; wherein, the backup register uses low voltage.

[0064] Specifically, if the MCU enters sleep mode, it needs to be powered on again upon restarting, and the software needs to configure the initialization sequence, which takes a relatively long time. Therefore, in some cases, the MCU can choose to enter hold mode.

[0065] Specifically, a backup register can be configured for the MCU. A data path exists between the backup register and the MCU's original working register. The working register uses the normal operating voltage, while the backup register uses a lower voltage to retain data. When the MCU chooses to enter hold mode, it first needs to store the data in the working register into the backup register and provide a lower voltage to maintain the data. Simultaneously, the operating voltage is cut off. In this way, the basic wake-up data required to wake up the MCU is backed up in the backup register. When the MCU needs to switch from hold mode to normal operating mode, it simply needs to power on, transfer the data from the backup register to the working register, and then cut off the lower voltage. The wake-up data mentioned above can be the MCU's configuration data.

[0066] In addition, in this exemplary embodiment, the on-chip memory 127 can also be divided into regions. One region can be used to enter hold mode; another region can only have two modes: power-on and power-off, i.e., it is used for sleep mode. If some necessary data information required for MCU wake-up is stored in SRAM, then if the power is completely cut off when entering sleep mode, it will affect the wake-up time. Therefore, this data can be put into the storage space that can enter hold mode.

[0067] The instruction processing method provided in this disclosure allows the external business system to first wake up the MCU inside the NPU after writing the current task's call request to the task triggering module. The MCU can then read the call request and task attribute data from the first and second registers respectively to determine the target computing engine and wake it up. This enables batch wake-up of NPU modules, achieving a more refined power management strategy. Furthermore, when there are no computing tasks, the computing engine can enter a sleep state, allowing the MCU to selectively enter or remain in sleep mode, minimizing performance impact and maximizing power consumption reduction. By selectively waking up computing engines based on computing tasks, performance losses caused by coarse-grained management are avoided.

[0068] It should be noted that the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may, for example, be executed synchronously or asynchronously in multiple modules.

[0069] Further reference Figure 6 As shown, this example embodiment also provides an instruction processing device 60, applied to a processor, the device including: a trigger module 601, a first wake-up control module 602, and a second wake-up control module 603. Wherein,

[0070] The triggering module 601 can be used to receive a call request from the business system for the current task through the task triggering module, and store the task attribute information corresponding to the current task.

[0071] The first wake-up control module 602 can be used to wake up the microcontroller unit and read the call request and task attribute information from the task triggering module, so as to determine the target computing engine corresponding to the current task based on the call request and task attribute information.

[0072] The second wake-up control module 603 can be used to wake up the target computing engine to execute the current task.

[0073] Further reference Figure 7 As shown, this example embodiment also provides a processor 70, including: a task triggering module 701, a microcontroller unit 702, and a target computing engine 703. Wherein,

[0074] The task triggering module 701 can be used to receive a call request from the business system for the current task and store the task attribute information corresponding to the current task.

[0075] The microcontroller unit 702 can be used to read the call request and task attribute information from the task triggering module after being woken up, so as to determine the target computing engine corresponding to the current task based on the call request and task attribute information.

[0076] The computing engine 703 can be used to execute the current task after being awakened.

[0077] In some exemplary embodiments, reference Figure 8 As shown, corresponding to the above Figure 1 The processor configuration shown may further include: a power management module 704, an interrupt control module 705, and an on-chip memory 706.

[0078] The task triggering module 701 may include a voting register for receiving and storing call requests from other modules and external business systems, and a task register group for writing task attribute data. The aforementioned computing engine 703 may include a digital signal computing engine and a tensor vector computing engine, with a data path for data exchange between them. An interrupt control module may also be provided between the microcontroller unit and the power management module for power control of the microcontroller unit. Modules within the processor can exchange data via an internal bus.

[0079] The specific details of each module in the instruction processing device 60 and processor 70 have been described in detail in the corresponding instruction processing methods, so they will not be repeated here.

[0080] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0081] It should be noted that, as another aspect, this application also provides a computer-readable medium, which may be included in an electronic device or may exist independently without being assembled into the electronic device. The aforementioned computer-readable medium carries one or more programs, which, when executed by an electronic device, cause the electronic device to perform the methods described in the following embodiments. For example, the electronic device may perform... Figure 2 The steps shown.

[0082] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0083] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0084] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. An instruction processing method, characterized in that, Applied to a processor, the method includes: The task triggering module receives the call request for the current task from the business system and stores the task attribute information corresponding to the current task; and The microcontroller unit is woken up, and the call request and task attribute information are read from the task triggering module to determine the target computing engine corresponding to the current task based on the call request and task attribute information. Wake up the target computing engine to execute the current task; The target computing engine includes: a digital signal processing computing engine and a tensor vector computing engine; a data path for data interaction is provided between the digital signal processing computing engine and the tensor vector computing engine. The method further includes: After the current task is completed, when the microcontroller reads the task triggering module and determines that the task triggering module is currently empty, it sends a computing engine hibernation control command to the power management module so that the power management module cuts off the power to the target computing engine. When the microcontroller reads the task triggering module and the task triggering module is empty within a preset time period, it sends a microcontroller management command to the power management module so that the power management module cuts off the power to the microcontroller and puts the microcontroller into a sleep mode or a hold mode. When the microcontroller enters the hold mode, the method further includes: The wake-up data of the microcontroller is saved to the backup register; when the microcontroller is woken up in hold mode, the wake-up data is written to the working register using the data path between the backup register and the working register to wake up the microcontroller; wherein, the backup register uses low voltage.

2. The instruction processing method according to claim 1, characterized in that, The task triggering module includes a first register and a second register; the process of receiving a call request for the current task from the business system and storing the task attribute information corresponding to the current task through the task triggering module includes: The task triggering module receives the call request of the current task through its first register and writes the task attribute information corresponding to the current task into its second register.

3. The instruction processing method according to claim 2, characterized in that, A direct connection is established between the first register and the business system; The step of receiving the call request of the current task through the first register of the task triggering module includes: The business system sends the call request to the first register of the task triggering module through the direct access path.

4. The instruction processing method according to claim 1, characterized in that, The step of waking up the target computing engine includes: The microcontroller sends a wake-up command to the power management module, so that the power management module executes the wake-up command and wakes up the target computing engine.

5. The instruction processing method according to claim 1 or 4, characterized in that, Executing the current task includes: The target computing engine reads task attribute information from the second register of the task triggering module, reads the source data corresponding to the current task from the system cache according to the task attribute information, and writes the source data into the on-chip memory for computation based on the source data; and The target computing engine writes the result data of the current task back to the on-chip memory.

6. An instruction processing device, characterized in that, Applied to a processor, the device includes: The triggering module is used to receive a call request from the business system for the current task through the task triggering module, and to store the task attribute information corresponding to the current task; and The first wake-up control module is used to wake up the microcontroller unit and read the call request and task attribute information from the task triggering module, so as to determine the target computing engine corresponding to the current task based on the call request and task attribute information. The second wake-up control module is used to wake up the target computing engine to execute the current task; wherein, the target computing engine includes: a digital signal processing computing engine and a tensor vector computing engine; a data path for data interaction is provided between the digital signal processing computing engine and the tensor vector computing engine; The device is also used to, after the current task is completed, when the microcontroller reads the task triggering module and determines that the current task triggering module is empty, send a computing engine hibernation control command to the power management module so that the power management module cuts off the power to the target computing engine; When the microcontroller reads the task triggering module and the task triggering module is empty within a preset time period, it sends a microcontroller management command to the power management module so that the power management module cuts off the power to the microcontroller and puts the microcontroller into a sleep mode or a hold mode. When the microcontroller enters the hold mode, the device is further configured to save the wake-up data of the microcontroller to a backup register; when waking up the microcontroller in the hold mode, the wake-up data is written to the working register using the data path between the backup register and the working register to wake up the microcontroller; wherein the backup register uses a low voltage.

7. A computer-readable medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the instruction processing method as described in any one of claims 1 to 5.

8. A processor, characterized in that, include: The task triggering module is used to receive the call request for the current task from the business system and store the task attribute information corresponding to the current task. The microcontroller unit is used to read the call request and task attribute information from the task triggering module after being woken up, so as to determine the target computing engine corresponding to the current task based on the call request and task attribute information; The target computing engine includes: a digital signal processing computing engine and a tensor vector computing engine; a data path for data interaction is provided between the digital signal processing computing engine and the tensor vector computing engine. The computing engine is used to execute the current task after being awakened; The processor is further configured to, upon completion of the current task, when the microcontroller reads the task triggering module and determines that the current task triggering module is empty, send a computing engine hibernation control command to the power management module so that the power management module cuts off the power to the target computing engine; When the microcontroller reads the task triggering module and the task triggering module is empty within a preset time period, it sends a microcontroller management command to the power management module so that the power management module cuts off the power to the microcontroller and puts the microcontroller into a sleep mode or a hold mode. When the microcontroller enters hold mode, the processor is further configured to save the wake-up data of the microcontroller to a backup register; when waking up the microcontroller in hold mode, the processor writes the wake-up data to the working register using the data path between the backup register and the working register to wake up the microcontroller; wherein the backup register uses a low voltage.

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