A nonlinear scrambling method, apparatus, computer equipment, and storage medium

Abstract

This invention discloses a nonlinear scrambling method, apparatus, computer device, and storage medium. The method includes: calculating dynamic variable PPA values ​​using minimum write address units of different manufacturers and sizes; calculating values ​​with offsets LPA and LBA using counters; constructing a configurable seed table; recording read / write counts using the content of the issued descriptor, based on the lifecycle of the granules, to modify the index of the seed table; and scrambling the data seed structure using a combination of linear and nonlinear calculations, based on the granule hierarchy relationships corresponding to the seed table. By implementing the method of this invention, additional differentiation can be achieved for seeds at different granule levels and with different read / write counts, avoiding excessively small differences in scrambling seeds and resulting in better data diffusion during the scrambling process.

Description

Technical Field

[0001] This invention relates to solid-state drives, and more specifically to a nonlinear scrambling method, apparatus, computer equipment, and storage medium. Background Technology

[0002] During solid-state drive (SSD) read / write operations, it is necessary to avoid a large number of "0"s and "1"s in the transmitted data. This is achieved through scrambling algorithms, which in turn affects the reliability of data written to and read from the flash memory.

[0003] In the implementation of data randomization, traditional scrambling codes have the following characteristics and classifications: the scrambling circuit is built from a fixed polynomial, using shift registers and XOR logic, and the generated data belongs to a pseudo-random distribution sequence; the actual principle of scrambling codes can be divided into linear and nonlinear, with serial scrambling codes used in the early days, and parallel scrambling codes now widely used. The implementation of parallel scrambling codes is divided into table lookup method and matrix construction method; it plays a certain data encryption function and has synchronous scrambling codes and self-synchronous scrambling codes.

[0004] Most existing scrambling circuit structures use the data scrambling mode of the linear feedback shift register (LFSR), which only considers the differences in seed construction at different addresses of the granules. However, the scrambling effect on seeds and data is not strong in bad situations.

[0005] Therefore, it is necessary to design a new method to achieve additional differentiation of seeds for different granular levels and different read / write cycles, so as to avoid the difference of scrambling seeds being too small, and to make the data have a better diffusion effect during the scrambling process. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a nonlinear scrambling method, apparatus, computer equipment, and storage medium.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: a nonlinear scrambling code method, comprising:

[0008] The dynamic variable ppa value is calculated by using the smallest write address unit of different manufacturers and sizes;

[0009] The values ​​of offsets lpa and lba are calculated using counters;

[0010] Construct a configurable seed table;

[0011] Based on the lifecycle of the granules, the content of the issued descriptor is used to record the number of reads and writes in order to modify the index of the seedtable table;

[0012] By combining linear and nonlinear calculations, the composition of data seeds is shuffled based on the granular hierarchy relationships corresponding to the seed table.

[0013] Its further technical solution is as follows: the composition of the data seed is shuffled by combining linear and nonlinear calculations to shuffle the granular hierarchical relationship corresponding to the seed table, including:

[0014] Based on the granular hierarchy relationship corresponding to the seed table, a combination of linear and nonlinear calculations is used to initially shuffle the input data seed in a three-stage pipeline manner.

[0015] The initial scrambling result is then scrambled a second time based on the write characteristics.

[0016] The further technical solution is as follows: the input data is initially shuffled using a three-stage pipelined process to construct the data seed, which combines linear and nonlinear calculations based on the granular hierarchical relationship corresponding to the seed table. This includes:

[0017] The input data is subjected to linear logical operations based on the granular hierarchy of the seed table, and the results of the operations are then split to obtain the split results.

[0018] Perform linear logic operations on the splitting result to obtain a second operation result;

[0019] The second operation result is used to perform non-linear permutation of the sbox of the AES encryption algorithm, followed by linear logic operations and data merging.

[0020] The further technical solution is as follows: the linear logic operation includes 9 to 12 numerical shift operations.

[0021] The further technical solution is as follows: the secondary scrambling of the initial scrambling result based on the writing characteristics includes:

[0022] An offset is added to the initial scrambled result to perform a second scrambling.

[0023] The further technical solution is as follows: adding an offset to the initial scrambling result to perform a secondary scrambling includes:

[0024] Add an offset to the codeword address and page address of the initial scrambled result;

[0025] Perform linear operations on the codeword address and page address to modify the codeword address and page address;

[0026] Based on the number of reads and writes, perform linear operations on the modified codeword address and page address;

[0027] The codeword address and page address after the linear operation are modified a second time.

[0028] The present invention also provides a nonlinear scrambling device, comprising:

[0029] The first calculation unit is used to calculate the dynamic variable ppa value using the smallest write address unit of different manufacturers and sizes;

[0030] The second calculation unit is used to calculate the values ​​of offsets lpa and lba using counters;

[0031] Construction unit, used to construct a configurable seed table;

[0032] The recording unit is used to record the number of reads and writes based on the lifecycle of the granule and the content of the issued descriptor, so as to modify the index of the seed table.

[0033] The scrambling unit is used to scramble the composition of the data seed by combining linear and nonlinear calculations based on the granular hierarchy relationship corresponding to the seed table.

[0034] The further technical solution is as follows: the scrambling unit includes:

[0035] The initial shuffling sub-unit is used to construct the initial shuffling of the input data seed by combining linear and nonlinear calculations based on the granular hierarchy relationship corresponding to the seed table.

[0036] The secondary scrambling subunit is used to perform secondary scrambling on the result of the initial scrambling based on the writing characteristics.

[0037] The present invention also provides a computer device, the computer device including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the above-described method.

[0038] The present invention also provides a storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0039] The beneficial effects of this invention compared to existing technologies are as follows: This invention improves resistance to linear and differential attacks by employing the sbox in the international standard encryption algorithm AES during the scrambling of the data seed structure. This enhances the scrambling effect even under the worst-case scrambling seed conditions. Furthermore, it utilizes numerous shift registers and XOR logic to increase the random distribution characteristics of each seed round. A three-stage pipeline architecture is adopted to increase system bandwidth while meeting circuit complexity requirements, satisfying the seed differentiation between different levels of the granular material, the seed differentiation of different codewords within a single page of the flash granular material, and adding secondary scrambling to satisfy seed differentiation for n consecutive read / write operations within the same address space. This achieves additional seed differentiation for different levels of the granular material and different read / write operations, preventing the scrambling seed difference from being too small, resulting in better data diffusion during the scrambling process.

[0040] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A flowchart illustrating a nonlinear scrambling method provided in an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of a sub-process of a nonlinear scrambling method provided in an embodiment of the present invention;

[0044] Figure 3 A schematic diagram of a sub-process of a nonlinear scrambling method provided in an embodiment of the present invention;

[0045] Figure 4 A schematic diagram of a sub-process of a nonlinear scrambling method provided in an embodiment of the present invention;

[0046] Figure 5 This is a schematic diagram of the flash particle structure provided in an embodiment of the present invention;

[0047] Figure 6 This is a schematic diagram of the circuit model of the scrambling code in the chip provided in an embodiment of the present invention;

[0048] Figure 7 A schematic diagram of a scrambling code encoding module provided in an embodiment of the present invention;

[0049] Figure 8 This is a schematic diagram of the scrambling code calculation circuit provided in an embodiment of the present invention;

[0050] Figure 9 This is a schematic diagram of the lfsr parallel computing unit provided in an embodiment of the present invention;

[0051] Figure 10 A schematic diagram illustrating the scrambling code calculation principle provided in this embodiment of the invention;

[0052] Figure 11 A pipeline structure diagram of the scrambling code provided in an embodiment of the present invention;

[0053] Figure 12 This is a timing diagram of scrambling code execution provided in an embodiment of the present invention;

[0054] Figure 13 This is a statistical chart showing the average total number of "0" and "1" values ​​provided in an embodiment of the present invention.

[0055] Figure 14 This is a graph showing the number of consecutive "0" and "1" occurrences in a random cw file provided in an embodiment of the present invention.

[0056] Figure 15 The distribution diagram of "0" and "1" of seed and data under the round scrambling mode provided in the embodiment of the present invention;

[0057] Figure 16 A schematic block diagram of a nonlinear scrambling device provided in an embodiment of the present invention;

[0058] Figure 17 A schematic block diagram of a scrambling unit of a nonlinear scrambling device provided in an embodiment of the present invention;

[0059] Figure 18 A schematic block diagram of the initial scrambling subunit of a nonlinear scrambling device provided in an embodiment of the present invention;

[0060] Figure 19 A schematic block diagram of a secondary scrambling subunit of a nonlinear scrambling device provided in an embodiment of the present invention;

[0061] Figure 20 A schematic block diagram of a computer device provided for an embodiment of the present invention. Detailed Implementation

[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0064] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0065] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0066] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating a nonlinear scrambling method provided in an embodiment of the present invention. This nonlinear scrambling method is applied to solid-state drives (SSDs) and improves the randomization of scrambled data by increasing the complexity of data computation.

[0067] Figure 2 This is a flowchart illustrating a nonlinear scrambling method provided in an embodiment of the present invention. Figure 2 As shown, the method includes the following steps S110 to S150.

[0068] S110. Calculate the dynamic variable ppa value using the smallest write address unit of different manufacturers and sizes;

[0069] S120. Calculate the values ​​of offset lpa and lba using a counter.

[0070] Please see Figure 5 An important component of seed generation is the location of data stored in the particles, which are ordered by size as follows: lun>plane>block>word line(WL)>ppa>lpa>lba.

[0071] Specifically, the values ​​of offsets lpa and lba are calculated using counters in the internal circuitry.

[0072] S130. Construct a configurable seed table.

[0073] In this embodiment, the seed table is maintained by the firmware department and contains highly randomized seeds, which also facilitates updates and iterations.

[0074] S140. Based on the lifecycle of the granules, use the content of the issued descriptor to record the number of reads and writes in order to modify the index of the seed table.

[0075] S150. Combining the granular hierarchy relationship corresponding to the seed table, the composition of the data seed is shuffled using a combination of linear and nonlinear calculations.

[0076] Specifically, considering the hierarchical relationship of particles, such as Figure 5 The wl information is used to shuffle the data seed composition of the low page, middle page, and up page.

[0077] This embodiment uses a dynamic seed update method, updating the seed value with each operation to prevent the writing of a large amount of similar data. The seed update uses a combination of linear and non-linear calculations. In a conventional circuit built with LFSR, a shift XOR operation is performed once per operation. This embodiment increases this to more than ten times and calls the sbox operation once to ensure that even if bad data is input, a highly randomized data output can be obtained.

[0078] Please see Figure 6 In the data path DP, the scrambling and descrambling modules have largely the same function; the main difference lies in the control logic at the circuit interface. The scrambling data is transmitted from the host to the Flash array; this process is called writing data (program data). Descrambling occurs when the host retrieves data from the Flash chip via commands (read data). The designed scrambling encoding and decoding circuit modules each consist of two parts: a seed generation module and a data scrambling module. The data scrambling module not only processes the data but also updates the seed. The seed generation module generates initial, configurable seed values ​​based on different scenarios.

[0079] The generation principle of Seeds: The generation of the initial key requires simple linear operations. The construction factors include descriptor content, hardware and software interaction information, meta content, internal offset counter, etc.

[0080] This embodiment uses two sets of data scrambling circuits: the older linear scrambling circuit based on LFSR and the new nonlinear scrambling scheme based on SBOX. The former uses linear scrambling, which has low complexity and is suitable for most application scenarios; the latter has higher circuit complexity, combining linear and nonlinear operations, and can be used as a means of protecting important data. The firmware developers have the right to use these two circuit logics and can select which circuit to use for data scrambling by configuring registers according to the actual situation.

[0081] Please see Figure 7 The circuit incorporates four currently compatible seed construction schemes and a circuit structure based on a linear feedback shift register (LFSR). It adds a new seed construction strategy and a new data scrambling circuit, along with new registers, allowing the host to choose from five seed generation schemes and two data scrambling schemes. This increases circuit flexibility and compatibility, while also further enhancing data protection capabilities.

[0082] The five seed schemes are: a scheme where the seed is generated entirely by hardware; a scheme that constructs a seed index and performs a lookup table mapping; a scheme where the high and low bits of the seed are constructed by both hardware and software (equivalent to granting some control over seed construction to the software); a seed scheme with meta information; and a scheme that performs secondary scrambling on the seed value. The use of these schemes can be controlled by register switches, with one scheme selected at a time. Software developers can configure these schemes based on actual usage.

[0083] The register configuration module allows software configuration of the offset and its calculation method, and can modify the size and number of data items written at once. The key generation module generates the corresponding seed (key) content through this control logic. The seed table is currently configured with 128 32-bit numbers, and the specific values ​​can be configured according to different manufacturers' NAND flash memory and NAND flash memory upgrades.

[0084] Please see Figure 8To meet the parallelism requirements of the circuit computation, the scrambling circuit needs to compute 128 bits of data per cycle. This embodiment calls the characteristic polynomial: X³² + X²⁶ + X²³ + X²² + X¹⁶ + X¹² + X¹¹ + X¹⁰ + X⁸ + X⁷ + X⁵ + X⁴ + X² + X + 1, i.e., poly = 0x04C11DB7. This embodiment uses the parallelism derivation based on Galios LFSR, with the poly value as the column of the matrix (rows and columns can be transposed, depending on the product relationship between the matrix and the seed). The identity matrix is ​​used for padding, and the remaining space is filled with zeros, thus constructing the basic matrix. The corresponding circuit structure is generated according to the input / output data bit width (128 bits) and the polynomial bit width (32 bits). The expanded matrix is ​​multiplied by the seed vector generated by the previous circuit to obtain the seed output of the first round. The second round uses the output of the first stage to multiply the expanded matrix. Starting from the second round, simplification is performed. Each time, the result is an initial seed vector multiplied by a dynamic matrix. The first column of this matrix represents the expanded result of each round, which is also the output of the data scrambling circuit. One cycle can complete 128-bit data computation, saving circuit storage space and improving parallel computing speed.

[0085] Please see Figure 9 Circuits built on LFSR can be implemented with high parallelism, and adding them to the circuit will not affect the data transmission rate. Furthermore, the circuit structure occupies less space compared to encoding modules and standard encryption modules. However, for extreme cases where the generated seed contains a large number of "0"s in the data, the linear circuit structure cannot achieve ideal data randomization. Therefore, the construction of the seed needs more stringent constraints, such as generating a non-linear seed parameter table and calculating to make the "0"s and "1"s in the data more discrete.

[0086] In one embodiment, please refer to Figure 2 The above-mentioned step S150 may include steps S151 to S152.

[0087] S151. Combining the granular hierarchy relationship corresponding to the seed table, a combination of linear and nonlinear calculations is used to perform a three-stage pipelined initial shuffling of the input data seed.

[0088] Please see Figure 10The initial scrambling process described above utilizes numerous linear logic operations, such as the linear logic operation units shown in the diagram. Each level of the linear logic operation unit circuit involves 9 to 12 numerical shift operations. The number of calculations varies between different levels. This operational logic ensures that each bit of the data input is processed multiple times, providing effective scrambling even for bad seed inputs. For example, if the data input bit width is 128 bits, but the actual input is 128'h25, containing a large number of "0"s, the linear logic operation unit in the diagram will scatter the lower 8 bits of valid data across various positions and perform logical XOR and logical shift operations. This ensures that the number of "0"s and "1"s in the output is roughly equal.

[0089] The data width for computation is 64 bits. The circuit splits the data into three blocks, each ranging from 16 to 32 bits in size, with some overlap between the blocks. Non-linear logic operations are introduced for data permutation, utilizing the AES encryption algorithm's sbox (256 permutation units, each a byte). During the operation, the data is first split and then merged; 128 bits of data requires 16 calls to the sbox lookup table. Randomization is increased for special data and extreme seed conditions. After extensive algorithm testing, good data scrambling results are achieved.

[0090] A circuit designed according to these requirements would be larger than a conventional scrambling circuit and would increase the data scrambling operation cycle, making it difficult to implement without changing the circuit manufacturing process. Therefore, it is necessary to... Figure 10 The calculation process is broken down and a scrambling circuit is designed using a pipeline.

[0091] In one embodiment, please refer to Figure 3 The above-mentioned step S151 may include steps S1511 to S1513.

[0092] S1511. Perform linear logical operations on the input data based on the granular hierarchy relationship corresponding to the seed table, and split the results of the operations to obtain the split results.

[0093] In this embodiment, the splitting result refers to the result formed by performing linear logical operations on the input data and splitting the result of the operations.

[0094] S1512. Perform linear logic operations on the splitting result to obtain a second operation result.

[0095] In this embodiment, the second operation result refers to the result formed after performing linear logical operations on the split result.

[0096] S1513. The second operation result is subjected to nonlinear permutation of the sbox of the AES encryption algorithm, and linear logic operation and data merging are performed.

[0097] In this embodiment, the linear logic operation includes 9 to 12 numerical shift operations.

[0098] Please see Figure 11 and Figure 12 SSD controller chips have extremely stringent bandwidth requirements for data transmission. The scrambling strategy proposed in this solution improves the randomization of data, but also increases the design complexity of the chip circuit. At the initial design stage, the characteristics of different chip process libraries from 6nm to 12nm were considered, and a three-stage pipeline design was adopted. While ensuring that data bandwidth was not affected, a scrambling scheme with altered complexity was proposed.

[0099] Figure 11 There are three operation units: 1, 2, and 3. Each operation consists of a complete 128-bit data operation. The first-level operation unit involves data input, a single call to a linear operation unit, and data splitting. The second-level operation unit calculates two data blocks, calling a linear operation unit (the unit with the largest number of calculations). The third-level operation unit calls the sbox, a single call to a linear operation unit, and data merging. Figure 13 This demonstrates that pipelined implementation is a space-for-time tradeoff strategy. The designed circuit, analyzed using EDA tools, meets timing requirements. The completed circuit can also complete one data output per clock cycle without affecting system throughput.

[0100] S152. Based on the writing characteristics, the result of the initial scrambling is scrambled a second time.

[0101] Specifically, an offset is added to the initial scrambling result to perform a second scrambling on the initial scrambling result.

[0102] In one embodiment, please refer to Figure 4 The above step S152 may include steps S1521 to S1524.

[0103] S1521. Add an offset to the codeword address and page address of the initial scrambled result;

[0104] S1522. Perform linear operations on the codeword address and page address to modify the codeword address and page address;

[0105] S1523. Perform linear operations on the modified codeword address and page address based on the number of read / write operations;

[0106] S1524. Modify the codeword address and page address after the linear operation a second time.

[0107] Specifically, secondary scrambling of the data is applied in the seed construction stage. As described previously, the scrambling circuit is divided into two parts: seed construction and data scrambling. Five circuit schemes were written for seed construction, and data scrambling integrates both linear and nonlinear scrambling strategies. The initial design purpose of secondary scrambling in the seed is to protect critical data. The basic idea is to introduce new conditions to increase the offset of the seed. The control logic introduced here is the level of the written data in the granular space and the number of times this storage space is used. In step S152 above, the codeword address or the page address can be modified separately.

[0108] Here, a codeword represents a complete data frame, a page is a storage unit of a flash chip, and slc~qlc represent different levels of the flash chip. Additionally, to increase the flexibility of seed construction, we allocate a certain amount of space during construction for the host side, allowing modification of the seed's composition.

[0109] The circuit was constructed using the method described above. After the circuit was completed, its performance was tested, including timing analysis, area analysis, and statistical analysis of the data scrambling effect. The following are the test results.

[0110] The test objects include scrambling tests based on linear feedback shift registers (LFSR), scrambling tests based on sboxes, tests for constructing fixed seeds and round seeds, tests for seeds with different bit widths, tests for random data input and "bad" data, and tests for constructing seed tables.

[0111] Record the total number of "0"s and "1"s in the scrambled data, the number of consecutive "0"s and "1"s within a codeword, and the distribution of "0"s and "1"s in each round of data, as follows: Figure 13 As shown.

[0112] The test data consisted of a single codeword. The average number of "0"s and "1"s in the output data was calculated. Within approximately 32,000 bits, the difference in the number of "0"s and "1"s was only a few hundred bits. Overall, the difference was small. Even under extreme test conditions, where the input data consisted entirely of "1"s and "0"s, this scrambling method still produced relatively good discrete data output. Figure 14 As shown.

[0113] The test records the average number of consecutive "0" and "1" occurrences in the codeword. It can be seen that sequences with two consecutive "0" and "1" appear thousands of times, sequences with eight consecutive "0" and "1" appear hundreds of times, but sequences with 15 consecutive "0" and "1" appear only a few times. This shows that the scrambled data has a random distribution characteristic. For example... Figure 15 As shown.

[0114] Test the data scrambling effect and seed iteration effect for each clock cycle, such as Figure 17 As shown, the "0" and "1" in the data are relatively evenly distributed, and there will be no situation where the signal remains at a high or low level for a long time within a data frame. The total number of "0" and "1" in the data in each clock cycle increases linearly.

[0115] The aforementioned nonlinear scrambling method enhances resistance to linear and differential attacks by employing the sbox from the international standard encryption algorithm AES when scrambling the data seed structure. This improves the scrambling effect even under worst-case scrambling seed conditions. Furthermore, it utilizes numerous shift registers and XOR logic to increase the random distribution of the seed in each round. A three-stage pipeline architecture is adopted to increase system bandwidth while maintaining circuit complexity, satisfying the seed differentiation between different levels of the granular material, the seed differentiation of different codewords within a single page of the flash granular material, and adding secondary scrambling to satisfy seed differentiation for n consecutive read / write operations within the same address space. This additional differentiation for different levels of the granular material and different read / write operations prevents the scrambling seed from having too small a difference, resulting in better data diffusion during the scrambling process.

[0116] Figure 16 This is a schematic block diagram of a nonlinear scrambling device 300 provided in an embodiment of the present invention. Figure 16 As shown, corresponding to the above nonlinear scrambling method, the present invention also provides a nonlinear scrambling device 300. This nonlinear scrambling device 300 includes a unit for performing the above-described nonlinear scrambling method, and the device can be configured in a server. Specifically, please refer to... Figure 16 The nonlinear scrambling device 300 includes a first calculation unit 301, a second calculation unit 302, a construction unit 303, a recording unit 304, and a scrambling unit 305.

[0117] The first calculation unit 301 is used to calculate the dynamic variable ppa value using the smallest write address units of different manufacturers and sizes; the second calculation unit 302 is used to calculate the values ​​of lpa and lba with offset using a counter; the construction unit 303 is used to construct a configurable seed table; the recording unit 304 is used to record the number of reads and writes using the content of the issued descriptor in combination with the life cycle of the particle, so as to modify the index of the seed table; the scrambling unit 305 is used to scramble the composition of the data seed by combining linear and nonlinear calculations in combination with the particle hierarchy relationship corresponding to the seed table.

[0118] In one embodiment, such as Figure 17 As shown, the scrambling unit 305 includes an initial scrambling subunit 3051 and a secondary scrambling subunit 3052.

[0119] The initial scrambling subunit 3051 is used to construct the initial scrambling data seed by combining linear and nonlinear calculations based on the granular hierarchy relationship corresponding to the seed table; the secondary scrambling subunit 3052 is used to perform secondary scrambling on the result of the initial scrambling according to the writing characteristics.

[0120] In one embodiment, such as Figure 18 As shown, the initial scrambling subunit 3051 includes a first-level operation module 30511, a second-level operation module 30512, and a third-level operation module 30513.

[0121] The first-level operation module 30511 is used to perform linear logical operations on the input data in combination with the granular hierarchy relationship corresponding to the seed table, and split the result of the operation to obtain the split result; the second-level operation module 30512 is used to perform linear logical operations on the split result to obtain the second operation result; the third-level operation module 30513 is used to perform nonlinear permutation on the second operation result by calling the sbox of the AES encryption algorithm, and perform linear logical operations and data merging.

[0122] In one embodiment, the secondary scrambling subunit 3052 is used to add an offset to the result of the initial scrambling in order to perform secondary scrambling on the result of the initial scrambling.

[0123] In one embodiment, such as Figure 19 As shown, the secondary scrambling subunit 3052 includes an addition module 30521, a first operation module 30522, a second operation module 30523, and a secondary modification module 30524.

[0124] An additional module 30521 is added to the codeword address and page address of the initial scrambled result by adding an offset; a first operation module 30522 is used to perform linear operations on the codeword address and page address to modify them; a second operation module 30523 is used to perform linear operations on the modified codeword address and page address based on the number of read and write operations; and a secondary modification module 30524 is used to perform secondary modifications on the codeword address and page address after the linear operations.

[0125] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above-mentioned nonlinear scrambling device 300 and each unit can be referred to the corresponding description in the foregoing method embodiments. For the sake of convenience and brevity, it will not be repeated here.

[0126] The aforementioned nonlinear scrambling device 300 can be implemented as a computer program, which can, for example... Figure 20 It runs on the computer device shown.

[0127] Please see Figure 20 , Figure 20 This is a schematic block diagram of a computer device provided in an embodiment of this application. The computer device 500 can be a server, wherein the server can be a standalone server or a server cluster composed of multiple servers.

[0128] See Figure 20 The computer device 500 includes a processor 502, a memory, and a network interface 505 connected via a system bus 501. The memory may include a non-volatile storage medium 503 and internal memory 504.

[0129] The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions that, when executed, cause the processor 502 to perform a non-linear scrambling method.

[0130] The processor 502 provides computing and control capabilities to support the operation of the entire computer device 500.

[0131] The internal memory 504 provides an environment for the execution of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a non-linear scrambling method.

[0132] This network interface 505 is used for network communication with other devices. Those skilled in the art will understand that... Figure 20 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 500 to which the present application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0133] The processor 502 is used to run a computer program 5032 stored in the memory to perform the following steps:

[0134] The dynamic variable ppa value is calculated using the smallest write address unit of different manufacturers and sizes; the values ​​of lpa and lba with offset are calculated using counters; a configurable seed table is constructed; the read and write counts are recorded using the content of the issued descriptor in conjunction with the life cycle of the granules, so as to modify the index of the seed table; and the composition of the data seed is shuffled by combining linear and nonlinear calculations based on the granule hierarchy relationship corresponding to the seed table.

[0135] In one embodiment, when the processor 502 implements the step of shuffling the data seed by combining linear and nonlinear calculations to establish the granular hierarchical relationship corresponding to the seed table, the specific steps are as follows:

[0136] Based on the granular hierarchy relationship corresponding to the seed table, a combination of linear and nonlinear calculations is used to construct the initial scrambling of the input data seed in a three-stage pipelined manner; the initial scrambling result is then subjected to secondary scrambling according to the writing characteristics.

[0137] In one embodiment, when the processor 502 constructs the initial data seed by combining linear and nonlinear calculations on the input data using a three-stage pipelined approach, the specific steps are as follows:

[0138] The input data is subjected to linear logical operations based on the granular hierarchy of the seed table, and the results are split to obtain a split result; linear logical operations are performed on the split result to obtain a second result; the second result is subjected to nonlinear permutation of the sbox of the AES encryption algorithm, followed by linear logical operations and data merging.

[0139] The linear logic operation includes 9 to 12 numerical shift operations.

[0140] In one embodiment, when implementing the step of performing a second scrambling on the result of the initial scrambling based on the write characteristics, the processor 502 specifically implements the following steps:

[0141] An offset is added to the initial scrambled result to perform a second scrambling.

[0142] In one embodiment, when the processor 502 implements the step of adding an offset to the initial scrambling result to perform a second scrambling on the initial scrambling result, the following steps are specifically implemented:

[0143] Add an offset to the codeword address and page address of the initial scrambled result; perform linear operations on the codeword address and page address to modify them; perform linear operations on the modified codeword address and page address based on the number of reads and writes; and then modify the codeword address and page address after the linear operations a second time.

[0144] It should be understood that in the embodiments of this application, the processor 502 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0145] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0146] Therefore, the present invention also provides a storage medium. This storage medium can be a computer-readable storage medium. The storage medium stores a computer program, wherein when executed by a processor, the computer program causes the processor to perform the following steps:

[0147] The dynamic variable ppa value is calculated using the smallest write address unit of different manufacturers and sizes; the values ​​of lpa and lba with offset are calculated using counters; a configurable seed table is constructed; the read and write counts are recorded using the content of the issued descriptor in conjunction with the life cycle of the granules, so as to modify the index of the seed table; and the composition of the data seed is shuffled by combining linear and nonlinear calculations based on the granule hierarchy relationship corresponding to the seed table.

[0148] In one embodiment, when the processor executes the computer program to implement the step of shuffling the data seed structure by combining linear and nonlinear calculations to establish the granular hierarchical relationship corresponding to the seed table, the specific implementation is as follows:

[0149] Based on the granular hierarchy relationship corresponding to the seed table, a combination of linear and nonlinear calculations is used to construct the initial scrambling of the input data seed in a three-stage pipelined manner; the initial scrambling result is then subjected to secondary scrambling according to the writing characteristics.

[0150] In one embodiment, when the processor executes the computer program to construct the initial data seed by combining linear and nonlinear calculations on the input data using a three-stage pipelined approach, the specific steps are as follows:

[0151] The input data is subjected to linear logical operations based on the granular hierarchy of the seed table, and the results are split to obtain a split result; linear logical operations are performed on the split result to obtain a second result; the second result is subjected to nonlinear permutation of the sbox of the AES encryption algorithm, followed by linear logical operations and data merging.

[0152] The linear logic operation includes 9 to 12 numerical shift operations.

[0153] In one embodiment, when the processor executes the computer program to implement the step of performing a second scrambling on the result of the initial scrambling based on the write characteristics, it specifically implements the following steps:

[0154] An offset is added to the initial scrambled result to perform a second scrambling.

[0155] In one embodiment, when the processor executes the computer program to implement the step of adding an offset to the initial scrambling result to perform a second scrambling on the initial scrambling result, the specific implementation includes the following steps:

[0156] Add an offset to the codeword address and page address of the initial scrambled result; perform linear operations on the codeword address and page address to modify them; perform linear operations on the modified codeword address and page address based on the number of reads and writes; and then modify the codeword address and page address after the linear operations a second time.

[0157] The storage medium can be any computer-readable storage medium capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0158] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0159] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0160] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the device of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0161] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0162] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method of non-linear scrambling, characterized by, include: The dynamic variable ppa value is calculated by using the smallest write address unit of different manufacturers and sizes; The values ​​of offsets lpa and lba are calculated using counters; Construct a configurable seed table; Based on the lifecycle of the granules, the content of the issued descriptor is used to record the number of reads and writes in order to modify the index of the seed table; By combining linear and nonlinear calculations to disrupt the composition of data seeds based on the granular hierarchy relationships corresponding to the seed table; The process of shuffling the data seed structure by combining linear and non-linear calculations, based on the granular hierarchy relationships corresponding to the seed table, includes: Based on the granular hierarchy relationship corresponding to the seed table, a combination of linear and nonlinear calculations is used to initially shuffle the input data seed in a three-stage pipeline manner. The initial scrambling result is then scrambled a second time based on the writing characteristics. The process of constructing the initial data seed by combining linear and nonlinear calculations based on the granular hierarchy relationship corresponding to the seed table involves a three-stage pipelined initial shuffling of the input data, including: The input data is subjected to linear logical operations based on the granular hierarchy of the seed table, and the results of the operations are then split to obtain the split results. Perform linear logic operations on the splitting result to obtain a second operation result; The second operation result is used to perform non-linear permutation of the sbox of the AES encryption algorithm, followed by linear logic operations and data merging.

2. The method of claim 1, wherein, The linear logic operation includes 9 to 12 numerical shift operations.

3. The nonlinear scrambling method according to claim 1, characterized in that, The second scrambling of the initial scrambling result based on the write characteristics includes: An offset is added to the initial scrambled result to perform a second scrambling.

4. A method of non-linear scrambling according to claim 3, wherein, The addition of an offset to the initial scrambling result to perform a secondary scrambling includes: Add an offset to the codeword address and page address of the initial scrambled result; Perform linear operations on the codeword address and page address to modify the codeword address and page address; Based on the number of reads and writes, perform linear operations on the modified codeword address and page address; The codeword address and page address after the linear operation are modified a second time.

5. A nonlinear scrambling device for performing the nonlinear scrambling method of claim 1, wherein include: The first calculation unit is used to calculate the dynamic variable ppa value using the smallest write address unit of different manufacturers and sizes; The second calculation unit is used to calculate the values ​​of offsets lpa and lba using counters; Construction unit, used to construct a configurable seed table; The recording unit is used to record the number of reads and writes based on the lifecycle of the granule and the content of the issued descriptor, so as to modify the index of the seed table. Scrambling units are used to combine the granular hierarchy relationships corresponding to the seed table with linear and nonlinear calculations. The method of combining disrupts the composition of the data seed; The scrambling unit includes: The initial shuffling sub-unit is used to construct the initial shuffling of the input data seed by combining linear and nonlinear calculations based on the granular hierarchy relationship corresponding to the seed table. The secondary scrambling subunit is used to perform secondary scrambling on the result of the initial scrambling based on the writing characteristics.

6. A computer device, comprising: The computer device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method as described in any one of claims 1 to 4.

7. A storage medium, characterized by The storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 4.

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