A random access memory

Abstract

The application discloses a random memory, which comprises a storage unit, a word line, a complementary bit line pair, a first input-output line and a second input-output line, which are connected with the bit line pair, and when the corresponding column gating module of the bit line pair is turned on, the bit line pair is connected with the input-output line pair through the turned-on column gating module; and an initialization module connected between the first input-output line and the second input-output line, wherein when a continuous writing operation is performed, if the next pen writing operation does not perform data input shielding, in the equalization stage, the first input-output line and the second input-output line are connected and share charges so that the voltage on both is the shared voltage; if the next pen writing operation performs data input shielding, in the equalization stage, the voltage on the first input-output line and the second input-output line is pre-charged to the working voltage and is connected and shares charges with each other, and after the equalization stage, the working voltage is maintained to shield the data writing to the bit line pair. In the above manner, the power consumption of the circuit can be reduced.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a random access memory. Background Technology

[0002] The memory array consists of multiple word lines (WL), multiple bit lines (BL), and multiple memory cells, each of which is connected to one word line (WL) and one bit line (BL).

[0003] Furthermore, the storage array also includes input / output pairs (IO / IO#). During data reading / writing, the input / output pairs (IO / IO#) and the selected bit pairs (BL / BL#) are connected through column gating circuits to perform data exchange (chargeshare), thereby realizing data reading / writing.

[0004] During continuous write operations, after each data write, there is an equalization phase that charges the input / output line pairs (IO / IO#). Summary of the Invention

[0005] To address the aforementioned problems, this application provides a random access memory that can reduce circuit power consumption.

[0006] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a random access memory (RAM) including: a memory cell; word lines; complementary bit line pairs; input / output line pairs, including a first input / output line and a second input / output line, for connecting to the bit line pairs. When the column gating module corresponding to the bit line pair is turned on, the bit line pair is connected to the input / output line pair through the turned-on column gating module; an initialization module is connected between the first input / output line and the second input / output line. During a continuous write operation, if the next write operation does not involve data input masking, in the equalization phase, the first input / output line and the second input / output line are connected to share charge so that the voltage on both is a shared voltage; if the next write operation involves data input masking, in the equalization phase, the voltage on the first input / output line and the second input / output line are pre-charged to the operating voltage and connected to each other to share charge, and the operating voltage is maintained after the equalization phase to mask data writing to the bit line pairs.

[0007] The initialization module includes: a first equalization unit, disposed between the first input / output line and the second input / output line, to connect the first input / output line and the second input / output line based on a first equalization signal; and a pre-charge unit, disposed between the first input / output line and the second input / output line, to pre-charge the first input / output line and the second input / output line to the operating voltage based on a pre-charge control signal.

[0008] The initialization module further includes: a logic gate control unit connected to the precharge unit, which generates and outputs a precharge control signal to the precharge unit based on the write operation identifier signal, the input data masking signal and the first equalization signal.

[0009] The initialization module further includes a second equalization unit, which is disposed between the first input / output line and the second input / output line to cooperate with the first equalization unit to connect the first input / output line and the second input / output line based on the second equalization signal.

[0010] The first equalization unit includes: a first switch, whose control terminal receives a first equalization signal, whose first path terminal is connected to a first input / output line, and whose second path terminal is connected to a second input / output line; wherein, during continuous write operation, if the next write operation does not involve data input shielding, during the equalization phase, the first equalization signal controls the first switch to turn on, and the first input / output line and the second input / output line are connected to share charge.

[0011] The second equalization unit includes a second switch, whose control terminal receives a second equalization signal, whose first path terminal is connected to a first input / output line, and whose second path terminal is connected to a second input / output line. During continuous write operations, if the next write operation involves data input shielding, the second equalization signal controls the second switch to turn on during the equalization phase, and the first input / output line and the second input / output line are connected to share charge.

[0012] The pre-charge unit includes: a third switch, whose control terminal receives a pre-charge control signal, whose first path terminal receives the operating voltage, and whose second path terminal is connected to the first input / output line; and a fourth switch, whose control terminal receives a pre-charge control signal, whose first path terminal receives the operating voltage, and whose second path terminal is connected to the second input / output line. During continuous write operations, if the next write operation involves data input masking, in the equalization phase, the pre-charge control signal controls the third and fourth switches to turn on, and the voltages on the first and second input / output lines are pre-charged to the operating voltage.

[0013] The logic gate control unit includes: a NOT logic gate, whose input terminal receives an input data shielding signal; a first NAND logic gate, whose first input terminal is connected to the output terminal of the NOT logic gate, and whose second input terminal receives a write operation flag signal; and a second NAND logic gate, whose first input terminal receives a first equalization signal, whose second input terminal is connected to the output terminal of the first NAND logic gate, and whose output terminal outputs a precharge control signal.

[0014] The first equalization signal and the second equalization signal are inverted.

[0015] The random access memory is a dynamic random access memory.

[0016] The beneficial effects of this application are as follows: The random access memory (RAM) provided by this application includes: a memory cell; word lines; complementary bit line pairs; a first input / output line and a second input / output line for connecting to the bit line pairs. When the column gating module corresponding to the bit line pair is turned on, the bit line pair is connected to the input / output line pair through the turned-on column gating module; an initialization module is connected between the first input / output line and the second input / output line. During a continuous write operation, if the next write operation does not involve data input masking, in the equalization phase, the first input / output line and the second input / output line are connected to share charge so that the voltage on both is a shared voltage. If the next write operation involves data input masking, in the equalization phase, the voltage on the first input / output line and the second input / output line are pre-charged to the operating voltage and connected to each other to share charge. After the equalization phase, the operating voltage is maintained to mask data writing to the bit line pairs. Through the above method, since no charging is performed when data masking is not performed, and only charge sharing is performed, the power consumption of the circuit is reduced, further reducing the overall power consumption of the RAM and improving the performance of the RAM. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0018] Figure 1 This is a schematic diagram of the storage array structure of the random access memory provided in this application;

[0019] Figure 2 yes Figure 1 A schematic diagram of the structure of an embodiment of the first initialization module;

[0020] Figure 3 yes Figure 1 A schematic diagram of the structure of an embodiment of the medium-sensitivity amplification module;

[0021] Figure 4 yes Figure 3 A circuit diagram of an embodiment of a medium-sensitivity amplification module;

[0022] Figure 5 yes Figure 1 A schematic diagram of one embodiment of the middle column selection circuit;

[0023] Figure 6 yes Figure 1 A schematic diagram of the first embodiment of the input / output circuit;

[0024] Figure 7This is a schematic diagram of the potential trend of an embodiment of the random access memory provided in this application;

[0025] Figure 8 yes Figure 6 Corresponding signal diagram;

[0026] Figure 9 yes Figure 1 A schematic diagram of the second embodiment of the input / output circuit;

[0027] Figure 10 yes Figure 9 Corresponding signal diagram;

[0028] Figure 11 yes Figure 1 A schematic diagram of the third embodiment of the input / output circuit;

[0029] Figure 12 yes Figure 11 Corresponding signal diagram;

[0030] Figure 13 This is a schematic diagram of the random access memory provided in this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the random access memory array provided in this application. The memory array 100 includes multiple word lines (WL), multiple bit lines (BL), and multiple memory cells 110, wherein each memory cell 110 is connected to a word line WL and a bit line BL.

[0034] In one embodiment where the random access memory is Dynamic Random Access Memory (DRAM), each memory cell 110 includes an access switch and a storage capacitor. The storage capacitor represents logical "1" and "0" by the amount of charge stored within it, or the voltage difference across its terminals. The on / off state of the access switch determines whether reading and rewriting of the information stored in the storage capacitor is permitted or prohibited.

[0035] Specifically, the word line WL determines whether the access switch is on or off, and the bit line BL is the only channel for external access to the storage capacitor. When the access switch is on, external access can read or write to the storage capacitor through the bit line BL.

[0036] In one embodiment, the common terminal of the storage capacitor is connected to Vcc / 2.

[0037] When the information stored in the storage capacitor is "1", the voltage at the other end of the storage capacitor is Vcc, and the charge stored at this time is:

[0038] Q = +Vcc / 2*C

[0039] When the information stored in the storage capacitor is "0", the voltage at the other end of the storage capacitor is 0. At this time, the stored charge is:

[0040] Q = -Vcc / 2*C

[0041] Furthermore, the storage array 100 also includes a first initialization module 120, a sensitive amplification module 130 (SenseAmplifier, SA), a column selection circuit 140, and an input / output circuit 150.

[0042] The first initialization module 120 is connected to a pair of complementary bit lines (BL / BL#) to charge the target bit line BL and the complementary bit line BL# to the initialization potential during the precharge phase. The sensitive amplification module 130 is connected to a pair of complementary bit lines (BL / BL#) to amplify the logic potential on the target bit line BL to a corresponding strong potential when the memory cell 110 connected to the target bit line BL is turned on by the word line (WL). The input / output circuit 150 includes a pair of complementary input / output lines (IO / IO#), and the column selection circuit 140 includes multiple column gating modules 141 and a column gating signal generation circuit 142. Each column gating module 141 is connected to a pair of complementary bit lines to determine whether the current complementary bit line pair is selected with the connected complementary input / output line pair (IO / IO#) based on the corresponding column selection signal generated by the column gating signal generation circuit 142.

[0043] See Figure 2 , Figure 2 yes Figure 1 A schematic diagram of the structure of an embodiment of the first initialization module 120 is shown. The first initialization module 120 includes switches T1, T2 and T3. The control terminals of switches T1, T2 and T3 receive a first pre-charge control signal EQ1. The first path terminal of switch T1 is connected to the target bit line BL. The first path terminal of switch T2 is connected to the complementary bit line BL#. The second path terminals of switches T1 and T2 are connected to the initialization potential Vref (in one embodiment, Vref = 1 / 2Vcc). The first path terminal of switch T3 is connected to the target bit line BL. The second path terminal of switch T3 is connected to the complementary bit line BL#.

[0044] During the precharge phase, the first precharge control signal EQ1 turns on switches T1 and T2, charging the target bit line BL and complementary bit line BL# with the initialization potential Vref, so that the potentials of the target bit line BL and complementary bit line BL# are at the initialization potential. Further, the first precharge control signal EQ1 turns on switch T3, ensuring that the potentials of the target bit line BL and complementary bit line BL# remain consistent.

[0045] Optionally, the switches T1, T2 and T3 mentioned above can be nMOS transistors.

[0046] See Figure 3 , Figure 3 yes Figure 1 A schematic diagram of the structure of an embodiment of a sensitive amplification module 130, which includes a first inverting unit 131 and a second inverting unit 132.

[0047] The first inverting unit 131 is connected between the target bit line BL and the complementary bit line BL#, wherein, when the memory cell 110 connected to the target bit line BL is turned on, the target bit line voltage V on the target bit line BL is... BL Based on the logic potential stored in storage cell 110 shifting from the initialization potential Vref, the first inverting cell 131 adjusts the target bit line voltage V based on the shifted value. BL Flip the complementary bit line voltage V on the complementary bit line BL#. BL# Pull to the strong potential of the first logic.

[0048] The second inverting unit 132 is connected between the complementary bit line BL# and the target bit line BL, wherein the complementary bit line voltage V on the complementary bit line BL# is... BL# When pulled to a strong potential in the first logic, the second inverting unit 132 operates based on the complementary bit line voltage V. BL# Flip, and change the target bit line voltage V on the target bit line BL. BL Pull to a strong potential of the second logic, which is the opposite of the first logic.

[0049] See also Figure 3 and Figure 4 , Figure 4 yes Figure 3 A circuit diagram of an embodiment of the sensitive amplification module, wherein the first inverting unit 131 includes an nMOS transistor T4 and a pMOS transistor T5, and the second inverting unit 132 includes an nMOS transistor T6 and a pMOS transistor T7.

[0050] See Figure 5 , Figure 5 yes Figure 1 A schematic diagram of one embodiment of the column selection circuit is shown. The column selection circuit 140 includes a column selection signal generation circuit 142 and a plurality of column selection modules 141. Each column selection module 141 is connected to a pair of complementary bit line pairs (BL / BL#) to determine whether the current complementary bit line pair (BL / BL#) is selected with the connected complementary input / output line pair (IO / IO#) based on the corresponding column selection signal YS generated by the column selection signal generation circuit 142.

[0051] The column gating module 141 includes switches T8 and T9. The control terminals of switches T8 and T9 are connected to the column gating signal generation circuit 142 to receive the corresponding column gating signal YS. The first path terminal of switch T8 is connected to the target bit line BL, and the second path terminal is connected to the first input / output line IO. The first path terminal of switch T9 is connected to the complementary bit line BL#, and the second path terminal is connected to the second input / output line IO#.

[0052] Specifically, when the column selection signal YS generated by the column selection signal generation circuit 142 controls the switches T8 and T9 to turn on, the target bit line BL is connected to the first input / output line IO, and the complementary bit line BL# is connected to the second input / output line IO#, so as to realize the selection of the complementary bit line pair (BL / BL#) and the complementary input / output line pair (IO / IO#): during the write operation, the complementary bit line pair (BL / BL#) is charged / discharged through the complementary input / output line pair (IO / IO#) to rewrite the voltage on the complementary bit line pair (BL / BL#) by changing the signal on the complementary input / output line pair (IO / IO#); during the read operation, the signal on the complementary bit line pair (BL / BL#) is output to the complementary input / output line pair (IO / IO#).

[0053] Optionally, the switches T8 and T9 mentioned above can be nMOS transistors.

[0054] See Figure 6 , Figure 6 yes Figure 1A schematic diagram of the structure of the first embodiment of the input / output circuit is shown. The input / output circuit 150 includes a second initialization module 151.

[0055] The second initialization module 151 includes switches T10, T11, and T12. The control terminals of switches T10, T11, and T12 receive a second pre-charge control signal EQ2. The first path terminal of switch T10 is connected to the first input / output line IO, the first path terminal of switch T11 is connected to the second input / output line IO#, the second path terminals of switches T10 and T11 are connected to the reference potential Vcc, the first path terminal of switch T12 is connected to the first input / output line IO, and the second path terminal of switch T12 is connected to the second input / output line IO#.

[0056] During the initialization phase of the input / output circuit 150, the second pre-charge control signal EQ2 controls switches T10 and T11 to turn on, charging the first input / output line IO and the second input / output line IO# with the reference voltage Vcc, so that the potentials of the first input / output line IO and the second input / output line IO# are equal to the reference potential Vcc. Further, the second pre-charge control signal EQ2 controls switch T12 to turn on, ensuring that the potentials of the first input / output line IO and the second input / output line IO# are consistent. After the sensitive amplification module 130 amplifies the logic potential read from the complementary bit line pair (BL / BL#) and pulls it to a strong "0" or strong "1", the input / output circuit 150 can connect to the complementary bit line pair (BL / BL#) through the complementary input / output line pair (IO / IO#) to complete read / write operations.

[0057] Optionally, the switches T10, T11 and T12 mentioned above can be nMOS transistors.

[0058] In combination with the above Figures 1-6 And see Figure 7 , Figure 7 This is a schematic diagram of the potential trend of a dynamic random access memory (DRAM) embodiment provided in this application. The following describes the working process of the DRAM in this embodiment using the read operation process, which includes a precharge stage, an access stage, a sense stage, and a restore stage.

[0059] precharge phase:

[0060] In this stage, the control signal EQ1 first turns on switches T1, T2, and T3, stabilizing the voltage on the target bit line BL and the complementary bit line BL# at Vref, assuming Vref = Vcc / 2. Then, the process proceeds to the next stage.

[0061] access phase:

[0062] After the precharge phase, the voltages on the target bit line BL and the complementary bit line BL# have stabilized at Vref. At this point, the access switch in memory cell 110 is turned on by controlling the word line WL (by applying voltage to the word line WL via the Active instruction). The positive charge stored in the storage capacitor in memory cell 110 (for example, if memory cell 110 stores "1", the voltage at one common terminal of the capacitor is Vcc / 2, and the voltage at the other terminal is Vcc) flows to the target bit line BL, causing the voltage of the target bit line BL to shift upwards to Vref+. If memory cell 110 stores "0", the voltage of the target bit line BL shifts downwards to Vref-. Then, the process proceeds to the next phase.

[0063] Sense stage:

[0064] Assuming storage cell 110 stores a "1": During the access phase, the voltage of the target bit line BL shifts upward to Vref+, and at this time, SAN is set to a strong logic "0" potential, while SAP is set to a strong logic "1" potential. Because the "1" stored in storage cell 110 pulls the voltage of the target bit line BL up to Vref+, while the voltage of the complementary bit line BL# remains at Vref, therefore... Figure 4 Switch T4 is more conductive than switch T6, and the voltage on the complementary bit line BL# is pulled to a strong logic "0" potential by SAP more quickly due to the conduction of T4. Since the gate of T7 is at a strong "0" and is conducting, the voltage on the target bit line BL is also pulled to a strong logic "1" potential by SAP more quickly due to the conduction of T7. Then switches T4 and T7 enter the conducting state, while switches T5 and T6 enter the cut-off state. Finally, the voltages of the target bit line BL and the complementary bit line BL# both enter a stable state, and the voltage on the target bit line BL correctly represents the information Bit ("1") stored by the storage capacitor in the memory cell 110.

[0065] Assuming memory cell 110 stores "0": During the access phase, the voltage of the target bit line BL shifts downward by Vref-. Since the voltage of the complementary bit line BL# is still Vref at this time, therefore... Figure 4Switch T5 is more conductive than switch T7, and the voltage on the complementary bit line BL# is pulled to a strong logic "1" potential by SAP more quickly due to the conduction of T5. Since the gate of T6 is at a strong "0" and is conducting, the voltage on the target bit line BL is also pulled to a strong logic "0" potential by SAN more quickly due to the conduction of T6. Then switches T5 and T6 enter the conducting state, while switches T4 and T7 enter the cut-off state. Finally, the voltages of the target bit line BL and the complementary bit line BL# both enter a stable state, and the voltage on the target bit line BL correctly represents the information Bit ("0") stored by the storage capacitor in the memory cell 110.

[0066] Restore phase:

[0067] After completing the sense phase, the target bit line BL is at a stable, strong potential Vcc of logic "1" or logic "0". At this time, the target bit line BL charges or discharges the storage capacitor in the storage cell 110. After a specific period of time, the charge of the storage capacitor can be restored to the state before the read operation.

[0068] Finally, as Figure 5 As shown, the column strobe signal generation circuit controls the YS signal, causing switches T8 and T9 to enter the conducting state. This outputs a strong "1" or strong "0" signal on the target bit line BL to the IO line, allowing the external system to read the specific information. It is worth noting that the aforementioned restore phase is performed automatically during the word line WL's activation. Therefore, for read operations, the restore operation may also occur after the YS signal is activated.

[0069] The above process describes a complete read operation. The initial flow of a write operation is the same as that of a read operation, executing the precharge, access, sense, and restore phases. The difference lies in that the restore phase includes a write phase, and a write recovery operation is performed afterward, as detailed below:

[0070] like Figure 5 As shown, the column selection signal YS is controlled by the column selection signal generation circuit 142, causing switches T8 and T9 to enter the conducting state. The signal of the input / output line IO will rewrite the target bit line BL. At this time, if "0" is written, the target bit line BL will be pulled to the logic "0" potential, and the complementary bit line BL# will be pulled to the logic "1" potential; if "1" is written, the target bit line BL will be pulled to the logic "1" potential, and the complementary bit line BL# will be pulled to the logic "0" potential.

[0071] Then, write recovery is performed: after a specific time (i.e., tWR), when the charge of the storage capacitor in the storage cell 110 is discharged to the "0" state or charged to the "1" state by the voltage on the target bit line BL, the switch in the storage cell 110 can be turned off by controlling the word line WL, and the operation of writing "0" or "1" is completed.

[0072] Combination Figure 5 and Figure 6 During read / write operations, the column strobe signal generation circuit 142 generates a column strobe signal YS to control the corresponding column strobe module 141 (such as switches T8 and T9) to open, further connecting the bit line pair (BL / BL#) to the input / output line pair (IO / IO#). Data is then written to the corresponding bit line pair (BL / BL#) through the input / output line pair (IO / IO#). After reading and writing the bit line pair (BL / BL#), the input / output line pair (IO / IO#) is charged and equalized to a relatively high potential (logic high potential, generally Vcc) in preparation for the next read / write operation.

[0073] During continuous read / write operations in the high-frequency operating state of random access memory, the above-mentioned charging and equalization operations are performed after each read / write operation. This generates a lot of power consumption, causing the random access memory to overheat, carrier scattering to be enhanced, circuit speed to be reduced, and circuit performance to be affected.

[0074] Assuming switches T10, T11, and T12 are pMOS transistors, please refer to [further details]. Figure 8 , Figure 8 yes Figure 6 The corresponding signal diagram.

[0075] During continuous write operations, in the Equalize phase of each write operation cycle, the column strobe signal YS is at a logic low level, controlling the column strobe module 141 to turn off, and the input / output line pair (IO / IO#) is charged to a logic high level Vcc. When data needs to be written, the input / output line pair (IO / IO#) is driven high or low by the secondary sense amplifier (SSA), then the column strobe signal YS is switched to a logic high level, controlling the column strobe module 141 to turn on, transmitting the data information to the bit line pair BL / BL#, and further amplified by the sense amplifier module 130, the amplified data is written to the memory cell.

[0076] During continuous write operations, when some data has a data mask (DM) and does not need to be written to the memory cell, the input / output line pair (IO / IO#) remains at the logic high level Vcc after the Equalize phase ends. When the column strobe signal YS is switched to a logic high level and the column strobe module 141 is turned on, due to the limitation of the nMOS transistor in the column strobe module 141 transmitting "1", the strong "1" information of the input / output line pair (IO / IO#) will not be written to the bit line pair BL / BL#, and the data is masked.

[0077] See Figure 9 , Figure 9 yes Figure 1 A schematic diagram of the second embodiment of the input / output circuit is shown. The input / output circuit 150 includes input / output line pairs (IO / IO#) and a third initialization module 152.

[0078] The input / output line pair (IO / IO#) includes a first input / output line IO and a second input / output line IO#, which are used to connect with the bit line pair (BL / BL#). When the column gating module 141 corresponding to the bit line pair (BL / BL#) is turned on, the bit line pair (BL / BL#) is connected to the input / output line pair (IO / IO#) through the turned-on column gating module 141.

[0079] Specifically, the first input / output line IO is connected to the target bit line BL through the column gating module 141, and the second input / output line IO# is connected to the complementary bit line BL# through the column gating module 141.

[0080] The third initialization module 152 is connected between the first input / output line IO and the second input / output line IO#. During a continuous write operation, if the next write operation does not involve data input masking, in the equalization phase, the first input / output line IO and the second input / output line IO# are connected to share charge so that the voltage on both is a shared voltage. If the next write operation involves data input masking, in the equalization phase, the voltage on the first input / output line IO and the second input / output line IO# is pre-charged to the operating voltage (e.g., Vcc) and connected to share charge. After the equalization phase, the operating voltage is maintained to mask the data writing to the bit line pair (BL / BL#).

[0081] In one specific embodiment, the third initialization module 152 includes a first equalization unit 152a, a pre-charging unit 152b, a logic gate control unit 152c, and a second equalization unit 152d.

[0082] The first equalization unit 152a is disposed between the first input / output line IO and the second input / output line IO#, so as to connect the first input / output line IO and the second input / output line IO# based on the first equalization signal IOPREET.

[0083] The pre-charge unit 152b is disposed between the first input / output line IO and the second input / output line IO# to pre-charge the first input / output line IO and the second input / output line IO# to the operating voltage based on the pre-charge control signal. Furthermore, the logic gate control unit 152c is connected to the pre-charge unit 152b to generate and output a pre-charge control signal to the pre-charge unit 152b based on the write operation flag signal CONWRT, the input data mask signal DM, and the first equalization signal IOPRET.

[0084] The second equalization unit 152d is disposed between the first input / output line IO and the second input / output line IO#, so as to cooperate with the first equalization unit 152a to connect the first input / output line IO and the second input / output line IO# based on the second equalization signal IOPREB.

[0085] Further reading Figure 10 , Figure 10 yes Figure 9 The corresponding signal diagram.

[0086] During continuous write operations, when certain data does not require data masking (e.g.) Figure 10 In the first Write "0" cycle, during the Equalize phase after data writing, the first equalization unit 152a connects the first input / output line IO and the second input / output line IO# based on the first equalization signal IOPRET. The first input / output line IO and the second input / output line IO# are charged and discharged to the same potential Vchs (sharing voltage) through charge sharing. When some data does not need to be written to the memory cell due to data masking operations (such as...), Figure 10 In the second Write "0" cycle, during the Equalize phase after data writing, the precharge unit 152b precharges the first input / output line IO and the second input / output line IO# to the operating voltage Vcc based on the precharge control signal. The second equalization unit 152d connects the first input / output line IO and the second input / output line IO# based on the second equalization signal IOPREB, and charges and discharges them to the same potential (still the operating voltage Vcc) through charge sharing.

[0087] Combination Figure 1 , Figure 9 and Figure 10During continuous write operations, the logic gate control unit 152c generates a corresponding precharge control signal based on the write operation identifier signal CONWRT, the input data masking signal DM, and the first equalization signal IOPRET. Specifically, this includes the following two scenarios:

[0088] Scenario 1: If the next write operation does not involve data input masking (data masking signal DM is in the first state), the precharge control signal generated by the logic gate control unit 152c is in the non-excitation state. During the equalization phase, the precharge unit 152b does not work, and the first equalization unit 152a controls the first input / output line IO and the second input / output line IO# to connect and share charge under the action of the first equalization signal IOPRET so that the voltage on both is the shared voltage.

[0089] In the above scenario, during the Equalize phase of each write operation cycle in the continuous write operation process, the first input / output line IO and the second input / output line IO# are not charged, but only share the charge, so no power consumption is generated.

[0090] The second scenario: If the next write operation involves data input masking (data masking signal DM is in the second state), the precharge control signal generated by the logic gate control unit 152c is in the activated state. During the equalization phase, the precharge control signal activates the precharge unit 152b to precharge the first input / output line IO and the second input / output line IO# to the working voltage (e.g., Vcc). Under the action of the second equalization signal IOPREB, the second equalization unit 152d controls the first input / output line IO and the second input / output line IO# to connect and share the charge so that the voltage on both is maintained at the working voltage Vcc. After the equalization phase, the working voltage Vcc is maintained to mask the data writing to the bit line pair (BL / BL#).

[0091] Combining the two scenarios described above, the input / output circuit in this embodiment, during continuous write operations, does not require charging the input / output lines (IO / IO#) during the Equalize phase after each data write when the written data does not require masking. Compared to... Figure 6 and Figure 8 In this embodiment, the input / output line IO / IO# needs to be charged after each data write during the Equalize phase. If data masking is not performed in this embodiment, no power consumption will be generated during the Equalize phase, thereby reducing the power consumption of the entire random access memory and further improving the performance of the random access memory.

[0092] Combination Figure 9 and Figure 11 , Figure 11 yes Figure 1 A schematic diagram of the third embodiment of the input / output circuit is shown. The input / output circuit 150 includes input / output line pairs (IO / IO#) and a third initialization module 152. The third initialization module 152 includes a first equalization unit 152a, a pre-charge unit 152b, a logic gate control unit 152c, and a second equalization unit 152d.

[0093] The first equalization unit 152a includes: a first switch T13, whose control terminal receives a first equalization signal IOPREET, whose first path terminal is connected to a first input / output line IO, and whose second path terminal is connected to a second input / output line IO#; wherein, during continuous write operation, if the next write operation does not involve data input masking, during the equalization phase, the first equalization signal IOPREET controls the first switch T13 to be turned on, and the first input / output line IO and the second input / output line IO# are connected to share charge.

[0094] The second equalization unit 152d includes a second switch T14, whose control terminal receives a second equalization signal IOPREB, whose first path terminal is connected to the first input / output line IO, and whose second path terminal is connected to the second input / output line IO#. During continuous write operations, if the next write operation involves data input masking, the second equalization signal IOPREB controls the second switch T14 to turn on during the equalization phase, and the first input / output line IO and the second input / output line IO# are connected to share charge.

[0095] The pre-charge unit 152b includes: a third switch T15, whose control terminal receives a pre-charge control signal, whose first path terminal receives the working voltage Vcc, and whose second path terminal is connected to the first input / output line IO; and a fourth switch T16, whose control terminal receives a pre-charge control signal, whose first path terminal receives the working voltage Vcc, and whose second path terminal is connected to the second input / output line IO#. During continuous write operations, if the next write operation involves data input masking, in the equalization phase, the pre-charge control signal controls the third switch T15 and the fourth switch T16 to be turned on, and the voltages on the first input / output line IO and the second input / output line IO# are pre-charged to the working voltage Vcc.

[0096] The logic gate control unit 152c includes: a NOT logic gate, whose input terminal receives an input data shielding signal DM; a first NAND logic gate NAND1, whose first input terminal is connected to the output terminal of the NOT logic gate, and whose second input terminal receives a write operation flag signal CONWR; and a second NAND logic gate NAND2, whose first input terminal receives a first equalization signal IOPRET, whose second input terminal is connected to the output terminal of the first NAND logic gate NAND1, and whose output terminal outputs a precharge control signal, i.e., the control terminal connected to the third switch T15 and the fourth switch T16.

[0097] The following is combined Figure 12 The following table illustrates the above embodiments. Figure 12 yes Figure 11 The corresponding signal diagram is shown in the table below. Figure 11 The corresponding signal logic table shows that the first equalization signal IOPRET and the second equalization signal IOPREB are a pair of logically opposite signals, which are the flag bits of the Equalize stage. When it is necessary to equalize the input / output lines IO / IO#, the first equalization signal IOPRET is pulled high to a logic high potential "1"; when DM is pulled high to a logic high potential "1", it means that the circuit needs to shield the data to be written and not write it to the memory cell.

[0098]

[0099] Combination Figure 11 , Figure 12 Based on the analysis in the table above, it can be seen that in the state of continuous write operation (CONWR is "1") and no data masking is required (DM is "0"), the Equalize phase only performs charge share operation on the input / output line pairs IO / IO#, without consuming power; in the state of continuous write operation (CONWR is "1") and data masking is required (DM is "1"), the Equalize phase charges the input / output line pairs IO / IO# to a logic high potential "1", and data is not written to the memory cell.

[0100] See Figure 13 , Figure 13 This is a schematic diagram of the structure of the random access memory 200 provided in this application. The random access memory 200 includes the storage array 100 as described in the above embodiments.

[0101] Optionally, the random access memory 200 may further include a controller connected to the memory array 100, which generates control signals to control the operation of the memory array 100. These control signals may be signals such as WL, EQ1, EQ3, and YS as described in the above embodiments. It is understood that the column strobe signal generation circuit 142 in the above embodiments may also be integrated into the controller.

[0102] Optionally, the random access memory 200 in this embodiment is DRAM (Dynamic Random Access Memory). DRAM is a semiconductor memory whose main operating principle is to use the amount of charge stored in a capacitor to represent whether a binary bit is "1" or "0". Optionally, the random access memory 200 in this embodiment can also be SRAM (Static Random Access Memory).

[0103] Building upon the beneficial effects of the above embodiments, the random access memory (RAM) in this embodiment, during continuous write operations in the input circuit, if the next write operation does not require data masking, only charge sharing is performed on the input / output line pairs during the equalization phase after the current write operation, without charging. If the next write operation requires data masking, both charging and charge sharing are performed on the input / output line pairs during the equalization phase after the current write operation. By avoiding charging when data masking is not required and only charge sharing is performed, the power consumption of the circuit is reduced, further lowering the overall power consumption of the RAM and improving its performance.

[0104] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A random access memory, characterized in that, include: Storage unit; Word lines; Complementary bit line pairs; The input / output line pair includes a first input / output line and a second input / output line, which are used to connect to the bit line pair. When the column gating module corresponding to the bit line pair is turned on, the bit line pair is connected to the input / output line pair through the turned-on column gating module. An initialization module is connected between the first input / output line and the second input / output line. During a continuous write operation, if the next write operation does not involve data input masking, in the equalization phase, the first input / output line and the second input / output line are connected to share charge so that the voltage on both is a shared voltage. If the next write operation involves data input masking, in the equalization phase, the voltage on the first input / output line and the second input / output line are pre-charged to the operating voltage and connected to share charge. After the equalization phase, the operating voltage is maintained to mask data writing to the bit line pair.

2. The random access memory according to claim 1, characterized in that, The initialization module includes: A first equalization unit is disposed between the first input / output line and the second input / output line to connect the first input / output line and the second input / output line based on a first equalization signal; A pre-charge unit is disposed between the first input / output line and the second input / output line to pre-charge the first input / output line and the second input / output line to the operating voltage based on a pre-charge control signal.

3. The random access memory according to claim 2, characterized in that, The initialization module further includes: A logic gate control unit, connected to the precharge unit, generates and outputs the precharge control signal to the precharge unit based on the write operation identifier signal, the input data masking signal, and the first equalization signal.

4. The random access memory according to claim 3, characterized in that, The initialization module further includes: The second equalization unit is disposed between the first input / output line and the second input / output line, in order to cooperate with the first equalization unit to connect the first input / output line and the second input / output line based on the second equalization signal.

5. The random access memory according to claim 4, characterized in that, The first equalization unit includes: A first switch, whose control terminal receives the first equalization signal, whose first path terminal is connected to the first input / output line, and whose second path terminal is connected to the second input / output line; During continuous write operations, if the next write operation does not involve data input masking, the first equalization signal controls the first switch to turn on during the equalization phase, and the first input / output line and the second input / output line are connected to share charge.

6. The random access memory according to claim 4, characterized in that, The second equalization unit includes: The second switch has a control terminal that receives the second equalization signal, a first path terminal that is connected to the first input / output line, and a second path terminal that is connected to the second input / output line. During continuous write operations, if the next write operation involves data input masking, in the equalization phase, the second equalization signal controls the second switch to turn on, and the first input / output line and the second input / output line are connected to share charge.

7. The random access memory according to claim 4, characterized in that, The pre-charging unit includes: The third switch has a control terminal that receives the pre-charge control signal, a first path terminal that receives the operating voltage, and a second path terminal that is connected to the first input / output line. The fourth switch has a control terminal that receives the pre-charge control signal, a first path terminal that receives the operating voltage, and a second path terminal that is connected to the second input / output line. During continuous write operations, if the next write operation involves data input masking, in the equalization phase, the pre-charge control signal controls the third and fourth switches to turn on, and the voltage on the first and second input / output lines is pre-charged to the operating voltage.

8. The random access memory according to claim 4, characterized in that, The logic gate control unit includes: A NOT logic gate, whose input terminal receives the input data shielding signal; The first NAND gate has its first input connected to the output of the NOT gate, and its second input receiving the write operation flag signal. The second NAND gate has a first input terminal that receives the first equalization signal, a second input terminal that is connected to the output terminal of the first NAND gate, and an output terminal that outputs the precharge control signal.

9. The random access memory according to claim 4, characterized in that, The first equalization signal and the second equalization signal are inverted.

10. The random access memory according to any one of claims 1-9, characterized in that, The random access memory is a dynamic random access memory.

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