Physical unclonable function based on circuits comprising resistive memory elements

Abstract

The present application relates to physically unclonable functions based on circuits comprising resistive memory elements. The present application relates to circuits comprising resistive memory elements and methods of generating physically unclonable functions using these circuits. The circuit comprises a first resistive memory element, a second resistive memory element, a first transistor having a source / drain region connected to the first resistive memory element, and a second transistor having a source / drain region connected to the second resistive memory element. The circuit further comprises a first inverter having an input connected to a first node between the first transistor and the first resistive memory element, and a second inverter having an input connected to a second node between the second transistor and the second resistive memory element.

Description

Technical Field

[0001] This disclosure relates to the manufacture of integrated circuits and semiconductor devices, and more specifically to circuits including resistive memory elements and methods for generating physically unclonable functions using these circuits. Background Technology

[0002] A physically non-cloning function (PUF) is a physical object that, given an input and a set of conditions, generates a physically defined digital fingerprint that can be used as a unique identifier for integrated circuits such as microprocessors. When a physical challenge is applied to this physical object, it reacts in unpredictable ways due to the complex interaction between the stimulus and the object, thus generating an unpredictable response. This response can be used to generate the unique digital fingerprint contained within the physical object.

[0003] Physically unclonable functions can be generated based on physical variations that occur inherently during semiconductor manufacturing and allow for other ways of distinguishing nominally identical semiconductor devices. For example, a physically unclonable function may depend on the uniqueness of the physical microstructure of a particular semiconductor device. Therefore, the random values ​​contained in a physically unclonable function may not be replicable or cloned.

[0004] There is a need for improved circuitry that includes resistive memory elements and methods for generating physically unclonable functions using these circuits. Summary of the Invention

[0005] According to one embodiment of the present invention, a circuit includes: a first resistive memory element; a second resistive memory element; a first transistor having a source / drain region connected to the first resistive memory element; and a second transistor having a source / drain region connected to the second resistive memory element. The circuit further includes: a first inverter having an input connected to a first node between the first transistor and the first resistive memory element; and a second inverter having an input connected to a second node between the second transistor and the second resistive memory element.

[0006] According to another embodiment of the present invention, a method includes: directing current in parallel to a first resistive memory element and a second resistive memory element; detecting a change in the first resistive memory element or the second resistive memory element from a high resistance state to a low resistance state; and interrupting the current in response to detecting the change. Attached Figure Description

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, the same reference numerals denote the same features in various views.

[0008] Figure 1 This is a circuit diagram of primitives configured to generate random values ​​of physically unclonable functions according to an embodiment of the present invention.

[0009] Figure 2 This is a circuit diagram of primitives and control blocks configured to generate multiple random values ​​of a physically unclonable function according to an embodiment of the present invention.

[0010] Figure 3 This is a circuit diagram of primitives configured to generate random values ​​of physically unclonable functions according to an alternative embodiment of the present invention.

[0011] Figure 4 This is a circuit diagram of primitives configured to generate random values ​​of physically unclonable functions according to an alternative embodiment of the present invention.

[0012] Figure 5 This is a circuit diagram of primitives and control blocks configured to generate multiple random values ​​of a physically unclonable function, according to an alternative embodiment of the present invention. Detailed Implementation

[0013] refer to Figure 1 According to an embodiment of the invention, the circuitry for base 10 includes resistive memory element 12, resistive memory element 14, field-effect transistor 16, field-effect transistor 18, field-effect transistor 20, inverter 22, inverter 24, and NAND gate 26. Resistive memory element 12 and field-effect transistor 16 provide 1R-1T bit bases, and resistive memory element 14 and field-effect transistor 18 provide different 1R-1T bit bases. Each of resistive memory elements 12 and 14 includes a bottom electrode, a top electrode, and a switching layer located between the bottom and top electrodes. The top electrode of each of resistive memory elements 12 and 14 is connected to a power supply voltage Vdd. Resistive memory element 12 and field-effect transistor 16 are electrically parallel to resistive memory element 14 and field-effect transistor 18, such that when initially biased during programming, the potential drop across resistive memory element 12 and field-effect transistor 16 is equal to the potential drop across resistive memory element 14 and field-effect transistor 18.

[0014] Each of the resistive memory elements 12 and 14 can be programmed by changing the resistance across the switching layer from a high-resistance state to a low-resistance state. The low-resistance state of resistive memory element 12 can be set by applying a programming voltage from field-effect transistor 16 sufficient to create one or more conductive wires bridging the thickness of the switching layer between the bottom and top electrodes of resistive memory element 12. The low-resistance state of resistive memory element 14 can be set by applying a programming voltage from field-effect transistor 18 sufficient to create one or more conductive wires bridging the thickness of the switching layer between the bottom and top electrodes of resistive memory element 14. During programming, the conductive wires can be formed, for example, by diffusion of a conductive material (e.g., metal ions) from one or both of the bottom and top electrodes into the switching layer.

[0015] Resistive memory elements 12 and 14 can be individually selected by switching field-effect transistors 16 and 18. The gate of field-effect transistor 16 is connected to programming control circuit 28. Figure 2 The programming control circuit 28 is configured to provide a gate control signal G1 to the gate of the field-effect transistor 16. The gate of the field-effect transistor 18 is connected to the programming control circuit 28, which is configured to provide a gate control signal G2 to the gate of the field-effect transistor 18. The field-effect transistor 16 has a source / drain region (e.g., drain) connected to the bottom electrode of the resistive memory element 12, and the field-effect transistor 18 has a source / drain region (e.g., drain) connected in a current path to the bottom electrode of the resistive memory element 14. As used herein, the term "source / drain region" refers to a doped region of semiconductor material that can be used as the source or drain of a field-effect transistor. In one embodiment, field-effect transistors 16 and 18 may be p-channel transistors. In an alternative embodiment, field-effect transistors 16 and 18 may be n-channel transistors.

[0016] The gate of the field-effect transistor 20 and the programming control circuit 28 ( Figure 2 The programming control circuit 28 is configured to provide a gate control signal G3 to the gate of the field-effect transistor 20. One of the source / drain regions of the field-effect transistor 20 is connected to ground via path S1, and the other of the source / drain region of the field-effect transistor 20 is connected in parallel with the source and drain regions of field-effect transistors 16 and 18. In one embodiment, the field-effect transistor 20 may be a p-channel transistor.

[0017] Field-effect transistor 20, inverter 22, inverter 24, and NAND gate 26 are components of the detection circuit, which is connected to the programming control circuit 28. Figure 2Together, they are configured to detect significant changes in the voltage across resistive memory element 12 or resistive memory element 14, and to shut off the voltage stress across resistive memory elements 12 and 14 in response to the detected voltage change. The detection circuit allows the state of resistive memory elements 12 and 14 to be maintained at a certain point during programming.

[0018] Inverter 22 has an input at node 21 in the current path between field-effect transistor 16 and resistive memory element 12, and inverter 24 has an input at node 23 in the current path between field-effect transistor 18 and resistive memory element 14. Inverter 22 is configured to detect a voltage collapse across resistive memory element 12 indicating a change from a high-resistance state to a low-resistance state, and change its state in response to the change in resistance state. Inverter 24 is configured to detect a voltage collapse across resistive memory element 14 indicating a change from a high-resistance state to a low-resistance state, and change its state in response to the change in resistance state.

[0019] Inverters 22 and 24 have outputs coupled to different inputs of NAND gate 26. NAND gate 26 is configured to output a low (logic 0) output only when both inputs from inverters 22 and 24 to NAND gate 26 are high (logic 1). If either input is low, NAND gate 26 is configured to output a high output. The output of NAND gate 26 can be provided to programming control circuitry 28 for generating and providing gate control signals G1, G2, and G3. Figure 2 ).

[0020] In use, the gate control signals G1 and G2 supplied to the gates of field-effect transistors 16 and 18 can be set high to turn on field-effect transistors 18 and 16, and the gate control signal G3 supplied to the gate of field-effect transistor 20 can be set high to turn on field-effect transistor 20. The nodes for resistive memory elements 12 and 14 are pulled down, which directs programming current to flow in parallel through resistive memory elements 12 and 14. The voltage drop across field-effect transistors 16 and 18 can be negligible, or the voltage across field-effect transistors 16 and 18 can be adequately matched so that resistive memory elements 12 and 14 are initially exposed to the same potential across them. Because the voltage across resistive memory elements 12 and 14 occurs simultaneously, each resistive memory element progresses towards a low-resistance state on an independent, separate trajectory or path. The formation or programming process is random, wherein the probability that resistive memory element 12 will be formed or programmed before resistive memory element 14 is limited, and conversely, the probability that resistive memory element 14 will be formed or programmed before resistive memory element 12 is also limited.

[0021] For example, if resistive memory element 12 is programmed first, it will become a low-impedance value that defines a low-resistance path through which relatively high current can flow. This, in turn, means that the voltage across resistive memory element 12 will drop sharply because the voltage drop across field-effect transistors 16 and 18 is negligible. The voltage across resistive memory element 12 will be pulled high, which will pull up the voltage across resistive memory element 14, thereby significantly reducing the probability that resistive memory element 14 will be programmed.

[0022] In response to a voltage drop across resistive memory element 12 preceding a voltage drop across resistive memory element 14, inverter 22 detects the voltage drop reflecting the programming of resistive memory element 12, changes its state, and then triggers output signal O1. Conversely, in response to a voltage drop across resistive memory element 14 preceding a voltage drop across resistive memory element 12, inverter 24 detects the voltage drop reflecting the programming of resistive memory element 14, changes its state, and then triggers output signal O2. Output signal O1 or output signal O2 can be provided to programming control circuit 28 through NAND gate 26. Figure 2 The programming current to resistive memory elements 12 and 14 is interrupted in response to a detected change in resistance from a high-resistance state to a low-resistance state in the first or second resistive memory element. Based on voltage feedback included in output signal O1 or output signal O2, the programming current can be interrupted by modifying the gate control signals G1, G2, and G3 provided to the gates of field-effect transistors 16, 18, and 20. For example, programming control circuit 28 can turn off field-effect transistor 20 by setting gate control signal G3 low, for example, upon receiving output signal O1 or output signal O2. This maintains the difference in resistance states between resistive memory elements 12 and 14.

[0023] The interruption of the programming current based on the reception of output signals O1 and O2 attempts to ensure that only one or the other of the resistive memory elements 12 and 14 is allowed to change to a low-resistance state. In the unlikely case that inverters 22 and 24 change state simultaneously or nearly simultaneously, the indeterminate bit can be discarded. Alternatively, in this case, as described later, a higher-resolution detector can be used to attempt to determine which of the resistive memory elements 12 and 14 has a lower impedance (i.e., lower resistance), and if this higher-resolution determination is successful, the bit is avoided from being discarded.

[0024] One of the resistive memory elements 12 and 14 that is programmed can be controlled by programming control circuit 28. Figure 2The resistive memory elements 12 and 14 can be identified and selected, and additional processing can be performed to ensure that programming is performed robustly. In this regard, different resistance states of the resistive memory elements 12 and 14 can be read or interrogated by using field-effect transistors 16, 18, and 20 to pass a read current through the resistive memory elements 12 and 14 and measuring the voltage difference between them. The read current is limited to avoid changing the corresponding resistance states of the resistive memory elements 12 and 14 during interrogation. In this respect, the read current is significantly smaller than the programming current. One of the resistive memory elements 12 and 14 programmed under voltage stress can be identified based on the measured voltage difference. Specifically, if the resistive memory element 12 is first programmed to a low resistance state that causes a voltage drop, then the resistive memory element 12 will exhibit a lower voltage drop, and if the resistive memory element 14 is first programmed to a low resistance state that causes a voltage drop, then the resistive memory element 14 will exhibit a lower voltage drop.

[0025] In one embodiment, the programming control circuit 28 can be used to identify one of the programmed resistive memory elements 12, 14. Figure 2 The programming control circuit 28 initiates and performs a harden enhancement operation to improve the robustness of the resistive memory element 12, 14 in its low-resistance state. One of the programmed resistive memory elements 12, 14 (e.g., resistive memory element 12) can be harder driven by applying an additional current to ensure the completion of the formation process, while the unprogrammed resistive memory element 12, 14 (e.g., resistive memory element 14) can be isolated from the additional current. For example, the programming control circuit 28 can turn on field-effect transistors 16 and 20 to provide additional current to the resistive memory element 12, while field-effect transistor 18 is turned off to isolate the resistive memory element 14. In one embodiment, the programming control circuit 28 can use field-effect transistors 16, 18, 20 to implement the harden enhancement operation without off-chip data transfer, which improves data security.

[0026] In one embodiment, a pair of resistive memory elements 12, 14 in the primitive contain data that can be considered to constitute a single random bit or value of a physically unclonable function. For example, if resistive memory element 12 is programmed to a low-resistance state through a randomization process, the random value can be considered logic 1, or if resistive memory element 14 is programmed to a low-resistance state through a randomization process, the random value can be considered logic 0. A binary state is created by programming only one of the resistive memory elements 12, 14 to a low-resistance state while restricting the other to a high-resistance state. The random value of the physically unclonable function can be read by using field-effect transistors 16, 18, 20 to pass a read current through the resistive memory elements 12, 14 without modifying the respective resistances and measuring the voltage difference between the resistive memory elements 12 and 14. In this respect, the read current is significantly smaller than the programming current used to generate the random value of the physically unclonable function.

[0027] In an alternative embodiment, after the enhancement operation, the programming control circuit 28 ( Figure 2 The states of the pair of resistive memory elements 12 and 14 can be written into the resistive memory elements of the bit bases in the memory array 30 on the same chip 50 as a single random bit or value of a physically unclonable function. The resistive memory elements of the memory array 30 can be pristine and may not have been subjected to any prior voltage stress. The random value written into the resistive memory elements of the bit bases in the memory array 30 can be, for example, logic 1 when resistive memory element 12 is programmed to a low-resistance state through a randomization process, and logic 0 when resistive memory element 14 is programmed to a low-resistance state through a randomization process. In this way, binary data generated by the controlled programming and enhancement of the pair of resistive memory elements 12 and 14 can be transferred to or written into the resistive memory elements of one of the bit bases in the memory array 30 on the chip and captured as a single random bit or value of a physically unclonable function. After the random value is transferred to the bit bases in the memory array 30, the bases including resistive memory elements 12 and 14 can be ignored in terms of their programmed or unprogrammed state. After the random formation of resistive memory elements 12 and 14 has been completed, memory array 30 operates as a shadow memory, and random values ​​of physically unclonable functions can be read from bit bases in memory array 30 instead of from the pair of resistive memory elements 12 and 14.

[0028] Primitive 10 can be used to generate single random values ​​for physically unclonable functions using a fast, self-restricted, and self-enhancing randomization method. Primitive 10 provides random values ​​for physically unclonable functions based on the inherent randomness of the formation voltage of resistive memory elements, but the derived random values ​​are independent of the logic used for evaluation and reaction. For physically unclonable functions, primitive 10 can facilitate efficient random bit generation with low bit error rates.

[0029] refer to Figure 1 , 2 According to an embodiment of the present invention, multiple instances of primitive 10 can be connected together as primitives 10a, 10b, and 10c to form an array 40. Primitives 10a, 10b, and 10c can be connected to a programming control circuit 28 configured to select and control the function of primitives 10a, 10b, and 10c, thereby generating multiple random bits or values ​​of a physically unclonable function. The number of primitives in the array 40 can be increased to provide a corresponding number of random values ​​that collectively constitute the physically unclonable function.

[0030] The programming control circuit 28 includes control logic for implementing a process control block to generate random values ​​for establishing a physically unclonable function. In this regard, the programming control circuit 28 is configured to select primitives 10a, 10b, and 10c individually, one at a time, and provide gate control signals G1, G2, and G3 via connections to the gates of field-effect transistors 16, 18, and 20 in the selected primitives, thereby causing programming current to flow through only a pair of resistive memory elements 12 and 14 in the selected primitives. In this regard, the programming control circuit 28 can be configured to have independent connections to the gates of field-effect transistors 16, 18, and 20 in the different primitives 10a, 10b, and 10c, allowing independent control of the field-effect transistors 16, 18, and 20. Transistor 32 can be controlled by the control block to connect the source / drain regions of the field-effect transistor 20 in each of the different primitives 10a, 10b, and 10c to ground via a common path S1. Similarly, the top electrodes of the resistive memory elements 12, 14 in each of the different primitives 10a, 10b, 10c can be connected to a bus providing a common power supply voltage Vdd. The programming control circuit 28 can use a constant current source 34 to program the resistive memory elements 12, 14 in each of the different primitives 10a, 10b, 10c. The current supplied from the constant current source 34 is high enough to initiate the formation process, but low enough that when one of the resistive memory elements 12, 14 transitions to a low-resistance state, the voltage across the resistive memory elements 12, 14 drops to a level substantially sufficient to prevent the other of the resistive memory elements 12, 14 from transitioning to a low-resistance state.

[0031] Programming control circuit 28 is configured with connections to different primitives 10a, 10b, 10c to receive output signals O1, O2. Programming control circuit 28 monitors the output signal O1 from a detector defined by inverter 22 in the selected primitive to indicate a significant decrease in the resistance of resistive memory element 12, which indicates that it is being programmed. Simultaneously, programming control circuit 28 monitors the output signal O2 from a detector defined by inverter 24 in the selected primitive to indicate a significant decrease in the resistance of resistive memory element 14, which indicates that it is being programmed. Programming control circuit 28 can identify, based on output signals O1, O2, which of the resistive memory elements 12, 14 has been programmed to its low-resistance state. Programming control circuit 28 can then perform enhancement operations as previously described herein to enhance the low-resistance state of the programmed resistive memory element 12 in the selected primitive, or alternatively, to enhance the low-resistance state of the programmed resistive memory element 14 in the selected primitive.

[0032] After all primitives 10a, 10b, and 10c have been selected and subjected to controlled voltage stress and optional enhancement operations, primitives 10a, 10b, and 10c can subsequently be read to provide random values ​​of physically unclonable functions. Alternatively, programming control circuitry 28 can write the state of a pair of resistive memory elements 12, 14 in each of the primitives 10a, 10b, and 10c to a resistive memory element in one of the bit primitives in the memory array 30 on the same chip 50, and can subsequently read multiple random values ​​of physically unclonable functions from the memory array 30.

[0033] The programming control circuit 28 can individually control the formation or programming of resistive memory elements 12, 14 in each of the primitives 10a, 10b, 10c. The programming control circuit 28 can independently initiate programming for each pair of resistive memory elements 12, 14 and stop programming based on feedback received from each of the primitives 10a, 10b, 10c, so that optimally, only one of the resistive memory elements 12, 14 forms a low-resistance state. The differential resistance state of each pair of differentially programmed resistive memory elements 12, 14 can be converted to one of the random values ​​of a physically non-cloning function.

[0034] refer to Figure 3 According to an alternative embodiment of the invention, base 10 can be modified to directly connect one of the source / drain regions of each of the field-effect transistors 16, 18 to ground, thereby eliminating the field-effect transistor 20 from base 10, and adding a control circuit from the programming control circuit 28. Figure 2The switch 38 is controlled by inputs G4 and G5. State control is achieved through inputs G4 and G5. When switch 38 is in one state, the terminals of resistive memory elements 12 and 14 are shorted together, and when switch 38 is in the other state, the terminals of resistive memory elements 12 and 14 are disconnected. Switch 38 can be, for example, a field-effect transistor. The use of switch 38 allows the gate control signals G1 and G2 to the gates of field-effect transistors 16 and 18 to be independently turned on and off.

[0035] refer to Figure 4 According to an alternative embodiment of the invention, the basic unit 44 can be formed by modifying basic unit 10 to introduce comparator 42. Comparator 42 has an input connected to node 41 in the current path between resistive memory element 12 and inverter 22, and another input connected to node 43 in the current path between resistive memory element 14 and inverter 24. The function of comparator 42 is to monitor nodes 41 and 43 to indicate that one of nodes 41, 43 has a higher voltage than the other, and to output a digital signal indicating which of nodes 41, 43 has a higher voltage. For example, if resistive memory element 12 is formed in a low-resistance state and resistive memory element 14 is not formed, there is a current path through field-effect transistor 20, and node 41 will be higher than node 43. The introduction of comparator 42 provides a higher resolution method for determining the relative resistance values ​​of resistive memory elements 12, 14. For example, if both inverters 22 and 24 indicate a low-resistance state, comparator 42 can distinguish which of the resistive memory elements 12 and 14 has a lower resistance and a higher voltage drop.

[0036] In one embodiment, the programming control circuit 28 ( Figure 5 A check can be performed to ensure that the node voltage difference between resistive memory elements 12 and 14 is significantly higher than the offset of comparator 42. This check can be performed by switching the input of comparator 42. If the output of comparator 42 is logic 0 before the switch and flips to logic 1 after the switch, the offset of comparator 42 is considered negligible compared to the voltage difference between resistive memory elements 12 and 14. Conversely, if the output of comparator 42 does not flip when the input is switched, the voltage difference between resistive memory elements 12 and 14 is insufficient to constitute a robust detection, and programming control circuit 28 can decide whether to abandon the result of primitive programming or continue the formation process.

[0037] refer to Figure 4 , 5According to an embodiment of the present invention, multiple instances of primitive 44 can be connected together as primitives 44a, 44b, 44c to form array 46. Similar to array 40 ( Figure 2 ), primitives 44a, 44b, and 44c are connected to a programming control circuit 28, which is configured to select and control the function of primitives 44a, 44b, and 44c to generate multiple random bits or values ​​of a physically unclonable function. The construction and operation of array 46 are similar to those described for array 40, except for the additional output O3 from comparator 42 received by the programming control circuit 28 from each of the primitives 44a, 44b, and 44c and used as previously described.

[0038] The methods described above are used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. The chips can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of intermediate or final products. The final product can be any product that includes integrated circuit chips, such as a computer product with a central processing unit or a smartphone.

[0039] References to terms modified by approximate language such as “approximately,” “about,” or “basically” in this document are not limited to the specified precise values. Approximate language may correspond to the precision of the instrument used to measure the value, and, unless dependent on the precision of the instrument, may indicate a range of + / -10% of the value.

[0040] The use of terms such as “vertical” and “horizontal” in this document establishes a frame of reference by way of example rather than limitation. As used herein, the term “horizontal” is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to directions perpendicular to the horizontal direction just defined. The term “lateral” refers to a direction within the horizontal plane.

[0041] A feature that is “connected” or “coupled” to or with another feature can be directly connected or coupled to or with other features, or one or more intermediate features may exist. If no intermediate features exist, a feature can be “directly connected” or “directly coupled” to or with another feature. If at least one intermediate feature exists, a feature can be “indirectly connected” or “indirectly coupled” to or with another feature. A feature that is “on” or “in contact” with another feature can be directly on or in contact with other features, or one or more intermediate features may exist. If no intermediate features exist, a feature can be “directly” on or in contact with another feature. If at least one intermediate feature exists, a feature can be “indirectly” on or in contact with another feature. If a feature extends above and covers a portion of another feature, the different features can “overlap.”

[0042] The description of various embodiments of the present invention is given for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is for the purpose of best explaining the principles of the embodiments, their practical application, or technical improvements relative to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A circuit for generating physically unclonable functions, comprising: First resistive memory element; Second resistive memory element; A first transistor having a first source / drain region connected to the first resistive memory element; The second transistor has a first source / drain region connected to the second resistive memory element; A first inverter has an input connected to a first node between the first transistor and the first resistive memory element; The second inverter has an input connected to a second node between the second transistor and the second resistive memory element; as well as A comparator having a first input and a second input, the first input being connected to a third node between the first resistive memory element and the first inverter, and the second input being connected to a fourth node between the second resistive memory element and the second inverter.

2. The circuit of claim 1, wherein, The first transistor has a second source / drain region, the second transistor has a second source / drain region, and the circuit further includes: The third transistor has a second source / drain region connected to the second source / drain region of the first transistor and a source / drain region connected to the second source / drain region of the second transistor.

3. A circuit for generating physically unclonable functions, comprising: First resistive memory element; Second resistive memory element; A first transistor includes a first source / drain region and a first gate, wherein the first source / drain region of the first transistor is connected to the first resistive memory element. The second transistor includes a first source / drain region and a second gate, wherein the first source / drain region of the second transistor is connected to the second resistive memory element; A first inverter has an input connected to a first node between the first transistor and the first resistive memory element; The second inverter has an input connected to a second node between the second transistor and the second resistive memory element; as well as A programming control circuit is connected to the first gate of the first transistor and the second gate of the second transistor.

4. The circuit according to claim 3, wherein, The programming control circuit is configured to turn on the first transistor and the second transistor.

5. The circuit according to claim 4, wherein, The first transistor has a second source / drain region, the second transistor has a second source / drain region, and the circuit further includes: The third transistor has a gate connected to the programming control circuit, and a source / drain region connected to the second source / drain region of the first transistor and the second source / drain region of the second transistor. The programming control circuit is configured to turn on the third transistor.

6. The circuit according to claim 5, wherein, The programming control circuit is configured to receive a first output signal from the first inverter, the programming control circuit is configured to receive a second output signal from the second inverter, and the programming control circuit is configured to turn off the third transistor in response to the first output signal or the second output signal.

7. The circuit according to claim 3, wherein, The programming control circuit is configured to receive a first output signal from the first inverter, and the programming control circuit is configured to receive a second output signal from the second inverter.

8. The circuit according to claim 3, further comprising: A comparator having a first input and a second input, the first input being connected to a third node between the first resistive memory element and the first inverter, the second input being connected to a fourth node between the second resistive memory element and the second inverter, and the programming control circuit being configured to receive an output signal from the comparator.

9. The circuit according to claim 1, further comprising: A switch having a first position in which the first resistive memory element is shorted to the second resistive memory element and a second position in which the first resistive memory element is disconnected from the second resistive memory element.

10. A method for generating physically unclonable functions, comprising: The first current is directed in parallel to the first resistive memory element and the second resistive memory element; Detect the change in resistance of the first resistive memory element or the second resistive memory element from a high resistance state to a low resistance state; The first current is interrupted in response to detecting a change in the resistance of the first resistive memory element or the second resistive memory element from the high resistance state to the low resistance state; The second current is guided through the first resistive memory element and the second resistive memory element; as well as While guiding the second current through the first resistive memory element and the second resistive memory element, the voltage difference between the first resistive memory element and the second resistive memory element is measured. Wherein, the second current is less than the first current.

11. The method according to claim 10, wherein, The first resistive memory element has the low resistance state based on the measured voltage difference, and the low resistance state of the first resistive memory element specifies a random value of a physically unclonable function.

12. The method of claim 11, further comprising: The random value of the physically unclonable function is transferred to a third resistive memory element in the bit base of the memory array.

13. The method of claim 12, further comprising: The random value of the physically unclonable function is read from the bit primitive in the memory array.

14. The method of claim 11, further comprising: The random value of the physically unclonable function is read based on the voltage difference between the first resistive memory element and the second resistive memory element.

15. The method of claim 11, further comprising: A third current is applied to the first resistive memory element in response to interruption of the first current; as well as The second resistive memory element is isolated from the third current.

16. The method of claim 10, wherein, Detecting the change from the high resistance state to the low resistance state of the first resistive memory element or the second resistive memory element includes: The inverter outputs an output signal from the node connected between the first resistive memory element and the first transistor. The output signal indicates that the first resistive memory element changes from the high resistance state to the low resistance state.

17. The method according to claim 10, wherein, The first current is directed in parallel to the first resistive memory element and the second resistive memory element, wherein there is an equal voltage across the first resistive memory element and the second resistive memory element.

18. The method according to claim 10, wherein, Detecting the change from the high resistance state to the low resistance state of the first resistive memory element or the second resistive memory element includes: A comparator compares a first voltage drop across the first resistive memory element with a second voltage drop across the second resistive memory element; and The low-resistance state of the first resistive memory element is determined based on the output from the comparator. The low-resistance state of the first resistive memory element determines a random value of the physical unclonable function.

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