Three-dimensional phase change memory sub-threshold data readout circuit and readout method

Abstract

The application relates to a three-dimensional phase change memory sub-threshold data readout circuit and method, wherein the readout circuit comprises: a sensitive amplifier circuit for comparing a bit line current and a reference bit line current and outputting a data readout voltage signal; a clamping voltage generation circuit for providing a clamping voltage to the sensitive amplifier circuit, and clamping the voltage of a bit line of the phase change memory array through the clamping voltage; a word line half-bias voltage generation circuit for providing a word line half-bias voltage to the phase change memory array; a current replication circuit for offsetting a leakage current generated by the phase change memory array; and a cell reference current generation circuit for generating a single cell reference current. The application solves the problem that the size of a storage array is limited due to a small read window margin during a three-dimensional phase change memory sub-threshold read operation.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to a subthreshold data readout circuit and readout method for a three-dimensional phase-change memory. Background Technology

[0002] The storage cells of a three-dimensional phase-change memory (3D phase-change memory) consist of bidirectional threshold selectors (OTS) and phase-change modules (PCMs) connected in series. By stacking memory cells vertically, a larger storage capacity is achieved, making it one of the best choices for storage-class memory. In traditional read operations, if the selected 1S1R storage cell is in a low-impedance state, the OTS is activated, and data is read using a very high current switching ratio. However, traditional read operations consume the number of cycles of the selector, shortening the lifespan of the 3D phase-change memory. Therefore, the industry has proposed a subthreshold region reading method to compensate for the shortcomings of traditional read operations.

[0003] Subthreshold read operations can be performed without turning on the selector transistor, greatly increasing the number of operation cycles in a 3D phase-change memory (PCM). However, during subthreshold read operations, the subthreshold current of the memory cells in the low-resistance state is small, resulting in a relatively small current ratio between low and high resistance. Furthermore, due to the small cell current, the leakage current caused by the V / 2 bias of the 3D PCM cannot be ignored, and the extremely small read window margin limits the capacity of the memory array. Currently, there is limited research on specific circuits for subthreshold read operations in 3D PCMs; therefore, there is an urgent need to propose a readout circuit and method suitable for subthreshold reads in 3D PCMs. Summary of the Invention

[0004] This invention provides a subthreshold data readout circuit and method for a three-dimensional phase-change memory, which solves the problem that the small read window margin limits the size of the storage array during subthreshold read operations of a three-dimensional phase-change memory.

[0005] The technical solution adopted by this invention to solve its technical problem is: providing a subthreshold data readout circuit for a three-dimensional phase-change memory, comprising:

[0006] A sensitive amplifier circuit, connected to the phase-change memory array via a bit line, is used to compare the bit line current and the reference bit line current, and output a data readout voltage signal.

[0007] A clamping voltage generation circuit, connected to the sensitive amplifier circuit, is used to provide a clamping voltage to the sensitive amplifier circuit, thereby clamping the voltage of the bit lines of the phase-change memory array.

[0008] A word line half-bias voltage generation circuit, connected to the phase-change memory array, is used to provide word line half-bias voltage to the phase-change memory array;

[0009] A current replication circuit, connected to the word line half-bias voltage generation circuit and the sensitive amplifier circuit, is used to counteract the leakage current generated by the phase change memory array.

[0010] A unit reference current generation circuit, connected to the current replication circuit and the sensitive amplifier circuit, is used to generate a single unit reference current.

[0011] The sensitive amplifier circuit includes a current sensing circuit and a comparator circuit;

[0012] The current sensing circuit is connected to the bit line and the reference bit line, and is used to collect the bit line current and the reference bit line current, and convert the bit line current and the reference bit line current into differential voltage signals;

[0013] The comparison circuit includes a level shifting circuit, a self-biased voltage comparator, and an output inverter. The level shifting circuit is connected to the read current sensing circuit and is used to convert the differential voltage signal into a value that the self-biased voltage comparator can process. The self-biased voltage comparator is connected to the level shifting circuit and is used to compare the processed differential voltage signal. The output inverter is connected to the self-biased voltage comparator and is used to convert the comparison result of the self-biased voltage comparator into a read voltage signal.

[0014] The current sensing circuit includes:

[0015] The first PMOS transistor has its source connected to the power supply voltage input terminal.

[0016] The source of the second PMOS transistor is connected to the power supply voltage input terminal;

[0017] The first NMOS transistor has its drain connected to the drain of the first PMOS transistor, and its gate connected to the clamping voltage generation circuit.

[0018] The second NMOS transistor has its drain connected to the drain of the second PMOS transistor and its gate connected to the gate of the first NMOS transistor.

[0019] The third NMOS transistor has its source connected to the drain of the first PMOS transistor, its drain connected to the gate of the first PMOS transistor, and its gate connected to the external first read enable signal RE1.

[0020] The fourth NMOS transistor has its source connected to the drain of the second PMOS transistor, its drain connected to the gate of the second PMOS transistor, and its gate connected to the external first read enable signal RE1.

[0021] A first capacitor, wherein a first port of the first capacitor is connected to the gate of the second PMOS transistor, and a second port is connected to the drain of the first PMOS transistor;

[0022] The second capacitor C2 has its first port connected to the gate of the first PMOS transistor and its second port connected to the drain of the second PMOS transistor.

[0023] The level shifting circuit includes:

[0024] The fifteenth NMOS transistor has its source grounded and its gate connected to the external bias VB5 output terminal.

[0025] The seventeenth NMOS transistor has its source connected to the drain of the fifteenth NMOS transistor and its gate connected to the drain of the first PMOS transistor. The drain serves as the second output terminal of the level shifting circuit.

[0026] The thirteenth PMOS transistor has its source connected to the power supply voltage input terminal, its drain connected to the drain of the seventeenth NMOS transistor, and its gate connected to the inverted signal RE2N of the external second read enable signal RE2.

[0027] The sixteenth NMOS transistor has its source grounded and its gate connected to the external bias VB5 output terminal.

[0028] The eighteenth NMOS transistor has its source connected to the drain of the sixteenth NMOS transistor and its gate connected to the drain of the second PMOS transistor. The drain serves as the first output terminal of the level shifting circuit.

[0029] The fourteenth PMOS transistor has its source connected to the power supply voltage input terminal, its drain connected to the drain of the eighteenth NMOS transistor, and its gate connected to the inverted signal RE2N of the external second read enable signal RE2.

[0030] The self-biased voltage comparator includes:

[0031] The nineteenth NMOS transistor, the source of which is grounded;

[0032] The twentieth NMOS transistor has its source connected to the drain of the nineteenth NMOS transistor and its gate connected to the external second read enable signal RE2.

[0033] The source of the 21st NMOS transistor is connected to the drain of the 20th NMOS transistor, and its gate is connected to the first output terminal of the level shifting circuit.

[0034] The source of the 22nd NMOS transistor is connected to the drain of the 20th NMOS transistor, and the gate is connected to the second output terminal of the level shifting circuit.

[0035] The fifteenth PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the gate of the nineteenth NMOS transistor and the drain of the twenty-first NMOS transistor.

[0036] The sixteenth PMOS transistor, the source of which is connected to the drain of the fifteenth PMOS transistor, and the gate of which is connected to the inverted signal RE2N of the external second read enable signal RE2;

[0037] The seventeenth PMOS transistor has its source connected to the drain of the sixteenth PMOS transistor, its gate connected to the gate of the twenty-first NMOS transistor, and its drain connected to the drain of the twenty-first NMOS transistor.

[0038] The eighteenth PMOS transistor has its source connected to the drain of the sixteenth PMOS transistor, its gate connected to the gate of the twenty-second NMOS transistor, and its drain connected to the drain of the twenty-second NMOS transistor. It also serves as the output terminal of the self-biased voltage comparator.

[0039] The output inverter includes:

[0040] The 23rd NMOS transistor has its source grounded and its gate connected to the external second read enable signal RE2.

[0041] The source of the 24th NMOS transistor is connected to the drain of the 23rd NMOS transistor, and its gate is connected to the output of the self-biased voltage comparator.

[0042] The nineteenth PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the inverted signal RE2N of the external second read enable signal RE2.

[0043] The twentieth PMOS transistor has its source connected to the drain of the nineteenth PMOS transistor, its gate connected to the gate of the twenty-fourth NMOS transistor, and its drain connected to the drain of the twenty-fourth NMOS transistor.

[0044] The phase-change memory array includes 1S1R phase-change memory cells, bit line transmission gates, and word line transmission gates;

[0045] The 1S1R phase change memory unit is composed of a phase change resistor PCM and a bidirectional threshold selector OTS connected in series.

[0046] The bit line transmission gate includes a bit line gating transmission gate and a bit line half-bias transmission gate; the first transmission terminal of the bit line gating transmission gate is connected to the sensitive amplifier circuit, and the second transmission terminal of the bit line gating transmission gate is connected to one end of the 1S1R phase-change memory cell; the first transmission terminal of the bit line half-bias transmission gate is connected to an external bias voltage V / 2, and the second transmission terminal of the bit line half-bias transmission gate is connected to one end of the 1S1R phase-change memory cell.

[0047] The word line transmission gate includes a word line gating transmission gate and a word line half-bias transmission gate. The first transmission terminal of the word line gating transmission gate is grounded, and the second transmission terminal of the word line gating transmission gate is connected to the other end of the 1S1R phase-change memory cell. The first transmission terminal of the word line half-bias transmission gate is connected to the word line half-bias voltage generation circuit, and the second transmission terminal of the word line half-bias transmission gate is connected to one end of the 1S1R phase-change memory cell.

[0048] The clamping voltage generation circuit includes:

[0049] The first inverter has its input terminal connected to an external first read enable signal RE1;

[0050] The second inverter has its input terminal connected to an external second read enable signal RE2.

[0051] The third PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the external bias VB4 output terminal.

[0052] The fourth PMOS transistor has its source connected to the drain of the third PMOS transistor, and its gate connected to the external bias VRC output terminal.

[0053] The fifth PMOS transistor has its source connected to the drain of the third PMOS transistor, its gate connected to the gate of the first NMOS transistor, and its drain connected to the source of the first NMOS transistor.

[0054] The fifth NMOS transistor has its drain and gate connected to the drain of the fourth PMOS transistor, and its source grounded.

[0055] The sixth NMOS transistor has its drain connected to the drain of the fifth PMOS transistor, its gate connected to the gate of the fifth NMOS transistor, and its source grounded.

[0056] The seventh NMOS transistor has its drain connected to the gate of the fifth PMOS transistor, its source grounded, and its gate connected to the output of the first inverter.

[0057] The word line half-bias voltage generation circuit includes:

[0058] The sixth PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the external bias VB4 output terminal.

[0059] The seventh PMOS transistor has its source connected to the drain of the sixth PMOS transistor and its gate connected to the output terminal of the external bias voltage V / 2.

[0060] The eighth PMOS transistor, the source of which is connected to the drain of the sixth PMOS transistor;

[0061] The eighth NMOS transistor has its drain and gate connected to the drain of the seventh PMOS transistor, and its source grounded.

[0062] The ninth NMOS transistor has its drain connected to the drain of the eighth PMOS transistor, its gate connected to the gate of the eighth NMOS transistor, and its source grounded.

[0063] The ninth PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the external bias VB2 output terminal.

[0064] The tenth PMOS transistor has its source connected to the drain of the ninth PMOS transistor and its gate connected to the external bias VB3 output terminal.

[0065] A first resistor, the first port of which is connected to the drain of the tenth PMOS transistor, and the second port of which is connected to the gate of the eighth PMOS transistor;

[0066] The tenth NMOS transistor has its source grounded and its gate connected to the drain of the eighth PMOS transistor.

[0067] The fourteenth NMOS transistor has its source connected to the drain of the tenth NMOS transistor, its drain connected to the gate of the eighth PMOS transistor and the phase-change memory array, and its gate connected to the external bias VB1 output terminal.

[0068] The second resistor Rm, the first port of the second resistor Rm is connected to the drain of the eighth PMOS transistor;

[0069] The third capacitor Cc has its first port connected to the second port of the second resistor Rm, and its second port connected to the drain of the fourteenth NMOS transistor.

[0070] The current replication circuit includes V HALF Current replication module and branch current replication module;

[0071] The VHALF The current replication module includes:

[0072] The eleventh NMOS transistor has its source grounded and its gate connected to the gate of the tenth NMOS transistor.

[0073] The twelfth NMOS transistor has its source connected to the drain of the eleventh NMOS transistor, its gate connected to the external bias VB1 output terminal, and its drain connected to the sensitive amplifier circuit.

[0074] The branch current replication module includes:

[0075] The eleventh PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the external bias VB2 output terminal.

[0076] The twelfth PMOS transistor has its source connected to the drain of the eleventh PMOS transistor, its gate connected to the external bias VB3 output terminal, and its drain connected to the sensitive amplifier circuit.

[0077] The V HALF The current replication module generates a first replication current based on the current flowing through the tenth NMOS transistor; the branch current replication module generates a second replication current based on the current flowing through the ninth PMOS transistor.

[0078] The unit reference current generation circuit includes a thirteenth NMOS transistor, the source of which is grounded and the gate is connected to an external bias V. REF At the output terminal, the drain is connected to the sensitive amplifier circuit.

[0079] The technical solution adopted by this invention to solve its technical problem is: to provide a subthreshold data readout method for a three-dimensional phase-change memory, applied to the aforementioned subthreshold data readout circuit of the three-dimensional phase-change memory, comprising the following steps:

[0080] (1) After the first read enable signal RE1 is valid, the phase change memory array selects the 1S1R phase change unit; the sensitive amplifier circuit and the clamping voltage generation circuit charge the phase change memory array.

[0081] (2) The word line half-bias voltage generation circuit stabilizes the half-biased word line of the phase-change memory array at V. HALF Voltage; the sensitive amplifier circuit and the clamping voltage generation circuit clamp the bit line voltage V of the phase-change memory array. BL The current replication circuit replicates the V respectively. HALF Current and branch current;

[0082] (3) When the VHALF Voltage and the bit line voltage V BL After stabilization, read the bit line current I. BL and reference bit line current I BLB ;

[0083] (4) After the first read enable signal RE1 is invalid and the second read enable signal RE2 is valid, the sensitive amplifier circuit disconnects the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor, and amplifies the voltage SA1 and the voltage SA2 based on the charge stored on the first capacitor C1 and the second capacitor C2.

[0084] (5) The comparison circuit performs voltage shift on the differential signals of voltage SA1 and voltage SA2, compares them, and outputs the read voltage.

[0085] The reading step (1) begins when the first read enable signal RE1 rises to the power supply voltage, and the reading step (4) begins when the first read enable signal RE1 drops to ground from the power supply voltage and the second read enable signal RE2 rises to the power supply voltage.

[0086] The unit reference current generation circuit is based on voltage V. REF Generate reference current I REF The reference current is between the low-resistivity subthreshold current and the high-resistivity subthreshold current of a single 1S1R phase-change memory cell; the bit line current I BL Unit current I CELL and leakage current I LEAK The sum of; the reference bit line current I BLB First replication current + reference current I REF - Second replication current; the bit line voltage V BL The low resistance threshold voltage is less than that of the 1S1R phase change memory cell.

[0087] Beneficial effects

[0088] By adopting the above-mentioned technical solution, this invention has the following advantages and positive effects compared with the prior art: Through the coordinated operation of a sensitive amplifier, a word line half-bias voltage generation circuit, a clamping voltage generation circuit, and a current replication circuit, this invention solves the problem of the small read margin window limiting the size of the storage array in subthreshold read operations of three-dimensional phase-change memory. The introduction of the word line half-bias voltage generation circuit and the clamping voltage generation circuit accelerates voltage stabilization, enabling precise replication of leakage current and shortening the subthreshold data reading speed of the phase-change memory. It also simplifies the read operation steps and control signals, making operation convenient. Attached Figure Description

[0089] Figure 1This is a schematic diagram of the subthreshold data readout circuit of a three-dimensional phase-change memory in an embodiment of the present invention;

[0090] Figure 2 This is a schematic diagram of the comparison circuit in an embodiment of the present invention;

[0091] Figure 3 This is a schematic diagram of the phase-change memory array structure in an embodiment of the present invention;

[0092] Figure 4 A schematic diagram illustrating the steps of the subthreshold data readout method for a three-dimensional phase-change memory in an embodiment of the present invention;

[0093] Figure 5 This is a simulation diagram of reading the low-resistivity phase-change memory cell in the subthreshold region in an embodiment of the present invention;

[0094] Figure 6 This is a simulation diagram of reading a high-resistivity phase-change memory cell in the subthreshold region according to an embodiment of the present invention;

[0095] Among them, 10-sensitive amplifier circuit, 101-read current sensing circuit, 102-comparison circuit, 1021-level shifting circuit, 1022-self-biased voltage comparator, 1023-output inverter, 20-phase-change memory array, 30-clamping voltage generation circuit, 40-word line half-biased voltage generation circuit, 50-current replication circuit, 501-V HALF Current replication module, 502-branch current replication module, 60-unit reference current generation circuit. Detailed Implementation

[0096] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0097] Embodiments of the present invention relate to a subthreshold data readout circuit for a three-dimensional phase-change memory, such as... Figure 1 As shown, it includes:

[0098] The sensitive amplifier circuit 10 is used to compare the bit line current and the reference bit line current, and output the data readout voltage signal.

[0099] The phase-change memory array 20 is connected to the sensitive amplifier circuit 10 via bit lines and is used to store data.

[0100] The clamping voltage generation circuit 30 is connected to the sensitive amplifier circuit 10 and is used to provide the required clamping voltage to the sensitive amplifier circuit 10 to clamp the bit line voltage of the phase change memory array 20 and make the bit line voltage quickly stabilized.

[0101] The word line half-bias voltage generation circuit 40 is connected to the phase change memory array 20 and is used to provide the required word line half-bias voltage to the phase change memory array 20 and to quickly stabilize the word line half-bias voltage.

[0102] The current replication circuit 50 is connected to the word line half-bias voltage generation circuit 40 and the sensitive amplifier circuit 10, and is used to counteract the leakage current generated by the phase change memory array 20.

[0103] The unit reference current generation circuit 60 is connected to the current replication circuit 50 and the sensitive amplifier circuit 10, and is used to generate a single unit reference current.

[0104] The sensitive amplifier circuit 10 in this embodiment includes a read current sensing circuit 101 and a comparator circuit 102; wherein,

[0105] The current sensing circuit 101 is connected to the bit line and the reference bit line, and is used to collect the bit line current and the reference bit line current and convert them into a differential voltage signal.

[0106] like Figure 2 As shown, the comparison circuit 102 in this embodiment includes: a level shifting circuit 1021, a self-biased voltage comparator 1022, and an output inverter 1023; wherein,

[0107] The level shifting circuit 1021 is connected to the current reading sensing circuit 101 and is used to convert the differential voltage to a suitable value so that the self-biased voltage comparator can process it.

[0108] The self-biased voltage comparator 1022 is connected to the level shifting circuit 1021 and is used to compare the processed differential voltage signal.

[0109] The output inverter 1023 is connected to the self-biased voltage comparator 1022 and is used to convert the comparison result of the self-biased voltage comparator 1022 into a readout voltage signal.

[0110] In this embodiment, the current sensing circuit 101 includes:

[0111] The first PMOS transistor has its source connected to the power supply voltage input terminal.

[0112] The source of the second PMOS transistor is connected to the power supply voltage input terminal.

[0113] The first NMOS transistor has its drain connected to the drain of the first PMOS transistor.

[0114] The second NMOS transistor has its drain connected to the drain of the second PMOS transistor, and its gate connected to the gate of the first NMOS transistor.

[0115] The third NMOS transistor has its source connected to the drain of the first PMOS transistor, its drain connected to the gate of the first PMOS transistor, and its gate connected to an external first read enable signal RE1.

[0116] The fourth NMOS transistor has its source connected to the drain of the second PMOS transistor, its drain connected to the gate of the second PMOS transistor, and its gate connected to the external first read enable signal RE1.

[0117] Capacitor C1, the first port of capacitor C1 is connected to the gate of the second PMOS transistor, and the second port of capacitor C1 is connected to the drain of the first PMOS transistor.

[0118] Capacitor C2, the first port of capacitor C2 is connected to the gate of the first PMOS transistor, and the second port of capacitor C2 is connected to the drain of the second PMOS transistor.

[0119] The level shifting circuit 1021 includes:

[0120] The fifteenth NMOS transistor has its source grounded and its gate connected to the external bias VB5 output terminal.

[0121] The seventeenth NMOS transistor has its source connected to the drain of the fifteenth NMOS transistor, and its gate connected to the drain of the first PMOS transistor.

[0122] The thirteenth PMOS transistor has its source connected to the power supply voltage input terminal, its drain connected to the drain of the seventeenth NMOS transistor, and its gate connected to the inverted signal RE2N of the external second read enable signal RE2.

[0123] The sixteenth NMOS transistor has its source grounded and its gate connected to the external bias VB5 output terminal.

[0124] The eighteenth NMOS transistor has its source connected to the drain of the sixteenth NMOS transistor, and its gate connected to the drain of the second PMOS transistor.

[0125] The fourteenth PMOS transistor has its source connected to the power supply voltage input terminal, its drain connected to the drain of the eighteenth NMOS transistor, and its gate connected to the inverted signal RE2N of the external second read enable signal RE2.

[0126] In this embodiment, the self-biased voltage comparator 1022 includes:

[0127] The nineteenth NMOS transistor, the source of which is grounded.

[0128] The twentieth NMOS transistor has its source connected to the drain of the nineteenth NMOS transistor, and its gate connected to an external second read enable signal RE2.

[0129] The source of the 21st NMOS transistor is connected to the drain of the 20th NMOS transistor, and the gate of the 21st NMOS transistor is connected to the source of the 18th NMOS transistor.

[0130] The source of the 22nd NMOS transistor is connected to the drain of the 10th NMOS transistor, and the gate of the 22nd NMOS transistor is connected to the source of the 17th NMOS transistor.

[0131] The fifteenth PMOS transistor has its source connected to the power supply voltage input terminal, and its gate connected to the gate of the nineteenth NMOS transistor and the drain of the twenty-first NMOS transistor.

[0132] The sixteenth PMOS transistor has its source connected to the drain of the fifteenth PMOS transistor, and its gate connected to the inverted signal RE2N of the external second read enable signal RE2.

[0133] The seventeenth PMOS transistor has its source connected to the drain of the sixteenth PMOS transistor, its gate connected to the gate of the twenty-first NMOS transistor, and its drain connected to the drain of the twenty-first NMOS transistor.

[0134] The eighteenth PMOS transistor has its source connected to the drain of the sixteenth PMOS transistor, its gate connected to the gate of the twenty-second NMOS transistor, and its drain connected to the drain of the twenty-second NMOS transistor.

[0135] In this embodiment, the output inverter 1023 includes:

[0136] The 23rd NMOS transistor has its source grounded and its gate connected to the external second read enable signal RE2.

[0137] The source of the 24th NMOS transistor is connected to the drain of the 23rd NMOS transistor, and the gate of the 24th NMOS transistor is connected to the drain of the 22nd NMOS transistor.

[0138] The nineteenth PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the inverted signal RE2N of the external second read enable signal RE2.

[0139] The twentieth PMOS transistor has its source connected to the drain of the nineteenth PMOS transistor, its gate connected to the gate of the twenty-fourth NMOS transistor, and its drain connected to the drain of the twenty-fourth NMOS transistor.

[0140] like Figure 3 As shown, the phase-change memory array 20 in this embodiment includes: 1S1R phase-change memory cells and bit-line transmission gates (RTGs). BL And word line transmission gate RTG WL .

[0141] The 1S1R phase change memory unit is composed of a phase change resistor PCM and a bidirectional threshold selector OTS connected in series.

[0142] The bit line transmission gate RTG BL It includes: a bit-line selected transmission gate and a bit-line half-biased transmission gate; the first transmission terminal of the bit-line selected transmission gate is connected to the source of the first NMOS transistor, and the second transmission terminal of the bit-line selected transmission gate is connected to one end of the phase-change memory cell 1S1R; the first transmission terminal of the bit-line half-biased transmission gate is connected to an external bias voltage V / 2, and the second transmission terminal of the bit-line half-biased transmission gate is connected to one end of the phase-change memory cell 1S1R.

[0143] The word line transmission gate RTG WLIt includes: a word line gating transmission gate and a word line half-bias transmission gate, wherein the first transmission terminal of the word line gating transmission gate is grounded, and the second transmission terminal of the word line gating transmission gate is connected to the other end of the phase change memory unit 1S1R; the first transmission terminal of the word line half-bias transmission gate is connected to the word line half-bias voltage generation circuit, and the second transmission terminal of the word line half-bias transmission gate is connected to one end of the phase change memory unit 1S1R.

[0144] Specifically, the size of the phase change memory array 20 can be 512×512. The size of the phase change memory array can be set according to actual needs and is not limited to this embodiment.

[0145] In this embodiment, the clamping voltage generation circuit 30 includes:

[0146] The first inverter has its input terminal connected to the external first read enable signal RE1.

[0147] The second inverter is connected to the external second read enable signal RE2 at the input of the first inverter.

[0148] The third PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the external bias VB4 output terminal.

[0149] The fourth PMOS transistor has its source connected to the drain of the third PMOS transistor, and its gate connected to the external bias VRC output terminal.

[0150] The fifth PMOS transistor has its source connected to the drain of the third PMOS transistor, its gate connected to the gate of the first NMOS transistor, and its drain connected to the source of the first NMOS transistor.

[0151] The fifth NMOS transistor has its drain and gate connected to the drain of the fourth PMOS transistor, and its source is grounded.

[0152] The sixth NMOS transistor has its drain connected to the drain of the fifth PMOS transistor, its gate connected to the gate of the fifth NMOS transistor, and its source grounded.

[0153] The seventh NMOS transistor has its drain connected to the gate of the fifth PMOS transistor, its source grounded, and the gate of the tenth NMOS transistor connected to the output of the first inverter.

[0154] In this embodiment, the word line half-bias voltage generation circuit 40 includes:

[0155] The sixth PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the external bias VB4 output terminal.

[0156] The seventh PMOS transistor has its source connected to the drain of the sixth PMOS transistor, and its gate connected to the output terminal of the external bias voltage V / 2.

[0157] The eighth PMOS transistor has its source connected to the drain of the sixth PMOS transistor.

[0158] The eighth NMOS transistor has its drain and gate connected to the drain of the seventh PMOS transistor, and its source is grounded.

[0159] The ninth NMOS transistor has its drain connected to the drain of the eighth PMOS transistor, its gate connected to the gate of the eighth NMOS transistor, and its source grounded.

[0160] The ninth PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the external bias VB2 output terminal.

[0161] The tenth PMOS transistor has its source connected to the drain of the ninth PMOS transistor, and its gate connected to the external bias VB3 output terminal.

[0162] Resistor R1, the first port of resistor R1 is connected to the drain of the tenth PMOS transistor, and the second port of resistor R1 is connected to the gate of the eighth PMOS transistor.

[0163] The tenth NMOS transistor has its source grounded and its gate connected to the drain of the eighth PMOS transistor.

[0164] The fourteenth NMOS transistor has its source connected to the drain of the tenth NMOS transistor, its drain connected to the gate of the eighth PMOS transistor and the first transmission terminal of the word line half-biased transmission gate of the phase-change memory array 20, and its gate connected to the external bias VB1 output terminal.

[0165] resistor R m The resistor R m The first port is connected to the drain of the eighth PMOS transistor.

[0166] Capacitor C c The capacitor C c The first port is connected to the resistor R m The second port, the capacitor C c The second port is connected to the drain of the fourteenth NMOS transistor.

[0167] In this embodiment, the current replication circuit 50 includes V HALF Current replication module 501 and branch current replication module 502;

[0168] The V HALF The current replication module 501 includes:

[0169] The eleventh NMOS transistor has its source grounded and its gate connected to the gate of the tenth NMOS transistor.

[0170] The twelfth NMOS transistor has its source connected to the drain of the eleventh NMOS transistor, its gate connected to the gate of the fourteenth NMOS transistor, and its drain connected to the source of the second NMOS transistor.

[0171] The branch current replication module 502 includes:

[0172] The eleventh PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the gate of the ninth PMOS transistor.

[0173] The twelfth PMOS transistor has its source connected to the drain of the eleventh PMOS transistor, its gate connected to the gate of the tenth PMOS transistor, and its drain connected to the source of the second NMOS transistor.

[0174] As an example, the V HALF The current replication module 501 generates current I based on the current I1 flowing through the tenth NMOS transistor. COPY1 The branch current replication module 502 generates current I based on the current I2 flowing through the ninth PMOS transistor. COPY2 .

[0175] In this embodiment, the unit reference current generation circuit 60 includes a thirteenth NMOS transistor, the source of which is grounded and the gate of which is connected to an external bias V. REF At the output terminal, the drain of the thirteenth NMOS transistor is connected to the source of the second NMOS transistor.

[0176] like Figure 4 As shown, the present invention also provides a method for subthreshold data readout of a three-dimensional phase-change memory, comprising the following steps:

[0177] Step S1: After the first read enable signal RE1 is valid, the phase change memory array 20 selects the 1S1R phase change unit; the sensitive amplifier circuit 10 and the clamping voltage generation circuit 30 charge the phase change memory array 20.

[0178] Step S2, the word line half-bias voltage generation circuit 40 stabilizes the half-biased word line of the phase-change memory array 20 at V. HALF Voltage; the sensitive amplifier circuit 10 and the clamping voltage generation circuit 30 clamp the bit line voltage V of the phase-change memory array 20. BL The current replication circuit 50 replicates the V respectively. HALF Current and the branch current.

[0179] Step S3, when the V HALF Voltage and the bit line voltage V BL After stabilization, read the bit line current I. BL and the reference bit line current I BLB .

[0180] In step S4, after the first read enable signal RE1 is invalid and the second read enable signal RE2 is valid, the sensitive amplifier circuit 10 disconnects the first, second, third, and fourth NMOS transistors and amplifies the voltages SA1 and SA2 based on the charge stored on the capacitors C1 and C2.

[0181] In step S5, the comparison circuit 102 shifts the voltages of the differential signals SA1 and SA2, compares them, and outputs the readout voltage.

[0182] As an example, the read step S1 begins when the first read enable signal RE1 rises to the power supply voltage, and the read step S4 begins when the first read enable signal RE1 drops to ground from the power supply voltage and the second read enable signal RE2 rises to the power supply voltage.

[0183] In the above readout method, the bit line voltage V BL The low-resistance threshold voltage is less than that of the 1S1R phase-change memory cell. The bit line current I... BL Unit current I CELL and leakage current I LEAK The sum of the reference bit line current I. BLB For I COPY1 +I REF -I COPY2The unit reference current generation circuit 60 is based on the voltage V. REF Generate reference current I REF The reference current is between the low-resistivity subthreshold current and the high-resistivity subthreshold current of a single 1S1R phase-change memory cell.

[0184] When the subthreshold data readout circuit of the three-dimensional phase-change memory in this embodiment reads the phase-change memory cell, the voltage simulation results are as follows: Figure 5 and Figure 6 As shown in the figure, the subthreshold read time of the low-resistivity phase-change memory cell is 41.5 ns, and the subthreshold read time of the high-resistivity phase-change memory cell is 43 ns. Therefore, the subthreshold data readout circuit of this embodiment solves the problem of the small read margin window limiting the size of the memory array in the subthreshold read operation of the three-dimensional phase-change memory. It introduces a word line half-bias voltage generation circuit and a clamping voltage generation circuit, which accelerates the voltage stabilization speed, allows for accurate replication of leakage current, shortens the subthreshold data readout speed of the phase-change memory, simplifies the read operation steps and control signals, and makes operation convenient.

Claims

1. A subthreshold data readout circuit for a three-dimensional phase-change memory, characterized in that, include: The sensitive amplifier circuit is connected to the phase-change memory array via the bit line to compare the bit line current and the reference bit line current, and outputs a data readout voltage signal. A clamping voltage generation circuit, connected to the sensitive amplifier circuit, is used to provide a clamping voltage to the sensitive amplifier circuit, thereby clamping the voltage of the bit lines of the phase-change memory array. A word line half-bias voltage generation circuit, connected to the phase-change memory array, is used to provide word line half-bias voltage to the phase-change memory array; A current replication circuit, connected to the word line half-bias voltage generation circuit and the sensitive amplifier circuit, is used to counteract the leakage current generated by the phase-change memory array; the current replication circuit includes V HALF Current replication module and branch current replication module: The V HALF The current replication module includes: The eleventh NMOS transistor has its source grounded and its gate connected to the gate of the tenth NMOS transistor in the word line half-bias voltage generation circuit. The twelfth NMOS transistor has its source connected to the drain of the eleventh NMOS transistor, its gate connected to the external bias VB1 output terminal, and its drain connected to the sensitive amplifier circuit. The branch current replication module includes: The eleventh PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the external bias VB2 output terminal. The twelfth PMOS transistor has its source connected to the drain of the eleventh PMOS transistor, its gate connected to the external bias VB3 output terminal, and its drain connected to the sensitive amplifier circuit. The V HALF The current replication module generates a first replication current based on the current flowing through the tenth NMOS transistor; the branch current replication module generates a second replication current based on the current flowing through the ninth PMOS transistor in the word line half-bias voltage generation circuit. A unit reference current generation circuit, connected to the current replication circuit and the sensitive amplifier circuit, is used to generate a single unit reference current.

2. The subthreshold data readout circuit of the three-dimensional phase-change memory according to claim 1, characterized in that, The sensitive amplifier circuit includes a current sensing circuit and a comparator circuit; The current sensing circuit is connected to the bit line and the reference bit line, and is used to collect the bit line current and the reference bit line current, and convert the bit line current and the reference bit line current into differential voltage signals; The comparison circuit includes a level shifting circuit, a self-biased voltage comparator, and an output inverter. The level shifting circuit is connected to the read current sensing circuit and is used to convert the differential voltage signal into a value that the self-biased voltage comparator can process; the self-biased voltage comparator is connected to the level shifting circuit and is used to compare the processed differential voltage signal; the output inverter is connected to the self-biased voltage comparator and is used to convert the comparison result of the self-biased voltage comparator into a read voltage signal.

3. The subthreshold data readout circuit of the three-dimensional phase-change memory according to claim 2, characterized in that, The current sensing circuit includes: The first PMOS transistor has its source connected to the power supply voltage input terminal. The source of the second PMOS transistor is connected to the power supply voltage input terminal; The first NMOS transistor has its drain connected to the drain of the first PMOS transistor, and its gate connected to the clamping voltage generation circuit. The second NMOS transistor has its drain connected to the drain of the second PMOS transistor and its gate connected to the gate of the first NMOS transistor. The third NMOS transistor has its source connected to the drain of the first PMOS transistor, its drain connected to the gate of the first PMOS transistor, and its gate connected to the external first read enable signal RE1. The fourth NMOS transistor has its source connected to the drain of the second PMOS transistor, its drain connected to the gate of the second PMOS transistor, and its gate connected to the external first read enable signal RE1. A first capacitor, wherein a first port of the first capacitor is connected to the gate of the second PMOS transistor, and a second port is connected to the drain of the first PMOS transistor; The second capacitor C2 has its first port connected to the gate of the first PMOS transistor and its second port connected to the drain of the second PMOS transistor.

4. The subthreshold data readout circuit of the three-dimensional phase-change memory according to claim 3, characterized in that, The level shifting circuit includes: The fifteenth NMOS transistor has its source grounded and its gate connected to the external bias VB5 output terminal. The seventeenth NMOS transistor has its source connected to the drain of the fifteenth NMOS transistor and its gate connected to the drain of the first PMOS transistor. The drain serves as the second output terminal of the level shifting circuit. The thirteenth PMOS transistor has its source connected to the power supply voltage input terminal, its drain connected to the drain of the seventeenth NMOS transistor, and its gate connected to the inverted signal RE2N of the external second read enable signal RE2. The sixteenth NMOS transistor has its source grounded and its gate connected to the external bias VB5 output terminal. The eighteenth NMOS transistor has its source connected to the drain of the sixteenth NMOS transistor and its gate connected to the drain of the second PMOS transistor. The drain serves as the first output terminal of the level shifting circuit. The fourteenth PMOS transistor has its source connected to the power supply voltage input terminal, its drain connected to the drain of the eighteenth NMOS transistor, and its gate connected to the inverted signal RE2N of the external second read enable signal RE2.

5. The subthreshold data readout circuit of the three-dimensional phase-change memory according to claim 2, characterized in that, The self-biased voltage comparator includes: The nineteenth NMOS transistor, the source of which is grounded; The twentieth NMOS transistor has its source connected to the drain of the nineteenth NMOS transistor and its gate connected to the external second read enable signal RE2. The source of the 21st NMOS transistor is connected to the drain of the 20th NMOS transistor, and its gate is connected to the first output terminal of the level shifting circuit. The source of the 22nd NMOS transistor is connected to the drain of the 20th NMOS transistor, and the gate is connected to the second output terminal of the level shifting circuit. The fifteenth PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the gate of the nineteenth NMOS transistor and the drain of the twenty-first NMOS transistor. The sixteenth PMOS transistor, the source of which is connected to the drain of the fifteenth PMOS transistor, and the gate of which is connected to the inverted signal RE2N of the external second read enable signal RE2; The seventeenth PMOS transistor has its source connected to the drain of the sixteenth PMOS transistor, its gate connected to the gate of the twenty-first NMOS transistor, and its drain connected to the drain of the twenty-first NMOS transistor. The eighteenth PMOS transistor has its source connected to the drain of the sixteenth PMOS transistor, its gate connected to the gate of the twenty-second NMOS transistor, and its drain connected to the drain of the twenty-second NMOS transistor. It also serves as the output terminal of the self-biased voltage comparator.

6. The subthreshold data readout circuit of the three-dimensional phase-change memory according to claim 2, characterized in that, The output inverter includes: The 23rd NMOS transistor has its source grounded and its gate connected to the external second read enable signal RE2. The source of the 24th NMOS transistor is connected to the drain of the 23rd NMOS transistor, and its gate is connected to the output of the self-biased voltage comparator. The nineteenth PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the inverted signal RE2N of the external second read enable signal RE2. The twentieth PMOS transistor has its source connected to the drain of the nineteenth PMOS transistor, its gate connected to the gate of the twenty-fourth NMOS transistor, and its drain connected to the drain of the twenty-fourth NMOS transistor.

7. The subthreshold data readout circuit of the three-dimensional phase-change memory according to claim 1, characterized in that, The phase-change memory array includes 1S1R phase-change memory cells, bit line transmission gates, and word line transmission gates; The 1S1R phase change memory unit is composed of a phase change resistor PCM and a bidirectional threshold selector OTS connected in series. The bit line transmission gate includes a bit line gating transmission gate and a bit line half-bias transmission gate; the first transmission terminal of the bit line gating transmission gate is connected to the sensitive amplifier circuit, and the second transmission terminal of the bit line gating transmission gate is connected to one end of the 1S1R phase-change memory cell; the first transmission terminal of the bit line half-bias transmission gate is connected to an external bias voltage V / 2, and the second transmission terminal of the bit line half-bias transmission gate is connected to one end of the 1S1R phase-change memory cell. The word line transmission gate includes a word line gating transmission gate and a word line half-biased transmission gate. The first transmission terminal of the word line gating transmission gate is grounded, and the second transmission terminal of the word line gating transmission gate is connected to the other end of the 1S1R phase-change memory cell. The first transmission terminal of the word line half-bias transmission gate is connected to the word line half-bias voltage generation circuit, and the second transmission terminal of the word line half-bias transmission gate is connected to one end of the 1S1R phase-change memory cell.

8. The subthreshold data readout circuit of the three-dimensional phase-change memory according to claim 3, characterized in that, The clamping voltage generation circuit includes: The first inverter has its input terminal connected to an external first read enable signal RE1; The second inverter has its input terminal connected to an external second read enable signal RE2. The third PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the external bias VB4 output terminal. The fourth PMOS transistor has its source connected to the drain of the third PMOS transistor, and its gate connected to the external bias VRC output terminal. The fifth PMOS transistor has its source connected to the drain of the third PMOS transistor, its gate connected to the gate of the first NMOS transistor, and its drain connected to the source of the first NMOS transistor. The fifth NMOS transistor has its drain and gate connected to the drain of the fourth PMOS transistor, and its source grounded. The sixth NMOS transistor has its drain connected to the drain of the fifth PMOS transistor, its gate connected to the gate of the fifth NMOS transistor, and its source grounded. The seventh NMOS transistor has its drain connected to the gate of the fifth PMOS transistor, its source grounded, and its gate connected to the output of the first inverter.

9. The subthreshold data readout circuit of the three-dimensional phase-change memory according to claim 1, characterized in that, The word line half-bias voltage generation circuit includes: The sixth PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the external bias VB4 output terminal. The seventh PMOS transistor has its source connected to the drain of the sixth PMOS transistor and its gate connected to the output terminal of the external bias voltage V / 2. The eighth PMOS transistor, the source of which is connected to the drain of the sixth PMOS transistor; The eighth NMOS transistor has its drain and gate connected to the drain of the seventh PMOS transistor, and its source grounded. The ninth NMOS transistor has its drain connected to the drain of the eighth PMOS transistor, its gate connected to the gate of the eighth NMOS transistor, and its source grounded. The ninth PMOS transistor has its source connected to the power supply voltage input terminal and its gate connected to the external bias VB2 output terminal. The tenth PMOS transistor has its source connected to the drain of the ninth PMOS transistor and its gate connected to the external bias VB3 output terminal. A first resistor, the first port of which is connected to the drain of the tenth PMOS transistor, and the second port of which is connected to the gate of the eighth PMOS transistor; The tenth NMOS transistor has its source grounded and its gate connected to the drain of the eighth PMOS transistor. The fourteenth NMOS transistor has its source connected to the drain of the tenth NMOS transistor, its drain connected to the gate of the eighth PMOS transistor and the phase-change memory array, and its gate connected to the external bias VB1 output terminal. The second resistor Rm, the first port of the second resistor Rm is connected to the drain of the eighth PMOS transistor; The third capacitor Cc has its first port connected to the second port of the second resistor Rm, and its second port connected to the drain of the fourteenth NMOS transistor.

10. The subthreshold data readout circuit for a three-dimensional phase-change memory according to claim 1, characterized in that, The unit reference current generation circuit includes a thirteenth NMOS transistor, the source of which is grounded and the gate is connected to an external bias V. REF At the output terminal, the drain is connected to the sensitive amplifier circuit.

11. A method for subthreshold data readout from a three-dimensional phase-change memory, characterized in that, The circuit applied to the subthreshold data readout circuit of the three-dimensional phase-change memory as described in any one of claims 1-10 includes the following steps: (1) After the first read enable signal RE1 is valid, the phase change memory array selects the 1S1R phase change unit; the sensitive amplifier circuit and the clamping voltage generation circuit charge the phase change memory array. (2) The word line half-bias voltage generation circuit stabilizes the half-biased word line of the phase-change memory array at V. HALF Voltage; the sensitive amplifier circuit and the clamping voltage generation circuit clamp the bit line voltage V of the phase-change memory array. BL The current replication circuit replicates the V respectively. HALF Current and branch current; (3) When the V HALF Voltage and the bit line voltage V BL After stabilization, read the bit line current I. BL and reference bit line current I BLB ; (4) After the first read enable signal RE1 is invalid and the second read enable signal RE2 is valid, the sensitive amplifier circuit disconnects the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor, and amplifies the voltage SA1 and the voltage SA2 based on the charge stored on the first capacitor C1 and the second capacitor C2. (5) The comparison circuit performs voltage shift on the differential signals of voltage SA1 and voltage SA2, compares them, and outputs the read voltage.

12. The subthreshold data readout method for a three-dimensional phase-change memory according to claim 11, characterized in that, The reading step (1) begins when the first read enable signal RE1 rises to the power supply voltage, and the reading step (4) begins when the first read enable signal RE1 drops to ground from the power supply voltage and the second read enable signal RE2 rises to the power supply voltage.

13. The subthreshold data readout method for a three-dimensional phase-change memory according to claim 11, characterized in that, The unit reference current generation circuit is based on voltage V. REF Generate reference current I REF The reference current is between the low-resistivity subthreshold current and the high-resistivity subthreshold current of a single 1S1R phase-change memory cell; the bit line current I BL Unit current I CELL and leakage current I LEAK sum; The reference bit line current I BLB First replication current + reference current I REF - Second replication current; the bit line voltage V BL The low resistance threshold voltage is less than that of the 1S1R phase change memory cell.

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