Mask structure and method of forming the same, method of forming a semiconductor structure
By forming central and edge regions in the mask layer and filling the mask holes in the edge regions with blocking parts, the problem of aperture defect transfer during etching is solved, thereby improving the stability of aperture within the mask layer and increasing product yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-06-15
- Publication Date
- 2026-06-23
Smart Images
Figure CN116646239B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a mask structure and a method for forming the same, and a method for forming a semiconductor structure. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as smartphones and tablets due to its advantages of small size, high integration, and high transfer speed. The mask structure is one of the important structures in the DRAM manufacturing process. However, structural defects are prone to occur during the etching process to form the mask pattern, resulting in low product yield.
[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0004] In view of this, the present disclosure provides a mask structure and a method for forming the same, as well as a method for forming a semiconductor structure, which can reduce structural defects and improve product yield.
[0005] According to one aspect of this disclosure, a method for forming a mask structure is provided, the mask structure being formed on a substrate, comprising:
[0006] A first mask layer is formed on the substrate;
[0007] A second mask layer is formed on the surface of the first mask layer. The second mask layer includes a first region and a second region. The first region includes a central region and an edge region surrounding the outer periphery of the central region. The second region is located on the side of the edge region away from the central region and is adjacent to the edge region.
[0008] The second mask layer is etched to form a first mask hole and a second mask hole within the second mask layer, wherein the first mask hole is located in the central region, the second mask hole is located in the edge region, and the second mask hole is distributed adjacent to the second region;
[0009] Fill the second mask hole with a blocking portion;
[0010] The first mask layer is etched using the second mask layer and the blocking portion as masks to form a target mask hole, wherein the etching rate of the blocking portion is less than the etching rate of the first mask layer.
[0011] In one exemplary embodiment of this disclosure, the aperture of the second mask aperture is smaller than the aperture of the first mask aperture in a direction parallel to the substrate, and a blocking portion is filled within the second mask aperture, including:
[0012] A barrier material is formed on the surface of the second mask layer having the first mask aperture and the second mask aperture, the barrier material filling the first mask aperture and the second mask aperture, and in a direction perpendicular to the substrate, the height of the barrier material located in the second mask aperture is greater than the height of the barrier material located in the first mask aperture;
[0013] The blocking material is etched until the blocking material located in the first mask hole is removed, and the remaining blocking material in the second mask hole is used as a blocking part.
[0014] In one exemplary embodiment of this disclosure, the material of the blocking portion is titanium oxide or zirconium oxide, the material of the first mask layer is at least one of amorphous silicon, silicon nitride, or silicon oxide, and the material of the second mask layer is at least one of silicon oxide, photoresist, spin-coated organic carbon, or spin-coated silicon glass.
[0015] In one exemplary embodiment of this disclosure, the forming method further includes:
[0016] After the target mask hole is formed, the second mask layer and the blocking portion are removed.
[0017] In one exemplary embodiment of this disclosure, the height of the blocking portion is 5 nm to 10 nm in the direction perpendicular to the substrate.
[0018] In one exemplary embodiment of this disclosure, etching the first mask layer using the second mask layer and the blocking portion as masks to form a target mask hole, wherein the etching rate of the blocking portion is less than the etching rate of the first mask layer, includes:
[0019] The first mask layer is etched using a dry etching process, wherein the etching gas used in the dry etching process includes a mixture of carbon tetrafluoride, chlorine and boron chloride, or a mixture of oxygen and nitrogen.
[0020] In one exemplary embodiment of this disclosure, there are multiple first mask holes and multiple second mask holes. The multiple first mask holes are distributed at intervals in the central region, and each second mask hole is distributed at intervals along the edge region and surrounds the central region.
[0021] According to one aspect of this disclosure, a mask structure is provided, said mask structure being formed by the method for forming a mask structure as described in any one of the preceding claims.
[0022] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:
[0023] A substrate is provided, the substrate comprising a base and stacked film layers formed on the surface of the base;
[0024] A mask structure as described in any one of the above is formed on the surface of the stacked film layers;
[0025] The stacked film layers are etched using the mask structure as a mask to form capacitor holes within the stacked film layers.
[0026] In one exemplary embodiment of this disclosure, the forming method further includes:
[0027] A lower electrode layer is formed within the capacitor hole.
[0028] The mask structure and its formation method disclosed herein, as well as the semiconductor structure formation method, can fill the second mask hole adjacent to the second region with a blocking portion. Since the etching rate of the blocking portion is lower than the etching rate of the first mask layer, during the etching process to form the target mask hole, the second mask hole is blocked by the blocking portion, thus preventing the second mask hole from being transferred into the first mask layer. This avoids the defect that the aperture of the second mask hole is smaller than the aperture of the first mask hole, which occurs during the etching process to form the first and second mask holes, from being transferred into the first mask layer. This ensures that the aperture of the target mask hole finally formed in the first mask layer is within the expected size range, which helps to reduce the size defect of the capacitor hole formed subsequently using the first mask layer with the target mask hole as a mask, thereby reducing the probability of structural defects occurring during the formation of the capacitor structure due to the size defect of the capacitor hole.
[0029] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0031] Figure 1 This is a schematic diagram of a semiconductor structure in related technologies.
[0032] Figure 2 This is a schematic diagram of the substrate in an embodiment of this disclosure.
[0033] Figure 3This is a flowchart of a method for forming a mask structure in an embodiment of this disclosure.
[0034] Figure 4 This is a schematic diagram of a portion of the first and second mask layers in an embodiment of this disclosure.
[0035] Figure 5 This is a schematic diagram of the first mask hole and the second mask hole in an embodiment of this disclosure.
[0036] Figure 6 This is a top view of the first mask hole and the second mask hole in an embodiment of this disclosure.
[0037] Figure 7 For the embodiments of this disclosure along Figure 4 A cross-sectional view taken along the aa' direction.
[0038] Figure 8 After completing step S140 in this embodiment of the present disclosure, along Figure 4 A cross-sectional view taken along the aa' direction.
[0039] Figure 9 After completing step S210 in this embodiment of the present disclosure, along Figure 4 A cross-sectional view taken along the aa' direction.
[0040] Figure 10 This is a schematic diagram of the target mask hole in an embodiment of this disclosure.
[0041] Figure 11 This is a schematic diagram of the lower electrode layer in an embodiment of this disclosure.
[0042] Explanation of reference numerals in the attached figures:
[0043] 100, Substrate; 200, Support layer; 300, Capacitor via; 400, Lower electrode layer; A, Array region; B, Peripheral region; 1, Substrate; 11, Base; 111, Storage node contact plug; 12, Stacked film layers; 121, First support layer; 122, First sacrificial layer; 123, Second support layer; 124, Second sacrificial layer; 125, Third support layer; 120, Capacitor via; 2, First mask layer; 201, Target mask via; 3, Second mask layer; 301, First mask via; 302, Second mask via; 31, First region; 311, Central region; 312, Edge region; 32, Second region; 4, Barrier portion; 410, Barrier material; 5, Lower electrode layer; a, Array region; b, Peripheral region. Detailed Implementation
[0044] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.
[0045] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.
[0046] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first” and “second” are used only as markers and are not a limitation on the number of objects.
[0047] The capacitor structure fabrication process includes: forming multiple alternately distributed support layers 200 and sacrificial layers on a substrate 100; etching each support layer 200 and each sacrificial layer to form capacitor holes 300; forming a lower electrode layer 400 of the capacitor structure within the capacitor holes 300; and removing the sacrificial layer by wet etching. However, during the etching process to form the capacitor holes 300, due to the influence of the fabrication process, the size of the capacitor holes 300 located at the junction of the array region A and the peripheral region B of the substrate 100 is relatively small. During the subsequent deposition of the lower electrode layer 400 of the capacitor structure, the small-sized capacitor holes 300 are easily sealed prematurely, preventing the deposition of the lower electrode layer 400 inside. During the subsequent wet etching process to remove the sacrificial layer, the etching solution easily penetrates into the peripheral region B through the small-sized capacitor holes 300, damaging the circuit structure within the peripheral region B and leading to structural defects (such as…). Figure 1 (As shown).
[0048] Based on this, embodiments of this disclosure provide a method for forming a mask structure, such as... Figure 2As shown, the mask structure is formed on a substrate 1, which may include a base 11 and a stacked film layer 12 formed on the surface of the base 11, wherein:
[0049] The substrate 11 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape. Its material may be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 11 here.
[0050] The base 11 may include an array region a and a peripheral region b. The array region a and the peripheral region b may be adjacent to each other, and the peripheral region b may surround the outer perimeter of the array region a. For example, the array region a may be a circular region, a rectangular region, or an irregularly shaped region; of course, it may also be a region of other shapes, without special limitation here. The peripheral region b may be a ring-shaped region and may surround the outer perimeter of the array region a. It may be a circular ring region, a rectangular ring region, or a ring region of other shapes, which will not be listed here.
[0051] Array region a can be used to form capacitor arrays, transistor arrays, word line structures and bit line structures connecting transistors and capacitors, while peripheral region b can be used to form word line contact plugs. The word line contact plugs can connect to word line drivers, sense amplifiers, row decoders and column decoders, as well as special-function control circuits located in peripheral region b. The control circuits can control the word lines and bit lines to realize the storage and reading functions of transistors and capacitors. In some embodiments of this disclosure, array region a may have multiple spaced storage node contact plugs 111.
[0052] The stacked film layer 12 may include a first support layer 121, a first sacrificial layer 122, a second support layer 123, a second sacrificial layer 124 and a third support layer 125, which are sequentially stacked along a direction perpendicular to the substrate 1, wherein the first support layer 121 covers the surface of the substrate 11.
[0053] Figure 3 A flowchart illustrating the method for forming the mask structure of this disclosure is shown; please refer to [link / reference]. Figure 3 As shown, the forming method includes steps S110-S150, wherein:
[0054] Step S110: A first mask layer is formed on the substrate;
[0055] Step S120: A second mask layer is formed on the surface of the first mask layer. The second mask layer includes a first region and a second region. The first region includes a central region and an edge region surrounding the outer periphery of the central region. The second region is located on the side of the edge region away from the central region and is adjacent to the edge region.
[0056] Step S130: Etch the second mask layer to form a first mask hole and a second mask hole in the second mask layer. The first mask hole is located in the central region, and the second mask hole is located in the edge region, and the second mask hole is distributed adjacent to the second region.
[0057] Step S140: Fill the second mask hole with a blocking portion;
[0058] Step S150: Using the second mask layer and the blocking portion as masks, the first mask layer is etched to form a target mask hole, wherein the etching rate of the blocking portion is less than the etching rate of the first mask layer.
[0059] The mask structure formation method disclosed herein can fill the second mask hole adjacent to the second region with a blocking portion. Since the etching rate of the blocking portion is lower than the etching rate of the first mask layer, the second mask hole will not be transferred to the first mask layer during the etching process of forming the target mask hole because the second mask hole is blocked by the blocking portion. This avoids the defect that the aperture of the second mask hole is smaller than the aperture of the first mask hole during the etching process of forming the first and second mask holes from being transferred to the first mask layer. This ensures that the aperture of the target mask hole finally formed in the first mask layer is within the expected size range, which helps to reduce the size defect of the capacitor hole formed subsequently using the first mask layer with the target mask hole as a mask, thereby reducing the probability of structural defects occurring during the formation of the capacitor structure due to the size defect of the capacitor hole.
[0060] The following provides a detailed description of each step and specific details of the method for forming the mask structure disclosed herein:
[0061] like Figure 3 As shown, in step S110, a first mask layer 2 is formed on the substrate 1.
[0062] like Figure 4 As shown, the first mask layer 2 can be a thin film formed on the surface of the substrate 1, or it can be a coating formed on the surface of the substrate 1. No specific limitation is made to the specific form of the first mask layer 2. In some embodiments of this disclosure, the material of the first mask layer 2 can be at least one of amorphous silicon, silicon nitride, or silicon oxide. The first mask layer 2 can be formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the first mask layer 2 can also be formed by other methods. No specific limitation is made to the formation method of the first mask layer 2.
[0063] like Figure 3As shown, in step S120, a second mask layer 3 is formed on the surface of the first mask layer 2. The second mask layer 3 includes a first region 31 and a second region 32. The first region 31 includes a central region 311 and an edge region 312 surrounding the outer periphery of the central region 311. The second region 32 is located on the side of the edge region 312 away from the central region 311 and is adjacent to the edge region 312.
[0064] Please continue reading Figure 4 As shown, the material of the second mask layer 3 is different from that of the first mask layer 2. For example, the material of the second mask layer 3 can be at least one of silicon oxide, photoresist, spin-coated organic carbon, or spin-coated silicon glass. The second mask layer 3 can be formed on the surface of the first mask layer 2 through processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, in-situ water vapor oxidation, or thermal oxidation. Of course, the second mask layer 3 can also be formed by other methods, and no special limitation is made on the formation method of the second mask layer 3 here. The thickness of the second mask layer 3 can be 400nm to 600nm. For example, its thickness can be 400nm, 450nm, 500nm, 550nm, or 600nm. Of course, the second mask layer 3 can also have other thicknesses, which will not be listed here.
[0065] In an exemplary embodiment of this disclosure, the second mask layer 3 may include a first region 31 and a second region 32 distributed adjacent to each other, wherein the orthographic projection of the first region 31 on the substrate 1 is located in the array region a, and the boundary of its projection coincides with the boundary of the array region a; the orthographic projection of the second region 32 on the substrate 1 is located in the peripheral region b, and the boundary of its projection coincides with the boundary of the peripheral region b.
[0066] In some embodiments of this disclosure, the first region 31 may include a central region 311 and an edge region 312 surrounding the central region 311. The central region 311 may be a rectangular region, a circular region, an elliptical region, a polygonal region, or an irregularly shaped region, without particular limitation. The edge region 312 may be annular and may surround the periphery of the central region 311, and the inner ring of the edge region 312 may be adjacent to the boundary of the central region 311. The second region 32 may be annular and may be located on the side of the edge region 312 away from the central region 311. For example, the second region 32 may surround the periphery of the edge region 312, and its inner ring may be adjacent to the outer ring of the edge region 312.
[0067] like Figure 3As shown, in step S130, the second mask layer 3 is etched to form a first mask hole 301 and a second mask hole 302 in the second mask layer 3. The first mask hole 301 is located in the central region 311, and the second mask hole 302 is located in the edge region 312. The second mask hole 302 is distributed adjacent to the second region 32.
[0068] like Figures 5-7 As shown, the second mask layer 3 can be etched by a dry etching process to form a first mask hole 301 and a second mask hole 302 spaced apart in the second mask layer 3. During the etching process to form the first mask hole 301 and the second mask hole 302, due to process limitations, the aperture of the second mask hole 302 formed in the direction parallel to the substrate 1 is smaller than the aperture of the first mask hole 301.
[0069] In some embodiments of this disclosure, there are multiple first mask holes 301 and multiple second mask holes 302. The multiple first mask holes 301 are distributed at intervals within the central region 311, and the multiple second mask holes 302 are distributed at intervals along the circumferential direction of the edge region 312 and surround the central region 311. That is, each second mask hole 302 is distributed adjacent to the second region 32 and covers the outer periphery of the central region 311.
[0070] Both the first mask aperture 301 and the second mask aperture 302 can be through-holes penetrating the second mask layer 3. In the direction parallel to the substrate 1, the cross-sectional shapes of the first mask aperture 301 and the second mask aperture 302 can be the same. For example, both the first mask aperture 301 and the second mask aperture 302 can be circular, elliptical, rectangular, polygonal, or irregularly shaped holes. No special limitations are placed on the shapes of the first mask aperture 301 and the second mask aperture 302. It should be noted that the different first mask apertures 301 have the same shape and basically the same size; that is, the size of each first mask aperture 301 is relatively uniform.
[0071] like Figure 3 As shown, in step S140, the blocking portion 4 is filled into the second mask hole 302.
[0072] The blocking portion 4 may or may not completely fill the second mask hole 302; the filling height of the blocking portion 4 is not specifically limited here. In some embodiments of this disclosure, such as Figure 8 As shown, the blocking part 4 does not fill the second mask hole 302, and in the direction perpendicular to the substrate 1, the height of the blocking part 4 can be 5nm to 10nm. For example, it can be 5nm, 6nm, 7nm, 8nm, 9nm or 10nm. Of course, the blocking part 4 can also be other heights, which will not be listed here.
[0073] The blocking portion 4 may have a higher etch selectivity relative to the first mask layer 2. In some embodiments of this disclosure, the etch selectivity of the blocking portion 4 relative to the first mask layer 2 may be greater than or equal to 5. For example, the etch selectivity of the blocking portion 4 relative to the first mask layer 2 may be 5, 10, 15, or 20. Of course, other values are also possible, which will not be listed here. For example, the material of the first mask layer 2 may include amorphous silicon, and the material of the blocking portion 4 may be titanium oxide. Alternatively, the material of the first mask layer 2 may include silicon oxide, silicon nitride, or amorphous silicon, and the material of the blocking portion 4 may be zirconium oxide. Since zirconium oxide has a higher etch selectivity than silicon oxide, silicon nitride, and amorphous silicon, when using it as a mask to etch films made of silicon oxide, silicon nitride, and amorphous silicon, it can better protect the underlying film structure and reduce structural defects. At the same time, zirconium oxide also has the characteristics of low stress, high planarization, high hardness, and good gap filling, which allows it to fill the first mask hole 301 and the second mask hole 302 well.
[0074] In one exemplary embodiment of this disclosure, filling the blocking portion 4 within the second mask hole 302 (i.e., step S140) includes steps S210 and S220, wherein:
[0075] In step S210, a barrier material 410 is formed on the surface of the second mask layer 3 having the first mask hole 301 and the second mask hole 302. The barrier material 410 fills the first mask hole 301 and the second mask hole 302, and in the direction perpendicular to the substrate 1, the height of the barrier material 410 located in the second mask hole 302 is greater than the height of the barrier material 410 located in the first mask hole 301.
[0076] like Figure 9 As shown, the barrier material 410 can be a material with a relatively high etching selectivity relative to the first mask layer 2. For example, the barrier material 410 can be titanium oxide or zirconium oxide. The barrier material 410 can be spin-coated on the surface of the second mask layer 3 by spin-coating or other methods. During this process, the barrier material 410 has a high degree of planarization and can fill the first mask hole 301 and the second mask hole 302 well. When the barrier material 410 is spin-coated into the first mask hole 301 and the second mask hole 302 at the same speed, the volume of the spin coating liquid entering the first mask hole 301 with a larger aperture is approximately equal to the volume of the spin coating liquid entering the second mask hole with a smaller aperture. Since the aperture of the second mask hole 302 is smaller than the aperture of the first mask hole 301, the height of the barrier material 410 filled in the second contact hole is higher than the height of the barrier material 410 filled in the first contact hole.
[0077] For example, the height of the barrier material 410 filling the first mask aperture 301 is 15nm to 25nm, and the height of the barrier material 410 filling the second mask aperture 302 is 30nm to 40nm. For example, the height of the barrier material 410 in the first mask aperture 301 is 15nm, and the height of the barrier material 410 in the second mask aperture 302 is 30nm; or, the height of the barrier material 410 in the first mask aperture 301 is 20nm, and the height of the barrier material 410 in the second mask aperture 302 is 35nm; or, the height of the barrier material 410 in the first mask aperture 301 is 25nm, and the height of the barrier material 410 in the second mask aperture 302 is 40nm, etc.
[0078] Step S220: Etch the blocking material 410 until the blocking material 410 located in the first mask hole 301 is removed, and the remaining blocking material 410 in the second mask hole 302 is used as the blocking part 4.
[0079] After filling the first mask aperture 301 and the second mask aperture 302 with barrier material 410, the barrier material 410 can be etched back using a dry etching process to remove the barrier material 410 located on top of the second mask layer 3 and the barrier material 410 located in the first mask aperture 301. During the etch-back process, the barrier material 410 located in the second mask aperture 302 is also consumed and its height is reduced. For example, during the back etching process, the first mask layer 2 located at the bottom of the first mask hole 301 can be used as an etching stop layer to simultaneously etch back the blocking material 410 in the first mask hole 301 and the second mask hole 302. During this process, since the height of the blocking material 410 in the first mask hole 301 is less than the height of the blocking material 410 in the second mask hole 302, when the blocking material 410 in the first mask hole 301 is completely etched away (i.e., there is no blocking material 410 in the first mask hole 301), a portion of the blocking material 410 is still retained in the second mask hole 302. The remaining blocking material 410 in the second mask hole 302 can be used as the blocking part 4.
[0080] In some embodiments of this disclosure, after forming the blocking portion 4, the second mask layer 3 can be etched back to reduce its thickness, which helps to reduce the process difficulty in the subsequent etching of the first mask layer 2. It should be noted that the surface of the remaining second mask layer 3 after the back etching is higher than the surface of the blocking portion 4.
[0081] like Figure 3As shown, in step S150, the first mask layer 2 is etched using the second mask layer 3 and the blocking part 4 as masks to form the target mask hole 201. The etching rate of the blocking part 4 is less than the etching rate of the first mask layer 2.
[0082] like Figure 10 As shown, the second mask layer 3 with the first mask hole 301 and the blocking part 4 can work together as a mask to etch the first mask layer 2 below the second mask layer 3, thereby forming the target mask hole 201 in the first mask layer 2. In the above process, since the second mask hole 302 is blocked by the blocking part 4, the second mask hole 302 will not be transferred into the first mask layer 2. This avoids transferring the smaller second mask hole 302 into the first mask layer 2, ensuring that the diameter of the target mask hole 201 finally formed in the first mask layer 2 is within a relatively large size range. This helps to reduce the size defects of the capacitor holes formed subsequently using the first mask layer 2 with the target mask hole 201 as a mask, thereby reducing the probability of structural defects occurring during the formation of the lower electrode layer due to the size defects of the capacitor holes.
[0083] In some embodiments of this disclosure, a dry etching process can be used to etch back the first mask layer 2. The etching gas for dry etching may include carbon tetrafluoride, a mixture of chlorine and boron chloride, or a mixture of oxygen and nitrogen. Of course, other gases may also be used to etch back the first mask layer 2. No special limitation is made here on the etching gas for the first mask layer 2.
[0084] It should be noted that the number of target mask holes 201 is equal to the number of first mask holes 301. For example, when there are multiple first mask holes 301, there are also multiple target mask holes 201, and a target mask hole 201 can be formed below each first mask hole 301. Since the different first mask holes 301 have relatively uniform sizes, the sizes of the target mask holes 201 formed using them as masks are also relatively uniform.
[0085] In one exemplary embodiment of this disclosure, the method for forming the mask structure may further include:
[0086] Step S160: After forming the target mask hole 201, the second mask layer 3 and the blocking part 4 are removed.
[0087] In some embodiments of this disclosure, after forming the target mask hole 201, the thickness of the first mask layer 2 containing the target mask hole 201 can be reduced, thereby reducing the process difficulty in the subsequent etching process of the substrate 1. In this process, the second mask layer 3 and the blocking portion 4 can be removed simultaneously. That is, the second mask layer 3 and the blocking portion 4 can be consumed during the thinning of the first mask layer 2, thereby removing the second mask layer 3 and the blocking portion 4.
[0088] For example, the first mask layer 2 can be thinned and the second mask layer 3 and the barrier portion 4 can be removed by a dry etching process. The etching gas for dry etching can be set according to the specific materials of the second mask layer 3, the barrier portion 4 and the first mask layer 2, as long as it can remove the second mask layer 3 and the barrier portion 4 and thin the first mask layer 2. No special limitation is made to the etching gas here.
[0089] It should be noted that although the steps of the mask structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.
[0090] This disclosure also provides a mask structure, which is formed by the mask structure forming method in any of the above embodiments. Its specific structure and beneficial effects have been described in detail in the embodiments of the mask structure forming method, and therefore will not be repeated here.
[0091] This disclosure also provides a method for forming a semiconductor structure, the method comprising steps S310-S330, wherein:
[0092] Step S310: Provide a substrate 1, the substrate 1 including a base 11 and a stacked film layer 12 formed on the surface of the base 11.
[0093] Step S320: Form the mask structure described in any of the above embodiments on the surface of the stacked film layer 12;
[0094] Step S330: Using the mask structure as a mask, the stacked film layer 12 is etched to form capacitor holes in the stacked film layer 12.
[0095] The semiconductor structure formation method disclosed herein has a relatively uniform aperture size for each target mask hole 201 in the mask structure, and the aperture size for each capacitor hole formed using it as a mask is also relatively uniform. Furthermore, the aperture size of each capacitor hole is kept within the expected size range, and there will be no situation where the aperture size of the capacitor holes in some areas is too small. In the subsequent process of forming the lower electrode layer 5 in the capacitor holes, the capacitor holes are not easy to seal prematurely, which can ensure that each capacitor hole is filled with the lower electrode layer 5. This can reduce the probability of the etching solution penetrating into the peripheral region b of the substrate 1 during the subsequent wet etching process to remove part of the film layer 12, thereby reducing the probability of circuit structure damage in the peripheral region b and reducing structural defects.
[0096] The steps and specific details of the semiconductor structure formation method disclosed herein are described in detail below:
[0097] In step S310, a substrate 1 is provided, the substrate 1 including a base 11 and a stacked film layer 12 formed on the surface of the base 11.
[0098] like Figure 2 As shown, the substrate 11 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 11 here.
[0099] The base 11 may include an array region a and a peripheral region b. The array region a and the peripheral region b may be adjacent to each other, and the peripheral region b may surround the outer perimeter of the array region a. For example, the array region a may be a circular region, a rectangular region, or an irregularly shaped region; of course, it may also be a region of other shapes, without special limitation here. The peripheral region b may be a ring-shaped region and may surround the outer perimeter of the array region a. It may be a circular ring region, a rectangular ring region, or a ring region of other shapes, which will not be listed here.
[0100] Array region a can be used to form capacitor arrays, transistor arrays, word line structures and bit line structures connecting transistors and capacitors, while peripheral region b can be used to form word line contact plugs. The word line contact plugs can connect to word line drivers, sense amplifiers, row decoders and column decoders, as well as special-function control circuits located in peripheral region b. The control circuits can control the word lines and bit lines to realize the storage and reading functions of transistors and capacitors. In some embodiments of this disclosure, array region a may have multiple spaced storage node contact plugs 111.
[0101] The stacked film layer 12 may include a first support layer 121, a first sacrificial layer 122, a second support layer 123, a second sacrificial layer 124, and a third support layer 125 sequentially stacked along a direction perpendicular to the substrate 1, wherein the first support layer 121 covers the surface of the substrate 11. The first support layer 121, the second support layer 123, and the third support layer 125 may be made of the same material; for example, the first support layer 121, the second support layer 123, and the third support layer 125 may all be made of silicon nitride. The first sacrificial layer 122 and the second sacrificial layer 124 may also be made of the same material; for example, the first sacrificial layer 122 and the second sacrificial layer 124 may both be made of silicon oxide.
[0102] In step S320, a mask structure as described in any of the above embodiments is formed on the surface of the stacked film layer 12.
[0103] A mask structure can be formed on the surface of the stacked film layer 12 by the mask structure formation method in any of the above embodiments.
[0104] Step S330: Using the mask structure as a mask, the stacked film layer 12 is etched to form a capacitor hole 120 in the stacked film layer 12.
[0105] like Figure 11 As shown, the target mask aperture 201 in the mask structure can be used as a mask to transfer the mask pattern (e.g., the target mask aperture 201) to the stacked film layer 12 to form capacitor apertures 120. When there are multiple target mask apertures 201, there can also be multiple capacitor apertures 120. A capacitor aperture 120 can be formed below each target mask aperture 201, and each capacitor aperture 120 can expose the contact plugs 111 of each memory node. For example, the stacked film layer 12 can be etched using a dry etching process to form capacitor apertures 120. In this process, since the apertures of the target mask apertures 201 in the mask structure are relatively uniform, the apertures of the capacitor apertures 120 formed using them as masks are also relatively uniform, and the apertures of each capacitor aperture 120 are kept within the expected size range, without any situation where the aperture of the capacitor aperture 120 in some areas is too small.
[0106] In one exemplary embodiment of this disclosure, the method for forming the semiconductor structure of this disclosure may further include:
[0107] Step S340: A lower electrode layer 5 is formed within the capacitor hole 120.
[0108] The lower electrode layer 5, which conformally covers the capacitor aperture 120, can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The lower electrode layer 5 can be contacted and connected to the storage node contact plug 111 at the bottom of the capacitor aperture 120, so as to input the charge stored in the lower electrode layer 5 to the storage node contact plug 111, thereby realizing charge storage. In some embodiments of this disclosure, the material of the lower electrode layer 5 can be a material with good conductivity, for example, titanium nitride. Of course, other materials that can be used as electrodes can also be used, and no special limitation is made to the material of the lower electrode layer 5 here.
[0109] After forming the lower electrode layer 5, the third support layer 125 can be etched to form a first opening exposing the second sacrificial layer 124. The second sacrificial layer 124 can then be removed by wet etching through the first opening. After removing the second sacrificial layer 124, the second support layer 123 can be etched to form a second opening exposing the first sacrificial layer 122. The first sacrificial layer 122 can then be removed by wet etching through the second opening. During the removal of the first sacrificial layer 122 and the second sacrificial layer 124, since the lower electrode layer 5 is formed within each capacitor hole 120, there are no unfilled capacitor holes 120. The etching solution from the wet etching process will not penetrate into the peripheral region b through the unfilled capacitor holes 120, thus reducing the probability of damage to the circuit structure in the peripheral region b and reducing structural defects.
[0110] After removing the first sacrificial layer 122, a conformal capacitor dielectric layer can be formed on the surface of the structure jointly composed of the lower electrode layer 5, the first support layer 121, the remaining second support layer 123, and the remaining third support layer 125 through chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The capacitor dielectric layer can be a single-layer film structure made of the same material, or a hybrid film structure made of different materials. For example, it can include materials with a high dielectric constant, such as alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or mixtures thereof. Of course, other materials are also possible, which will not be listed here.
[0111] The top electrode layer can be formed on the surface of the capacitor dielectric layer through methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other processes can also be used to form the top electrode layer, and no special limitations are made here. The material of the top electrode layer can be titanium nitride, or other materials, which will not be listed here.
[0112] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A method for forming a mask structure on a substrate, the method comprising: include: A first mask layer is formed on the substrate; A second mask layer is formed on the surface of the first mask layer. The second mask layer includes a first region and a second region. The first region includes a central region and an edge region surrounding the outer periphery of the central region. The second region is located on the side of the edge region away from the central region and is adjacent to the edge region. The second mask layer is etched to form a first mask hole and a second mask hole within the second mask layer, wherein the first mask hole is located in the central region, the second mask hole is located in the edge region, and the second mask hole is distributed adjacent to the second region; Fill the second mask hole with a blocking portion; The first mask layer is etched using the second mask layer and the blocking portion as masks to form a target mask hole, wherein the etching rate of the blocking portion is less than the etching rate of the first mask layer; In a direction parallel to the substrate, the aperture of the second mask aperture is smaller than the aperture of the first mask aperture, and a blocking portion is filled within the second mask aperture, including: A barrier material is formed on the surface of the second mask layer having the first mask aperture and the second mask aperture, the barrier material filling the first mask aperture and the second mask aperture, and in a direction perpendicular to the substrate, the height of the barrier material located in the second mask aperture is greater than the height of the barrier material located in the first mask aperture; The blocking material is etched until the blocking material located in the first mask hole is removed, and the remaining blocking material in the second mask hole is used as a blocking part.
2. The forming method according to claim 1, characterized in that, The material of the blocking part is titanium oxide or zirconium oxide, the material of the first mask layer is at least one of amorphous silicon, silicon nitride or silicon oxide, and the material of the second mask layer is at least one of silicon oxide, photoresist, spin-coated organic carbon or spin-coated silicon glass.
3. The forming method according to claim 1, characterized in that, The forming method further includes: After the target mask hole is formed, the second mask layer and the blocking portion are removed.
4. The forming method according to claim 1, characterized in that, In the direction perpendicular to the substrate, the height of the blocking portion is 5nm~10nm.
5. The forming method according to claim 2, characterized in that, The step of etching the first mask layer using the second mask layer and the blocking portion as masks to form a target mask hole, wherein the etching rate of the blocking portion is less than the etching rate of the first mask layer, includes: The first mask layer is etched using a dry etching process, wherein the etching gas used in the dry etching process includes a mixture of carbon tetrafluoride, chlorine and boron chloride, or a mixture of oxygen and nitrogen.
6. The forming method according to any one of claims 1-5, characterized in that, The number of first mask holes and second mask holes are both multiple. The multiple first mask holes are distributed at intervals in the central region, and the second mask holes are distributed at intervals along the edge region and surround the central region.
7. A mask structure, characterized in that, The mask structure is formed by the method for forming a mask structure according to any one of claims 1-6.
8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a base and stacked film layers formed on the surface of the base; The mask structure of claim 7 is formed on the surface of the stacked film layers; The stacked film layers are etched using the mask structure as a mask to form capacitor holes within the stacked film layers.
9. The forming method according to claim 8, characterized in that, The forming method further includes: A lower electrode layer is formed within the capacitor hole.