Method of manufacturing a semiconductor structure
By fabricating an etching buffer layer in a polysilicon layer and forming etching walls that gradually approach the pores from top to bottom, the porosity problem of the polysilicon layer is solved, conductivity is improved, etching damage is reduced, and device performance is enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-06-15
- Publication Date
- 2026-06-16
AI Technical Summary
In existing technologies, the conductivity of doped polycrystalline silicon is affected by porosity, resulting in reduced conductivity. Furthermore, the porosity problem becomes more severe when the doping concentration increases, making further optimization difficult.
An etching buffer layer is prepared in a polycrystalline silicon layer. The etching buffer layer has a first groove that gradually shrinks from top to bottom, and the etching rate gradually decreases. The etching forms an etching wall that gradually approaches the pores from top to bottom. Combined with passivation treatment, the etching degree of the polycrystalline silicon layer is reduced, and the porosity problem is improved.
It effectively improves the conductivity of the polycrystalline silicon layer, reduces hole wall damage, and enhances the overall performance of the device.
Smart Images
Figure CN116646241B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Technology
[0002] Doped polysilicon is a common material in semiconductor devices; for example, it is often used to fabricate the conductive structure of the gate. For doped polysilicon, the higher the doping concentration, the better the conductivity. Therefore, increasing the doping concentration is an important way to optimize its conductivity.
[0003] Doped polycrystalline silicon is typically prepared by deposition. The morphology of the deposited silicon material is also affected by the doping concentration. Specifically, when the doping concentration is high, the surface roughness of the polycrystalline silicon gradually increases. This results in the presence of pores within the polycrystalline silicon prepared in pores, which reduces the conductivity of the polycrystalline silicon and limits further increases in the doping concentration. Summary of the Invention
[0004] Therefore, it is necessary to provide a method for preparing a semiconductor structure to address the problems mentioned in the background art, so as to improve the porosity problem existing in the preparation of polycrystalline silicon and thereby improve the conductivity of polycrystalline silicon.
[0005] According to some embodiments of this disclosure, a method for fabricating a semiconductor structure is provided, which includes the following steps:
[0006] Provide a substrate with contact holes;
[0007] A polycrystalline silicon layer is prepared in a contact hole, the polycrystalline silicon layer having pores;
[0008] An etching buffer layer is prepared on the polysilicon layer, and the etching buffer layer has a first groove located above the pore. The first groove gradually shrinks from top to bottom, and the etching rate of the etching buffer layer gradually decreases from top to bottom.
[0009] The etching buffer layer and the polysilicon layer are etched, and based on the first groove, an etching wall is formed on the surface of the polysilicon layer that gradually approaches the aperture from top to bottom, with the bottom end of the etching wall connected to the aperture wall; and,
[0010] A silicon-filled layer is prepared in the pores.
[0011] In some embodiments of this disclosure, the etching buffer layer includes multiple buffer sublayers, and the etching rate of the multiple buffer sublayers gradually decreases from top to bottom. In the etching buffer layer, the etching rate ratio of the buffer sublayer with the slowest etching rate to the buffer sublayer with the fastest etching rate is 1:10 to 1:100.
[0012] In some embodiments of this disclosure, the multiple buffer sublayers are made of the same material and are prepared by vapor deposition; in the step of preparing the etched buffer layer, the preparation temperature of the lower buffer sublayer is higher than that of the upper buffer sublayer.
[0013] In some embodiments of this disclosure, the total thickness of the etching buffer layer is 1 nm to 2 nm.
[0014] In some embodiments of this disclosure, the multiple buffer sublayers comprise the same substrate, and at least a portion of the buffer sublayers also contain doping elements; in the etched buffer layer, the doping concentration of the multiple buffer sublayers gradually decreases from top to bottom.
[0015] In some embodiments of this disclosure, the etching buffer layer comprises two buffer sublayers, wherein the lower buffer sublayer has a doping concentration of 1×10⁻⁶. 20 / cm 3 Below, the doping concentration of the uppermost buffer sublayer is greater than 1×10⁻⁶. 20 / cm 3 .
[0016] In some embodiments of this disclosure, preparing an etching buffer layer on the surface of the polysilicon layer includes controlling the total thickness of the etching buffer layer to be d;
[0017] After etching the etching buffer layer and the polysilicon layer, the top surface of the entire etching buffer layer and the polysilicon layer is higher than the top opening of the contact hole, and the height difference between the top surface of the entire etching buffer layer and the polysilicon layer and the top opening of the contact hole is a;
[0018] Where the ratio of d to a is greater than 1.5.
[0019] In some embodiments of this disclosure, the distance between the wall of the etched hole and the top edge of the contact hole is ≥0.8a.
[0020] In some embodiments of this disclosure, the ratio between a and the aperture of the contact hole is 0.3:1 to 0.8:1.
[0021] In some embodiments of this disclosure, during the step of etching the etching buffer layer and the polysilicon layer, the bottom end of the formed etching wall is controlled to be located at the widest point of the aperture, or the bottom end of the formed etching wall is controlled to be located above the aperture wall at the widest point of the aperture.
[0022] In some embodiments of this disclosure, an etchant including chlorine is used in the step of etching the etch buffer layer and the polysilicon layer.
[0023] In some embodiments of this disclosure, after etching the etching buffer layer and the polysilicon layer, and before filling the pores with doped silicon material, the method further includes: passivating the pores and the etched walls with a passivation gas including hydrogen.
[0024] In some embodiments of this disclosure, before etching the etching buffer layer, the method further includes: passivating the surface of the etching buffer layer with a passivating gas including hydrogen.
[0025] In some embodiments of this disclosure, fabricating a polysilicon layer in a contact hole includes: fabricating the polysilicon layer by deposition, controlling the deposition progress so that the surface of the polysilicon layer has a second groove located above the hole; and fabricating an etching buffer layer on the polysilicon layer includes: fabricating the etching buffer layer on the second groove by deposition, such that the etching buffer layer has a first groove located above the hole.
[0026] In some embodiments of this disclosure, the bottom of the first groove in the prepared etching buffer layer is pointed.
[0027] In some embodiments of this disclosure, the surface of the etched wall is flat and inclined relative to the top surface of the polysilicon layer.
[0028] In the above-described semiconductor structure fabrication method, the prepared polycrystalline silicon layer contains pores. Then, an etching buffer layer is prepared. The top surface of this etching buffer layer has a first groove that gradually narrows from top to bottom, and the etching rate of the etching buffer layer gradually decreases from top to bottom. During the etching process, the etchant accumulates more at the first groove. Combined with the etching buffer layer with its decreasing etching rate gradient, the opening of the first groove can gradually widen laterally during the etching process, ultimately forming an etching wall on the surface of the polycrystalline silicon layer that gradually approaches the pores from top to bottom. The opening at the top of this etching wall can be wider than the opening of the pores themselves, providing more space for the subsequent fabrication of the filling layer. This effectively improves the porosity problem in polycrystalline silicon layers in conventional techniques and enhances the conductivity of the polycrystalline silicon layer.
[0029] Furthermore, if the polysilicon layer is directly etched back, there will be problems such as excessively high etching rates and difficulty in controlling the etching progress, which may lead to damage to the contact hole walls. By forming etched walls in the polysilicon layer that gradually approach the holes from top to bottom in the manner disclosed in this disclosure, the degree of etching of the polysilicon layer can be minimized during the etching process, thereby reducing or avoiding damage to the contact hole walls during the etching process and improving device performance.
[0030] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0031] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.
[0032] Figure 1 A schematic diagram illustrating the steps of a semiconductor structure fabrication method;
[0033] Figure 2 This is a schematic diagram of a cross-sectional structure of a substrate provided in this disclosure;
[0034] Figure 3 In order to be in Figure 2 A schematic diagram of a polycrystalline silicon layer fabricated based on the structure shown.
[0035] Figure 4 In order to be in Figure 3 A schematic diagram of the structure for fabricating the first buffer sublayer based on the structure shown;
[0036] Figure 5 In order to be in Figure 4 A schematic diagram of the structure for fabricating the second buffer sublayer based on the structure shown;
[0037] Figure 6 In order to be in Figure 5 A schematic diagram of the structure after etching the etch buffer layer and polysilicon layer based on the structure shown;
[0038] Figure 7 In order to be in Figure 6 A schematic diagram of a silicon-filled layer fabricated based on the structure shown.
[0039] Figure 8 This is a schematic diagram of the temperature control procedure during the preparation process of Example 1;
[0040] Figure 9 This is a schematic diagram of the temperature control procedure during the preparation process of Example 2;
[0041] The reference numerals and their meanings in the attached figures are as follows:
[0042] 110, Substrate; 111, Contact hole; 120, Polysilicon layer; 121, Pore; 122, Second groove; 130, First buffer sublayer; 140, Second buffer sublayer; 141, First groove; 1201, Etched wall; 150, Silicon filling layer. Detailed Implementation
[0043] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0045] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.
[0046] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0048] One embodiment of this disclosure provides a method for fabricating a semiconductor structure, the method comprising the following steps:
[0049] A polycrystalline silicon layer is prepared in a contact hole, the polycrystalline silicon layer having pores;
[0050] An etching buffer layer is prepared on the polysilicon layer. The etching buffer layer is located on the pores, and the top surface of the etching buffer layer has a first groove located above the pores. The etching rate of the etching buffer layer gradually decreases from top to bottom.
[0051] Etching the etching buffer layer and the polysilicon layer, forming an etching hole in the polysilicon layer based on the first groove, which communicates with the pores and tapers from top to bottom toward the pores; and,
[0052] The pores are filled with doped silicon material.
[0053] In the above-described semiconductor structure fabrication method, the prepared polycrystalline silicon layer contains pores. Then, an etching buffer layer with a first groove is prepared. The top surface of the etching buffer layer has a first groove that gradually narrows from top to bottom, and the etching rate of the etching buffer layer gradually decreases from top to bottom. During the etching process, the etchant accumulates more at the first groove. Combined with the etching buffer layer with its decreasing etching rate gradient, the opening of the first groove can gradually widen laterally during the etching process, ultimately forming etching walls on the surface of the polycrystalline silicon layer that gradually approach the pores from top to bottom. The openings between the etching walls are significantly wider than the openings of the pores, providing more ample space for the subsequent fabrication of the filling layer. This effectively improves the porosity problem in polycrystalline silicon layers in conventional techniques and enhances the conductivity of the polycrystalline silicon layer.
[0054] Furthermore, if the polysilicon layer is directly etched back, there will be problems such as excessively high etching rates and difficulty in controlling the etching progress, which may lead to damage to the contact hole walls. By forming etched walls in the polysilicon layer that gradually approach the holes from top to bottom in the manner disclosed in this disclosure, the degree of etching of the polysilicon layer can be minimized during the etching process, thereby reducing or avoiding damage to the contact hole walls during the etching process and improving device performance.
[0055] The embodiments disclosed herein are described with reference to cross-sectional views that serve as schematic representations of preferred embodiments (and intermediate structures). Furthermore, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are also contemplated. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of this disclosure.
[0056] In one embodiment of this disclosure, reference is made to Figure 1 As shown, a schematic diagram of a method for fabricating a semiconductor structure is provided, including steps S1 to S5, as detailed below.
[0057] Step S1, a substrate 110 with contact holes 111 is provided.
[0058] Figure 2 A schematic cross-sectional view of a substrate 110 provided in this disclosure is shown. (Refer to...) Figure 2 As shown, the substrate 110 has a contact hole 111.
[0059] In some examples of this embodiment, substrate 110 may include an active region, in which contact holes 111 are formed. Substrate 110 may also have a plurality of shallow trench isolation structures (not shown in the figure) for separating the active region.
[0060] In some examples of this embodiment, the material of the substrate 110 may be a semiconductor material, such as one or more selected from silicon, germanium, silicon-germanium alloy and gallium nitride.
[0061] In some examples of this embodiment, the way to provide a substrate 110 with contact holes 111 may include: providing a substrate 110 and etching the substrate 110 to form contact holes 111 in the substrate 110.
[0062] In some examples of this embodiment, the contact hole 111 can be a hole with a high aspect ratio, for example, the aspect ratio of the contact hole 111 is 1:(0.5 to 3). For example, the aspect ratio of the contact hole 111 can be 1:0.5, 1:1, 1:2, or 1:3. The aspect ratio of the contact hole 111 can also be within the range of the above aspect ratios. Controlling the aspect ratio of the contact hole 111 to be high helps to improve the integration of the device, but it can also lead to problems such as difficulty in fully filling the hole and the easy occurrence of pores 121 in the filling material.
[0063] In some examples of this embodiment, the depth of the contact hole 111 is 10 nm to 50 nm. For example, the depth of the contact hole 111 is 10 nm, 15 nm, 20 nm, 30 nm, or 50 nm. The depth of the contact hole 111 can also be within the range of the above-mentioned depths.
[0064] In some examples of this embodiment, the aperture of the contact hole 111 is 5 nm to 30 nm. For example, the aperture of the contact hole 111 is 5 nm, 10 nm, 20 nm, or 30 nm. The aperture of the contact hole 111 can also be within the range of the above apertures.
[0065] Step S2: Prepare a polycrystalline silicon layer 120 in the contact hole 111.
[0066] Figure 3 It shows in Figure 2 A schematic diagram of the structure of polycrystalline silicon layer 120 fabricated based on the structure shown. (Refer to...) Figure 3 As shown, the prepared polysilicon layer 120 has pores 121. In this embodiment, the pores 121 can be closed pores 121, existing inside the polysilicon layer 120. In other embodiments, the pores 121 can also be open pores 121, having openings exposed from the surface of the polysilicon layer 120.
[0067] It is understandable that the pores 121 are generally caused by the slower growth rate of silicon material in the middle part on both sides of the contact hole 111 during the attachment and growth of silicon material on the hole wall, resulting in insufficient timely filling of the hole. The pores 121 in the polysilicon layer 120 are usually generated as device size shrinks, and these pores 121 severely affect the conductivity of the polysilicon layer 120. Since the polysilicon layer 120 is typically used to connect adjacent components, these pores 121 further affect the overall performance of the device.
[0068] In some examples of this embodiment, the method for preparing the polycrystalline silicon layer 120 in the contact hole 111 can be selected from chemical vapor deposition. For example, preparing the polycrystalline silicon layer 120 in the contact hole 111 includes: placing the substrate 110 in a deposition chamber and depositing silicon material in the contact hole 111 using a raw material including a silicon source. During the deposition of the silicon material, the deposition temperature can be controlled to be above 400°C to improve the lattice structure of the deposited silicon material.
[0069] In some examples of this embodiment, a step of preparing a silicon seed layer in the contact hole 111 may be included before preparing the polysilicon layer 120. The silicon seed layer is used to promote the growth of the polysilicon layer 120.
[0070] In some examples of this embodiment, the prepared polycrystalline silicon layer 120 also contains dopant elements to give the polycrystalline silicon layer 120 higher conductivity. During the deposition of silicon material, the raw materials used for deposition may also include a dopant source to form a polycrystalline silicon layer 120 containing dopant elements. The dopant source can be selected based on the dopant element, and the dopant source should contain a dopant element. For example, in this embodiment, if the dopant element includes phosphorus, then the dopant source may include phosphine.
[0071] Furthermore, the step of preparing the polycrystalline silicon layer 120 includes: controlling the doping concentration in the polycrystalline silicon layer 120 to be greater than 1 × 10⁻⁶. 20 / cm 3 In this process, a higher doping concentration in the polysilicon layer 120 is beneficial for improving its conductivity. However, when the doping concentration is too high, the porosity 121 problem in the polysilicon layer 120 becomes more severe and more difficult to solve. The semiconductor structure fabrication method disclosed in this invention can effectively solve the porosity 121 problem in the polysilicon layer 120 with excessively high doping concentration.
[0072] In some examples of this embodiment, during the step of fabricating a polysilicon layer 120 in the contact hole 111, the polysilicon layer 120 may also extend to cover the surface of the substrate 110 in order to protect the underlying substrate 110 in subsequent etching processes.
[0073] Reference Figure 3As shown, in some examples of this embodiment, in the step of preparing the polysilicon layer 120, the polysilicon layer 120 is prepared by deposition, and the deposition progress is controlled so that the surface of the polysilicon layer 120 has a second groove 122 located above the pore 121. The second groove 122 is used to allow the first groove 141 to be directly formed on the surface of the etching buffer layer during the subsequent preparation of the etching buffer layer.
[0074] Controlling the deposition progress refers to controlling the timing of stopping the deposition of the polysilicon layer 120 during its fabrication. In this embodiment, the deposition can be stopped after the pores 121 in the polysilicon layer 120 are sealed and before the grooves above the pores 121 are filled. It is understood that the deposition progress can be controlled by adjusting the deposition rate and deposition time.
[0075] It is understandable that during the silicon deposition process, the silicon material on the sidewalls closer to the top and bottom of the contact hole 111 is deposited at a faster rate. This causes the silicon material at the top of the contact hole 111 to contact first and close the hole 121. As soon as the hole 121 closes, a second groove 122 naturally forms on the surface of the polysilicon layer 120 above the hole 121. By stopping the deposition process at this point, the surface of the polysilicon layer 120 will have the second groove 122 located above the hole 121.
[0076] In some examples of this embodiment, the groove depth of the second groove 122 on the surface of the polysilicon layer 120 is 0.5 nm to 2 nm.
[0077] In some examples of this embodiment, the distance between the bottom of the second groove 122 and the top of the aperture 121 is 0.5 nm to 5 nm.
[0078] Reference Figure 3 As shown, in some examples of this embodiment, the second groove 122 on the surface of the polysilicon layer 120 gradually shrinks from top to bottom; for example, the radial width of the second groove 122 gradually decreases from top to bottom.
[0079] Obtaining the second groove 122 by controlling the deposition progress is a relatively simple fabrication method. In other embodiments, the second groove 122 can also be obtained by methods such as etching, but this would increase the number of fabrication steps.
[0080] Step S3: Prepare an etching buffer layer on the polysilicon layer 120.
[0081] The etching buffer layer can cover the entire polysilicon layer 120, and has a first groove 141 located above the aperture 121. The first groove 141 gradually shrinks from top to bottom, and the etching rate of the etching buffer layer gradually decreases from top to bottom.
[0082] In some examples of this embodiment, the etching buffer layer includes multiple buffer sublayers, with the etching rate of the multiple buffer sublayers gradually decreasing from top to bottom. In the etching buffer layer, the etching rate ratio of the buffer sublayer with the slowest etching rate to the buffer sublayer with the fastest etching rate is 1:10 to 1:100.
[0083] In some examples of this embodiment, the etching buffer layer may include two buffer sublayers, namely a first buffer sublayer 130 and a second buffer sublayer 140.
[0084] Figure 4 It shows in Figure 3 A schematic diagram of the structure of the first buffer sublayer 130 prepared based on the structure shown. Figure 5 It shows in Figure 4 A schematic diagram of the structure of the second buffer sublayer 140 fabricated based on the structure shown. The etching rate of the first buffer sublayer 130 is lower than the etching rate of the second buffer sublayer 140. The etching rate refers to the etching rate of the first buffer sublayer 130 and the second buffer sublayer 140 under the same etching conditions.
[0085] In some examples of this embodiment, the first buffer sublayer 130 and the second buffer sublayer 140 can be formed by deposition. (Refer to...) Figure 4 As shown, since the surface of the polysilicon layer 120 has a second groove 122, the surfaces of the deposited first buffer sublayer 130 and the second buffer sublayer 140 will both form grooves in the same shape, resulting in the surface of the final etched buffer layer having a first groove 141.
[0086] It is understood that, for the sake of clarity in describing the difference between the first buffer sublayer 130 and the second buffer sublayer 140, this document states that the first buffer sublayer 130 and the second buffer sublayer 140 have different etching rates. However, the etching rate is usually related to the etching process, so this etching rate actually refers to the difference in etching rate between the first buffer sublayer 130 and the second buffer sublayer 140 under the same etching process.
[0087] In some examples of this embodiment, the first and second etched sublayers are made of the same material so that they can be prepared using the same raw materials. It is understood that during the preparation process, different etching rates can be obtained for the first and second etched sublayers by controlling conditions such as temperature or raw material dosage.
[0088] In some examples of this embodiment, the first etch sublayer and the second etch sublayer are made of the same material and are prepared by vapor deposition. In the step of preparing the etch buffer layer, the preparation temperature of the first etch sublayer is higher than that of the second etch sublayer. Controlling the preparation temperature of the first etch sublayer to be higher than that of the second etch sublayer allows the first etch sublayer to be denser than the second etch sublayer, thereby obtaining a first etch sublayer with a slower etching rate and a second etch sublayer with a faster etching rate.
[0089] It is understandable that in other examples, more etched sublayers can be prepared, as long as the preparation temperature of the lower buffer sublayer is higher than that of the upper buffer sublayer.
[0090] Furthermore, the etching rate ratio of the first etched sublayer to the second etched sublayer is 1:10 to 1:100.
[0091] Furthermore, the total thickness of the etching buffer layer can be controlled to be 1nm to 2nm, so as to form a more effective widening of the first groove 141 and control the etching progress in subsequent etching processes.
[0092] Furthermore, the materials of the first and second etched sublayers may include silicon. For example, both the first and second etched sublayers may be undoped silicon, i.e., intrinsic silicon. The raw materials used to prepare the first and second etched sublayers may include hydrides, such as silane. The materials of the first and second etched sublayers may also be doped silicon. In some examples of this embodiment, the material of the first etched sublayer may be the same as the material of the polysilicon layer 120. In this case, the first etched sublayer and the polysilicon layer 120 can be prepared in the same process, which simplifies the fabrication process.
[0093] In some examples of this embodiment, the deposition temperature of the first etched sublayer can be controlled to be 420°C to 500°C. The deposition temperature of the second etched sublayer can be controlled to be 350°C to 400°C. It is understood that during the preparation of the first buffer sublayer 130 and the second buffer sublayer 140, other deposition conditions except for the deposition temperature can be kept constant to continuously prepare the first buffer sublayer 130 and the second buffer sublayer 140, simplifying the preparation process.
[0094] In the etching buffer layer, the thicknesses of the first etching sublayer and the second etching sublayer can be matched according to actual needs. In this embodiment, the thickness ratio of the first etching sublayer to the second etching sublayer can be 1:(0.5~2).
[0095] It is understandable that in this example, by controlling the deposition temperature to control the density of the first etched sublayer and the second etched sublayer, a first etched sublayer and a second etched sublayer with the same material type but different etching rates are obtained.
[0096] In other examples of this embodiment, the first etched sublayer and the second etched sublayer comprise the same substrate, and the first etched sublayer and the second etched sublayer have different doping concentrations. Specifically, the doping concentration of the second etched sublayer is higher than that of the first etched sublayer. It can be understood that the doping concentration of the first etched sublayer can be 0, that is, the first etched sublayer does not contain any doping elements.
[0097] Furthermore, the etching rate ratio of the first etched sublayer to the second etched sublayer is 1:10 to 1:100.
[0098] Further, the substrate of the multilayer buffer sublayer is selected from silicon. The fabrication of the etching buffer layer on the surface of the polysilicon layer 120 includes: depositing silicon on the surface of the polysilicon layer 120 using a reactive material containing a silicon source. In the step of fabricating the etching buffer layer, the amount of dopant source used when fabricating the first etching sublayer is lower than the amount of dopant source used when fabricating the second etching sublayer, so that the doping concentration of the first etching sublayer is lower than that of the second etching sublayer. In this embodiment, no dopant source is used when fabricating the first etching sublayer, but a dopant source is used when fabricating the second etching sublayer.
[0099] It is understandable that in other examples, more etched sublayers can also be prepared by simply increasing the amount of dopant source in the reaction materials from bottom to top in the step of preparing the etch buffer layer.
[0100] Furthermore, the doping concentration of the first buffer sublayer 130 is ≤10. 20 / cm 3 .
[0101] Furthermore, the doping concentration of the second buffer sublayer 140 is >1×10⁻⁶. 20 / cm 3 For example, the doping concentration of the second buffer sublayer 140 is 1 × 10⁻⁶. 20 / cm 3 ~1×10 22 / cm 3 .
[0102] It is understandable that in this example, by controlling the amount of doping source, the doping concentration of the first etched sublayer and the second etched sublayer is controlled, thereby obtaining the first etched sublayer and the second etched sublayer with the same material type but different etching rates.
[0103] Step S4: Etch the etch buffer layer and the polysilicon layer 120.
[0104] During the etching process, based on the first groove 141, an etching wall 1201 is formed on the surface of the polysilicon layer 120, which gradually approaches the hole 121 from top to bottom, and the bottom end of the etching wall 1201 is connected to the hole wall of the hole 121.
[0105] In some examples of this embodiment, the same etchant is used when etching the etch buffer layer and the polysilicon layer 120. Further, the etchant may include chlorine gas.
[0106] In some examples of this embodiment, before etching the etching buffer layer, the surface of the etching buffer layer is passivated using a passivating gas including hydrogen. Passivating the surface of the etching buffer layer with a passivating gas can improve the crystal structure of the surface of the etching buffer layer, making its etching progress more controllable.
[0107] Figure 6 It shows in Figure 5 This is a schematic diagram showing the structure after etching the etch buffer layer and polysilicon layer 120 based on the structure shown. (Combined with...) Figure 5 and Figure 6 As shown, during the etching process, the etchant accumulates more at the wall of the first groove 141, thus the wall of the first groove 141 is etched more quickly. Combined with the etching buffer layer that reduces the etching rate gradient, the first groove 141 can be gradually widened to the side during the etching process. Therefore, when etching to the polysilicon layer 120, an etched wall 1201 can be formed in the polysilicon layer 120 above the aperture 121, gradually approaching the aperture 121 from top to bottom. The bottom end of the etched wall 1201 is directly connected to the aperture wall of the aperture 121.
[0108] Furthermore, the etching buffer layer on the polysilicon layer 120 also serves to buffer the etching progress. By buffering the etching process, the etching buffer layer can minimize the etching degree of the polysilicon layer 120, thereby reducing or avoiding damage to the hole walls of the contact holes 111 during the etching process and improving device performance. If the etching buffer layer is not provided and the polysilicon layer 120 is directly etched back, the etching rate of the polysilicon layer 120 with a high doping concentration will be too high, making it difficult to control the etching process. Consequently, the polysilicon layer 120 may be etched through in some areas, and the substrate 110 will be etched and damaged.
[0109] In some examples of this embodiment, the surface of the etched wall 1201 is flat and inclined relative to the top surface of the polysilicon layer 120. Controlling the flatness of the surface of the etched wall 1201 allows for a relatively thicker gap between the surface of the polysilicon layer 120 and the top of the contact hole 111, avoiding etching damage to the surface of the substrate 110. On the other hand, it also provides more space for the subsequent fabrication of the silicon filling layer 150.
[0110] Reference Figure 6 As shown, in some examples of this embodiment, the top surface of the etching buffer layer and the polysilicon layer 120 as a whole is higher than the top opening of the contact hole 111, and the height difference between the top surface of the etching buffer layer and the polysilicon layer 120 as a whole and the top opening of the contact hole 111 is 'a', with the ratio between 'a' and the aperture of the contact hole 111 being 0.3:1 to 0.8:1. By controlling the ratio between 'a' and the aperture of the contact hole 111, the substrate 110 located below the polysilicon layer 120 can be protected while widening the opening on the surface of the polysilicon layer 120 as much as possible.
[0111] Reference Figure 6 As shown, in some examples of this embodiment, the etching buffer layer is completely removed during the etching process, and the height difference between the top surface of the remaining polysilicon layer 120 and the top opening of the contact hole 111 is a.
[0112] Reference Figure 6 As shown, in some examples of this embodiment, during the etching process, the top surface height of the polysilicon layer 120 is kept unchanged compared to before etching. It can be understood that due to the faster etching rate at the first groove 141 and the hole enlargement process during etching, it is possible to form etched walls 1201 in the polysilicon layer 120 while keeping the top surface height of the polysilicon layer 120 unchanged.
[0113] Combination Figure 5 and Figure 6 As shown, in some examples of this embodiment, corresponding to the different doping concentrations of different etch sublayers in the etch buffer layer, when preparing the etch buffer layer on the surface of the polysilicon layer 120, the total thickness of the etch buffer layer can be controlled to be d. The ratio of d to a can be controlled to be >1.5, so that the etching progress of the etch buffer layer is easier to control, and a better morphology etch wall 1201 is formed on the surface of the polysilicon layer 120.
[0114] Reference Figure 6 As shown, in some examples of this embodiment, the distance between the formed etched wall 1201 and the top edge of the contact hole 111 is b, which can be controlled to be ≥0.8a, so as to avoid damage to the top edge of the contact hole 111 during the etching process as much as possible.
[0115] In some examples of this embodiment, during the etching steps of the etch buffer layer and the polysilicon layer 120, the bottom end of the formed etch wall 1201 is controlled to be located at the widest point of the aperture 121, or the bottom end of the formed etch wall 1201 is controlled to be located above the widest point of the aperture 121. By controlling the bottom end of the etch wall 1201 to be located at or above the widest point of the aperture 121, the opening of the aperture 121 can be widened while minimizing the thickness loss of the polysilicon layer 120, thus facilitating the subsequent fabrication of the silicon filling layer 150.
[0116] In some examples of this embodiment, after etching the etch buffer layer and the polysilicon layer 120, the process further includes passivating the pores 121 and the etched walls 1201 with a passivating gas including hydrogen. Passivating the etched walls 1201 can repair the etching damage suffered by the pores 121 and the etched walls 1201 during the etching process and improve their surface roughness.
[0117] Step S5: Prepare a silicon-filled layer 150 in the pores 121.
[0118] Figure 7 It shows in Figure 6 A schematic diagram of the silicon filling layer 150 fabricated based on the structure shown. (Refer to...) Figure 7 As shown, the silicon filling layer 150 is prepared in the pores 121 and is in contact with the polycrystalline silicon layer 120, which can improve the conductivity of the original polycrystalline silicon layer 120.
[0119] In some examples of this embodiment, the silicon filling layer 150 may further extend and fill the spaces between the etched walls 1201. Further, the silicon filling layer 150 may also extend and cover the top surface of the polysilicon layer 120. It is understood that the material of the silicon filling layer 150 may be the same as that of the polysilicon layer 120. The silicon filling layer 150 and the polysilicon layer 120 can collectively form a conductive structure with good conductivity.
[0120] In some examples of this embodiment, the method for preparing the silicon-filled layer 150 can be chemical vapor deposition. For example, preparing the polycrystalline silicon layer 120 in the contact hole 111 includes placing the substrate 110 in a deposition chamber and depositing silicon material in the contact hole 111 using a raw material including a silicon source. During the deposition of the silicon material, the deposition temperature can be controlled to be above 400°C to improve the lattice structure of the deposited silicon material.
[0121] In some examples of this embodiment, the silicon filling layer 150 also contains doping elements to give it high conductivity. Furthermore, the doping concentration of the silicon filling layer 150 can be controlled to be ≥1×10⁻⁶. 20 / cm 3 .
[0122] It is understood that a semiconductor structure can be prepared through steps S1 to S5. In this semiconductor structure, the polycrystalline silicon layer 120 and the silicon filling layer 150 can serve as contact structures between adjacent components, such as bit line contacts, to improve the conductivity between adjacent components.
[0123] Furthermore, this disclosure also provides a memory comprising a semiconductor structure prepared by the above embodiments.
[0124] To facilitate understanding of the specific process of the semiconductor structure fabrication method in this disclosure, the following embodiments are also provided.
[0125] Figure 8 This is a schematic diagram of the heating process during the preparation of Example 1. Figure 8 In the graph, the vertical axis T represents temperature, and the horizontal axis t represents time. (Refer to...) Figure 8 As shown, the method for fabricating this semiconductor structure includes a sequential temperature control procedure C. 11 ~C 17 .
[0126] In C 11 During the process, the substrate is placed in the processing chamber, and the temperature of the processing chamber is controlled at T. 10 The substrate is boron-doped to obtain a P-type doped region within it. Wherein T 10 It can be 380℃.
[0127] In C 11 After the process, maintain the temperature at T. 10 Continue with C 12 Process. In C 12 During the process, a silicon seed layer can be deposited in the contact holes of the substrate using chemical vapor deposition.
[0128] In C 12 After the process, the temperature will be changed from T. 10 Heat up to T 11 Then proceed with C. 13 During this heating process, hydrogen gas can be introduced to repair defects in the substrate and silicon seed layer. At C... 13 During the process, a polycrystalline silicon layer can be grown on a silicon seed layer using chemical vapor deposition. Furthermore, during deposition, a phosphorus source (such as phosphine) can be incorporated into the reaction gas to obtain an N-type polycrystalline silicon layer. Further, in C... 13 During the process, a first buffer sublayer can also be directly prepared on the polycrystalline silicon layer. This first buffer sublayer is also an N-type polycrystalline silicon layer. Wherein T... 11 It can be 470℃. It is understood that in Example 1, the polysilicon layer and the first buffer sublayer can be in the same process (i.e., C...). 13 The polysilicon layer and the first buffer sublayer can be made of the same material.
[0129] In C 13 After the process, the temperature will be changed from T. 11 Cool down to T 10 Then proceed with C. 14During the cooling process, a protective gas, such as nitrogen, can be continuously introduced into the processing chamber. At C... 14 During the process, the reaction gas can be kept the same as the reaction gas used when depositing the first buffer sublayer by chemical vapor deposition, and a second buffer sublayer can be deposited on the first buffer sublayer to form an etching buffer layer, which can be controlled in Example 1.
[0130] In C 14 After the process, the temperature will be changed from T. 10 Cool down to T 12 Then proceed with C. 15 During this cooling process, hydrogen gas can be introduced to repair defects in the etching buffer layer. At C... 15 During the process, chlorine gas can be used as an etchant to perform dry etching on the etching buffer layer. Because the preparation temperature of the second buffer sublayer is lower than that of the first buffer sublayer, the etching rate of the second buffer sublayer is faster than that of the first buffer sublayer. This allows for the formation of a structure similar to... Figure 6 The inclined etched wall in the structure shown.
[0131] In C 15 After the process, the temperature will be changed from T. 12 Heat up to T 11 Then proceed with C. 16 During this heating process, hydrogen gas can be introduced to repair defects in the etching buffer layer. At C... 16 During the process, a silicon-filled layer can be prepared in the pores using chemical vapor deposition. During the deposition process, a phosphorus source can be incorporated into the reaction gas to obtain an N-type silicon-filled layer.
[0132] In C 16 After the process, the temperature will be changed from T. 11 Cool down to T 10 Then you can proceed with C. 17 During this cooling process, a protective gas can be introduced. At C... 17 During the process, some post-processing techniques can be performed, such as removing excess boron atoms from the substrate.
[0133] Figure 9 This is a schematic diagram of the temperature control procedure during the preparation process of Example 2. Figure 9 In the graph, the vertical axis T represents temperature, and the horizontal axis t represents time. (Refer to...) Figure 9 As shown, the method for fabricating this semiconductor structure includes a sequential temperature control procedure C. 21 ~C 28 .
[0134] In C 21 During the process, the substrate is placed in the processing chamber, and the temperature of the processing chamber is controlled at T.20 The substrate is boron-doped to obtain a P-type doped region within it. Wherein T 20 It can be 380℃.
[0135] In C 21 After the process, maintain the temperature at T. 20 Continue with C 22 Process. In C 22 During the process, a silicon seed layer can be deposited in the contact holes of the substrate using chemical vapor deposition.
[0136] In C 22 After the process, the temperature will be changed from T. 20 Heat up to T 21 Then proceed with C. 23 During this heating process, hydrogen gas can be introduced to repair defects in the substrate and silicon seed layer. At C... 23 During the process, a polycrystalline silicon layer can be grown on a silicon seed layer using chemical vapor deposition. Furthermore, during deposition, a phosphorus source (e.g., phosphine) can be incorporated into the reaction gas to obtain an N-type polycrystalline silicon layer with a phosphorus doping concentration greater than 1 × 10⁻⁶. 20 / cm 3 .
[0137] In C 23 After the process, maintain the temperature at T. 21 Continue with C 24 Process. In C 24 During the process, a first buffer sublayer can be deposited on the polycrystalline silicon layer using chemical vapor deposition. The phosphorus source content in the reaction gas during the preparation of the first buffer sublayer is lower than that during the preparation of the polycrystalline silicon layer. The material of the first buffer sublayer is polycrystalline silicon, with a phosphorus doping concentration of 1×10⁻⁶. 20 / cm 3 the following.
[0138] In C 24 After the process, maintain the temperature at T. 21 Continue with C 25 Process. In C 25 During the process, a second buffer sublayer can be deposited on the first buffer sublayer using chemical vapor deposition to form an etching buffer layer. The phosphorus source content in the reaction gas during the preparation of the second buffer sublayer is higher than that during the preparation of the first buffer sublayer. The material of the second buffer sublayer is polycrystalline silicon, in which the phosphorus atom doping concentration is greater than 1 × 10⁻⁶. 20 / cm 3 .
[0139] In C 25 After the process, the temperature will be changed from T.21 Cool down to T 22 Then proceed with C. 26 During this cooling process, a protective gas can be introduced. At C... 26 During the process, chlorine gas can be used as an etchant to perform dry etching on the etching buffer layer. Because the doping concentration of the second buffer sublayer is higher than that of the first buffer sublayer, the etching rate of the second buffer sublayer is faster than that of the first buffer sublayer. This can create an effect similar to... Figure 6 The inclined etched wall in the structure shown.
[0140] In C 26 After the process, the temperature will be changed from T. 22 Heat up to T 21 Then proceed with C. 27 During this heating process, hydrogen gas can be introduced to repair defects in the etching buffer layer. At C... 27 During the process, a silicon-filled layer can be prepared in the pores using chemical vapor deposition. During the deposition process, a phosphorus source can be incorporated into the reaction gas to obtain an N-type silicon-filled layer.
[0141] In C 27 After the process, the temperature will be changed from T. 21 Cool down to T 20 Then you can proceed with C. 28 During this cooling process, a protective gas can be introduced. At C... 28 During the process, some post-processing techniques can be performed, such as removing excess boron atoms from the substrate.
[0142] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.
[0143] It should be understood that, unless otherwise expressly stated herein, there is no strict order in which the steps are performed, and these steps may be performed in other orders. Moreover, at least some of the steps may include multiple sub-steps or multiple stages, which are not necessarily completed at the same time, but may be performed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.
[0144] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0145] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide a substrate with contact holes; A polycrystalline silicon layer is prepared in a contact hole, the polycrystalline silicon layer having pores; An etching buffer layer is prepared on the polysilicon layer, and the etching buffer layer has a first groove located above the pore. The first groove gradually shrinks from top to bottom, and the etching rate of the etching buffer layer gradually decreases from top to bottom. The etching buffer layer and the polysilicon layer are etched, and based on the first groove, an etching wall is formed on the surface of the polysilicon layer that gradually approaches the aperture from top to bottom, with the bottom end of the etching wall connected to the aperture wall; and, A silicon-filled layer is prepared in the pores; The etching buffer layer includes multiple buffer sub-layers, and the etching rate of the multiple buffer sub-layers gradually decreases from top to bottom. In the etching buffer layer, the etching rate ratio of the buffer sub-layer with the slowest etching rate to the buffer sub-layer with the fastest etching rate is 1:10 to 1:
100.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The multiple buffer sublayers are made of the same material and are prepared by vapor deposition; in the step of preparing the etched buffer layer, the preparation temperature of the lower buffer sublayer is higher than that of the upper buffer sublayer.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The total thickness of the etching buffer layer is 1 nm to 2 nm.
4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The multiple buffer sublayers comprise the same substrate, and at least a portion of the buffer sublayers also contain doping elements; in the etched buffer layer, the doping concentration of the multiple buffer sublayers gradually decreases from top to bottom.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The etching buffer layer comprises two buffer sub-layers, wherein the lower buffer sub-layer has a doping concentration of 1×10⁻⁶. 20 / cm 3 Below, the doping concentration of the uppermost buffer sublayer is greater than 1×10⁻⁶. 20 / cm 3 .
6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that, Preparing an etching buffer layer on the surface of the polysilicon layer includes: controlling the total thickness of the etching buffer layer to be d; After etching the etching buffer layer and the polysilicon layer, the top surface of the entire etching buffer layer and the polysilicon layer is higher than the top opening of the contact hole, and the height difference between the top surface of the entire etching buffer layer and the polysilicon layer and the top opening of the contact hole is a; Where the ratio of d to a is greater than 1.5; and / or, The distance between the etched wall and the top edge of the contact hole is ≥0.8a; and / or, The ratio between a and the diameter of the contact hole is 0.3:1 to 0.8:
1.
7. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that, In the step of etching the etching buffer layer and the polysilicon layer, the bottom end of the formed etching wall is controlled to be located at the widest point of the aperture, or the bottom end of the formed etching wall is controlled to be located above the aperture wall at the widest point of the aperture.
8. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that, In the step of etching the etching buffer layer and the polysilicon layer, an etchant including chlorine gas is used for etching; And / or, After etching the etching buffer layer and the polysilicon layer, and before filling the pores with doped silicon material, the method further includes: passivating the pores and the etched walls with a passivation gas comprising hydrogen; and / or, Before etching the etching buffer layer, the method further includes: passivating the surface of the etching buffer layer with a passivating gas including hydrogen.
9. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that, Fabricating a polysilicon layer in a contact hole includes: fabricating the polysilicon layer by deposition, controlling the deposition progress such that the surface of the polysilicon layer has a second groove located above the hole; and fabricating an etching buffer layer on the polysilicon layer includes: fabricating the etching buffer layer on the second groove by deposition, such that the etching buffer layer has a first groove located above the hole; and / or, In the prepared etching buffer layer, the bottom of the first groove is pointed; and / or, The surface of the etched wall is flat and inclined relative to the top surface of the polycrystalline silicon layer.