A semiconductor packaging method and a semiconductor packaging structure

Abstract

A semiconductor packaging method and a semiconductor packaging structure, the semiconductor packaging method comprising: forming an initial package, the initial package comprising: a redistribution structure; a chip located at one side of the redistribution structure; a seed layer located at a surface of the redistribution structure away from the chip; a plastic encapsulation layer located at a side of the redistribution structure away from the seed layer and encapsulating the chip; applying a first initial photoresist layer on a side of the seed layer away from the redistribution structure; removing an edge region of at least a part of a thickness of the first initial photoresist layer, so that the first initial photoresist layer forms a first photoresist layer, a peripheral side of the first photoresist layer having a first groove; then, performing an initial solidification treatment on the first photoresist layer; then, applying a second photoresist layer on a surface of the first photoresist layer away from the seed layer and in the first groove. The semiconductor packaging method improves the yield of the formed semiconductor packaging structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor packaging method and a semiconductor packaging structure. Background Technology

[0002] A semiconductor packaging method, comprising: reference Figure 1 An initial package is formed, comprising: a redistribution structure 2', which includes a redistribution conductive layer 22' and a dielectric layer 21'; a chip 4' located on one side of the redistribution structure 2', with a conductive connector between the chip 4' and the redistribution structure 2', the conductive connector including a conductive post 11', a solder layer 12', and an interconnect pad 13'; an underfill layer 7' encapsulating the conductive connector between the chip 4' and the redistribution structure 2'; a seed layer 5' located on the surface of the redistribution structure 2' opposite to the chip 4'; and a molding compound 3' located on the side of the redistribution structure 2' opposite to the seed layer 5' and encapsulating the chip 4'; Reference Figure 1 A patterned photoresist layer 6' is formed on the surface of the seed layer 5' facing away from the redistribution structure 2', and the patterned photoresist layer 6' has a patterned opening 61'; Reference Figure 2 Electrical terminals 62' are formed in the patterned opening 61', and then the patterned photoresist layer 6' is removed; after removing the patterned photoresist layer 6', the seed layer 5' not covered by the electrical terminals 62' is removed.

[0003] The yield of semiconductor packaging structures formed by the above semiconductor packaging methods is reduced. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the low yield of semiconductor packaging structures in the prior art, thereby providing a semiconductor packaging method and a semiconductor packaging structure.

[0005] This invention provides a semiconductor packaging method, comprising: forming an initial package, the initial package comprising: a redistribution structure; a chip located on one side of the redistribution structure; a seed layer located on a side surface of the redistribution structure opposite to the chip; a molding compound layer located on the side of the redistribution structure opposite to the seed layer and encapsulating the chip; coating a first initial photoresist layer on the side of the seed layer opposite to the redistribution structure; removing at least a portion of the thickness of the edge region of the first initial photoresist layer, such that the first initial photoresist layer forms a first photoresist layer, the peripheral side of the first photoresist layer having a first groove; after forming the first groove, performing an initial curing treatment on the first photoresist layer; after the initial curing treatment of the first photoresist layer, coating a second photoresist layer on the side surface of the first photoresist layer opposite to the seed layer and in the first groove.

[0006] Optionally, the step of removing at least a portion of the thickness of the edge region of the first initial photoresist layer includes: performing a first edge washing process on the first initial photoresist layer; and after performing the first edge washing process, performing a second edge washing process on the first initial photoresist layer to form a first photoresist layer, wherein the edge washing width of the second edge washing process is greater than the edge washing width of the first edge washing process, and the edge washing depth of the second edge washing process is greater than the edge washing depth of the first edge washing process.

[0007] Optionally, the edge washing width of the first edge washing process is 0.2mm-2mm; the edge washing width of the second edge washing process is 4mm-7mm.

[0008] Optionally, in the step of coating the first initial photoresist layer on the side of the seed layer away from the redistribution structure, the edge region of the first initial photoresist layer has a first protrusion; the first initial photoresist layer is subjected to a first edge washing process to remove the first protrusion.

[0009] Optionally, a seed layer is exposed at the bottom of the first groove before the second photoresist layer is applied.

[0010] Optionally, it may also include: performing a third edge washing process on the second photoresist layer, wherein the edge washing width of the third edge washing process is smaller than the width of the first groove.

[0011] Optionally, in the step of coating the second photoresist layer on the side of the first photoresist layer opposite to the seed layer and in the first groove, the edge region of the second photoresist layer has a second protrusion; the third edge washing process is used to remove the second protrusion.

[0012] Optionally, it also includes: after performing the third edge washing process, curing the second photoresist layer and the first photoresist layer.

[0013] Optionally, the initial curing treatment is a soft baking treatment.

[0014] Optionally, it further includes: pre-wetting the surface of the seed layer on the side facing away from the redistribution structure before coating the first initial photoresist layer on the side of the seed layer facing away from the redistribution structure.

[0015] Optionally, the molding compound does not cover the sidewall of the redistribution structure; or, the molding compound further encapsulates the sidewall of the redistribution structure, with the molding compound on the sidewall of the redistribution structure protruding from the seed layer on the side surface opposite to the chip; in the step of coating the first initial photoresist layer on the side of the seed layer opposite to the redistribution structure, the first initial photoresist layer further covers the molding compound on the sidewall of the redistribution structure; the height of the first initial photoresist layer from the side surface opposite to the seed layer to the seed layer is greater than the height of the molding compound on the sidewall of the redistribution structure protruding from the seed layer; the first groove is located between the first photoresist layer and the molding compound on the sidewall of the redistribution structure.

[0016] Optionally, it further includes: patterning the first photoresist layer and the second photoresist layer to form a plurality of patterned openings penetrating the first photoresist layer and the second photoresist layer, with some of the patterned openings penetrating the second photoresist layer in the first groove; and forming electrical terminals in the patterned openings.

[0017] The present invention also provides a semiconductor packaging structure, comprising: a redistribution structure; a chip located on one side of the redistribution structure; a seed layer located on the side surface of the redistribution structure opposite to the chip; a molding compound layer located on the side of the redistribution structure opposite to the seed layer and encapsulating the chip; a first photoresist layer located on the side of the seed layer opposite to the redistribution structure, the first photoresist layer having a first groove on its periphery; and a second photoresist layer located on the side surface of the first photoresist layer opposite to the seed layer and in the first groove.

[0018] Optionally, the bottom of the first groove extends to the surface of the seed layer.

[0019] Optionally, the width of the first groove is 4mm to 7mm.

[0020] Optionally, the molding compound does not cover the sidewall of the redistribution structure; the molding compound also encapsulates the sidewall of the redistribution structure, with the molding compound on the sidewall of the redistribution structure protruding from the seed layer on the side surface away from the chip; the first groove is located between the first photoresist layer and the molding compound on the sidewall of the redistribution structure.

[0021] Optionally, it also includes: a plurality of patterned openings, the patterned openings penetrating the first photoresist layer and the second photoresist layer, and a portion of the patterned openings penetrating the second photoresist layer in the first groove; and electrical terminals located in the patterned openings.

[0022] The technical solution of the present invention has the following beneficial effects:

[0023] The semiconductor packaging method of this invention involves coating a first initial photoresist layer on the side of the seed layer away from the redistribution structure, followed by removing at least a portion of the thickness of the edge region of the first initial photoresist layer to form a first photoresist layer with a first groove on its periphery. Because at least a portion of the thickness of the edge region of the first initial photoresist layer is removed, this step can remove flow marks when they exist on the edge of the upper surface of the first initial photoresist layer. After forming the first groove, the first photoresist layer undergoes an initial curing treatment, which shapes the first photoresist layer to a certain extent, making it less prone to flow. Then, a second photoresist layer is coated on the side of the first photoresist layer away from the seed layer and in the first groove. Because the sidewalls of the first groove act as a barrier to the second photoresist layer coated in the first groove, flow marks on the top surface of the second photoresist layer in the first groove are reduced. Secondly, during the coating process to form the second photoresist layer, the photoresist is flung from the top surface of the first photoresist layer outwards. Some photoresist remains on the top surface of the first photoresist layer, while the portion flung to the edge overflows into the first groove. Therefore, there are no flow marks on the top surface of the first photoresist layer. Thirdly, the process of the photoresist overflowing into the first groove involves impacting the bottom surface of the groove from top to bottom. The horizontal force experienced by the photoresist overflowing into the first groove is very small, further reducing flow marks on the top surface of the second photoresist layer formed in the first groove. Because the flow marks on the top surface of the second photoresist layer are reduced, the upper surface of the second photoresist layer is smoother, and the thickness uniformity of the edge region of the second photoresist layer is improved. This improves the uniformity of the height of the subsequent patterned first photoresist layer and the patterned openings formed by the first photoresist layer, reducing the probability of electrical terminal abnormalities and improving yield. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figures 1 to 3 This is a schematic diagram of a semiconductor packaging process in the prior art;

[0026] Figure 4 A flowchart of a semiconductor packaging method provided in an embodiment of the present invention;

[0027] Figures 5 to 13This is a schematic diagram of a semiconductor packaging process provided in an embodiment of the present invention. Detailed Implementation

[0028] The yield of semiconductor packaging structures formed by existing semiconductor packaging methods is reduced.

[0029] The inventor discovered through research that the reason is:

[0030] The step of forming a patterned photoresist layer 6' on the side of the seed layer 5' facing away from the redistribution structure 2' includes: spin-coating a photoresist film onto the side of the seed layer 5' facing away from the redistribution structure 2'; and then exposing and developing the photoresist film to form the patterned photoresist layer 6'. In the step of spin-coating the photoresist film onto the side of the seed layer 5' facing away from the redistribution structure 2', the initial package is rotated by a rotating machine. The centrifugal force generated by the rotation of the initial package removes excess photoresist applied to the surface of the seed layer 5' by the coating mechanism, aiming to form a photoresist film of uniform thickness on the surface of the seed layer 5'. When excess photoresist applied to the surface of the seed layer 5' cannot be removed in time, a protrusion will form at the edge of the photoresist film, with a width of approximately 1 mm.

[0031] During the formation of the molding compound 3′, a portion of the molding compound flows along the sidewall surface of the redistribution structure 2′ to the side of the redistribution structure 2′ facing away from the chip 4′, thereby forming an annular protrusion (not shown) at the edge of the layer on the side of the redistribution structure 2′ facing away from the chip 4′. Due to the presence of the annular protrusion, the photoresist that should have been directly ejected is blocked by the annular protrusion and flows back, resulting in a relatively large flow mark 64′ (approximately 4mm to 5mm) at the edge of the top surface of the photoresist film.

[0032] Before exposure and development of the photoresist film, a washing process is used to remove approximately 1mm of the photoresist film's edge to ensure there are no protrusions. The width of the edge removal during washing cannot be too large, otherwise it would significantly waste the effective area of ​​the photoresist film, affecting the fabrication of the electrical terminals 62'. Therefore, even after removing approximately 1mm of the photoresist film's edge, flow marks 64' of a certain width still exist. The presence of flow marks 64' results in inconsistent thickness of the photoresist film's edge region before exposure and development. Furthermore, because the patterned photoresist layer 6' required to define the electrical terminals 62' is relatively thick, the corresponding photoresist film thickness is also relatively thick, leading to more flow marks 64'.

[0033] Based on this, the depth of the patterned openings 61' in the formed patterned photoresist layer 6' is inconsistent. Specifically, during the development step of the photoresist film, the photoresist in the thinner areas of the film is easily washed away, forming abnormal openings. During the electroplating process to form electrical terminals 62' in these abnormal openings, metal is easily filled in, leading to over-plating and the formation of abnormal bumps on the seed layer 5'. When the electrical terminals 62' are connected to the external packaging substrate, these abnormal bumps can also enter the circuitry of the external packaging substrate, causing short circuits. Furthermore, when the depth of the patterned openings 61' is inconsistent, the amount of electroplated metal filled in each opening 61' is different, resulting in inconsistent heights of the formed electrical terminals 62'. When the height of the electrical terminals 62' is less than the preset height, solder joint defects occur when the electrical terminals 62' are connected to the external packaging substrate. This leads to a decrease in the yield of the formed semiconductor package structure.

[0034] To address the aforementioned technical problems, this invention provides a semiconductor packaging method and a semiconductor packaging structure, thereby improving the yield of the formed semiconductor packaging structure.

[0035] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0037] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0038] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0039] Example 1

[0040] This embodiment provides a semiconductor packaging method, referencing... Figure 4 ,include:

[0041] Step S1: Form an initial package, the initial package comprising: a redistribution structure; a chip located on one side of the redistribution structure; a seed layer located on the side of the redistribution structure opposite to the chip; and a molding compound layer located on the side of the redistribution structure opposite to the seed layer and encapsulating the chip.

[0042] Step S2: Coat the seed layer on the side facing away from the redistribution structure with a first initial photoresist layer;

[0043] Step S3: Remove at least a portion of the thickness of the edge region of the first initial photoresist layer, so that the first initial photoresist layer forms a first photoresist layer, and the periphery of the first photoresist layer has a first groove;

[0044] Step S4: After forming the first groove, perform initial curing treatment on the first photoresist layer;

[0045] Step S5: After initial curing of the first photoresist layer, a second photoresist layer is coated on the side of the first photoresist layer opposite to the seed layer and in the first groove.

[0046] In this embodiment, after coating the seed layer on the side facing away from the redistribution structure with a first initial photoresist layer, at least a portion of the thickness of the edge region of the first initial photoresist layer is removed, thus forming a first photoresist layer with a first groove on its periphery. Since at least a portion of the thickness of the edge region of the first initial photoresist layer is removed, this step can remove flow marks when they exist on the edge of the upper surface of the first initial photoresist layer. After forming the first groove, the first photoresist layer undergoes an initial curing treatment, which shapes the first photoresist layer to a certain extent, making it less prone to flow. Then, a second photoresist layer is coated on the side of the first photoresist layer facing away from the seed layer and in the first groove. Since the sidewalls of the first groove act as a barrier to the second photoresist layer coated in the first groove, flow marks on the top surface of the second photoresist layer in the first groove are reduced. Secondly, during the coating process to form the second photoresist layer, the photoresist is flung from the top surface of the first photoresist layer outwards. Some photoresist remains on the top surface of the first photoresist layer, while the portion flung to the edge overflows into the first groove. Therefore, there are no flow marks on the top surface of the first photoresist layer. Thirdly, the process of the photoresist overflowing into the first groove involves impacting the bottom surface of the groove from top to bottom. The horizontal force experienced by the photoresist overflowing into the first groove is very small, further reducing flow marks on the top surface of the second photoresist layer formed in the first groove. Because the flow marks on the top surface of the second photoresist layer are reduced, the upper surface of the second photoresist layer is smoother, and the thickness uniformity of the edge region of the second photoresist layer is improved. This improves the uniformity of the height of the subsequent patterned first photoresist layer and the patterned openings formed by the first photoresist layer, reducing the probability of electrical terminal abnormalities and improving yield.

[0047] The following is for reference. Figures 5 to 13 This section details the process of semiconductor packaging methods.

[0048] refer to Figure 5 An initial package is formed, comprising: a redistribution structure 2; a chip 4 located on one side of the redistribution structure 2; a seed layer 5 located on the side of the redistribution structure 2 opposite to the chip 4; and a molding compound 3 located on the side of the redistribution structure 2 opposite to the seed layer 5 and encapsulating the chip 4.

[0049] The redistribution structure 2 includes a redistribution conductive layer 21 and a dielectric layer 22, wherein the redistribution conductive layer 21 is located within the dielectric layer 22. The redistribution conductive layer 21 may consist of multiple layers.

[0050] Interconnect pads 13 are provided on the surface of the redistribution structure 2 facing away from the seed layer 5. Conductive pillars 11 and a solder layer 12 are provided on the active side of the chip 4, with the solder layer 12 disposed on the surface of the conductive pillars 11 facing away from the chip 4. The chip 4 includes internal chip pads, and the conductive pillars 11 are connected to the internal chip pads.

[0051] The solder layer 12 is connected to the interconnect pad 13 on the side facing away from the conductive pillar 11. The solder layer 12, conductive pillar 11, and interconnect pad 13 constitute a conductive connector. A conductive connector is provided between the chip 4 and the redistribution structure 2. The chip 4 is electrically connected to the redistribution structure 2 through the chip-in-chip pads, conductive pillar 11, solder layer 12, and interconnect pad 13.

[0052] In this embodiment, the molding layer 3 also encapsulates the sidewall of the redistribution structure 2. The molding layer 3 located on the sidewall of the redistribution structure 2 protrudes from the side surface of the seed layer 5 away from the chip 4, and the molding layer 3 protruding from the side surface of the seed layer 5 away from the chip 4 constitutes a molding protrusion 131.

[0053] It should be noted that in other embodiments, the molding layer does not cover the sidewalls of the redistribution structure; the molding layer is only disposed on the side of the redistribution structure away from the chip.

[0054] In this embodiment, a patterned photoresist layer needs to be formed to define the positions of the electrical terminals. The thickness of the patterned photoresist layer needs to match the height of the electrical terminals; therefore, the patterned photoresist layer needs to be relatively thick. In this embodiment, the patterned photoresist layer is formed by patterning a first photoresist layer and an Mth photoresist layer as a whole. After coating and forming any mth photoresist layer and before coating the next photoresist layer, the mth photoresist layer needs to be soft-baked. To reduce the number of heating cycles for any mth photoresist layer and improve the stability of the first and Mth photoresist layers, M needs to be set to be less than or equal to 3. Here, m is an integer greater than or equal to 1 and less than or equal to M.

[0055] In this embodiment, M equals 2 as an example for illustration.

[0056] In some embodiments, the thickness of the patterned photoresist layer is 60 micrometers to 120 micrometers; the thickness of any m-th photoresist layer is 20 micrometers to 40 micrometers.

[0057] refer to Figure 6 A first initial photoresist layer 62 is coated on the side of the seed layer 5 opposite to the redistribution structure 2.

[0058] In this embodiment, during the step of coating the first initial photoresist layer 62 on the side of the seed layer 5 away from the redistribution structure 2, the edge region of the first initial photoresist layer 62 has a first protrusion (reference). Figure 6 The reason for the formation of the first protrusion is that during the spin coating of the first initial photoresist layer 62, some photoresist in the edge area of ​​the first initial photoresist layer 62 was not detached from the first initial photoresist layer 62 and accumulated in the edge area of ​​the first initial photoresist layer 62, thus forming the first protrusion.

[0059] In some embodiments, the width of the first protrusion is 0.2 mm, 0.5 mm, 1 mm, 1.5 mm, or 2 mm.

[0060] In other embodiments, during the step of coating the first initial photoresist layer on the side of the seed layer away from the redistribution structure, the edge region of the first initial photoresist layer does not have a first protrusion.

[0061] When the encapsulation layer 3 located on the side wall of the redistribution structure 2 protrudes from the seed layer 5 on the side surface away from the chip 4, the first protrusion corresponds to the encapsulation layer 3 located on the side wall of the redistribution structure 2.

[0062] In this embodiment, during the step of coating the first initial photoresist layer 62 on the side of the seed layer 5 away from the redistribution structure 2, the first initial photoresist layer 62 also covers the molding layer 3 located on the sidewall of the redistribution structure 2, that is, the first initial photoresist layer 62 also covers the molding protrusion 131; the height of the surface of the first initial photoresist layer 62 away from the seed layer 5 to the seed layer 5 is greater than the height of the molding layer protruding from the seed layer 5 on the sidewall of the redistribution structure.

[0063] In other embodiments, the thickness of the first initial photoresist layer 62 is not limited. The first initial photoresist layer does not cover the molding protrusion 131. The thickness of the first initial photoresist layer is less than or equal to the height of the molding protrusion 131.

[0064] In some embodiments, the semiconductor packaging method further includes: pre-wetting the surface of the seed layer 5 facing away from the redistribution structure 2 before coating the seed layer 5 on the side facing away from the redistribution structure 2 with a first initial photoresist layer 62.

[0065] In the pre-wetting treatment, a pre-wetting solution is sprayed onto the surface of the seed layer 5 on the side opposite to the redistribution structure 2.

[0066] The pre-wetting treatment is used to wet the surface of the seed layer 5 so that, during the process of coating the first initial photoresist layer 62 on the side of the seed layer 5 away from the redistribution structure 2, the first initial photoresist layer 62 can more easily cover each area of ​​the surface of the seed layer 5.

[0067] Because high-viscosity photoresists have poor crawling ability, they are not easy to cover every area of ​​the seed layer 5 surface during coating, especially when the surface roughness of the seed layer 5 is large. However, in the pre-wetting process, the pre-wetting solution can cover every area of ​​the seed layer 5 surface, filling in any seams or voids on the seed layer 5 surface to avoid creating seams or voids during the formation of the first initial photoresist layer 62. This allows the first initial photoresist layer 62 to be coated more evenly and smoothly on the seed layer 5.

[0068] In some embodiments, the pre-wetting solution used in the pre-wetting treatment comprises 70%–80% propylene glycol methyl ether and 20%–30% propylene glycol methyl acetate by mass. In other embodiments, pre-wetting treatment may be omitted.

[0069] In some embodiments, the step of coating the seed layer 5 on the side opposite to the redistribution structure 2 with a first initial photoresist layer 62 includes: a first step: placing the initial package on the spin coating platform of a spin coater, guiding the photoresist to the upper surface of the seed layer 5, and the spin coating platform driving the initial package to rotate to spin coat the photoresist on the upper surface of the seed layer 5 until there is a sufficient amount of photoresist on the upper surface of the seed layer 5. In the first step, the rotational angular velocity of the spin coating platform gradually increases to a preset rotational angular velocity ω; a second step: the spin coating platform driving the initial package to rotate at a preset rotational angular velocity, and the excess photoresist is thrown away from the seed layer of the initial package by centrifugal force, thereby forming the first initial photoresist layer 62 on the seed layer 5.

[0070] The time for the second step is t, and the viscosity of the photoresist in the second step is N.

[0071] The thickness of the first initial photoresist layer 62

[0072] In some embodiments, the thickness of the first initial photoresist layer 62 is 20 micrometers to 40 micrometers. The relatively thick thickness of the first initial photoresist layer 62 reduces the number of soft-feed cycles required, thus improving its stability.

[0073] Because the first initial photoresist layer 62 is relatively thick, flow marks are easily formed in the edge region of the top surface of the first initial photoresist layer, and the width of the flow marks is greater than the width of the first protrusion.

[0074] In some embodiments, the width of the flow mark is 4mm-7mm, for example 5mm.

[0075] refer to Figure 7 and Figure 8At least a portion of the thickness of the edge region of the first initial photoresist layer 62 is removed, such that the first initial photoresist layer 62 forms a first photoresist layer 62a, and the periphery of the first photoresist layer 62a has a first groove 65.

[0076] The step of removing at least a portion of the thickness of the edge region of the first initial photoresist layer 62 includes: (Refer to...) Figure 7 A first edge washing process is performed on the first initial photoresist layer 62; refer to Figure 8 After performing the first edge washing process, the first initial photoresist layer 62 is subjected to a second edge washing process to form a first photoresist layer 62a. The edge washing width of the second edge washing process is greater than the edge washing width of the first edge washing process, and the edge washing depth of the second edge washing process is greater than the edge washing depth of the first edge washing process.

[0077] Because the first edge washing process and the second edge washing process are used to form the first groove, the bottom surface of the first groove is relatively flat and the side wall surface of the first groove is relatively vertical.

[0078] In one embodiment, the edge washing width of the first edge washing process is 0.2mm-2mm; the edge washing width of the second edge washing process is 4mm-7mm.

[0079] When the first protrusion is formed, the first initial photoresist layer 62 is subjected to a first edge washing process to remove the first protrusion.

[0080] Regardless of whether the first protrusion is formed, the first edge washing process and the second edge washing process are used to form the first groove 65. In this way, it is not necessary to detect the presence of the first protrusion, and the process used to form the first groove is uniform, so there is no need to adjust the process.

[0081] In other embodiments, the first groove may be formed using a single edge-washing process.

[0082] In this embodiment, the seed layer 5 is exposed at the bottom of the first groove 65. In other embodiments, the seed layer is not exposed at the bottom of the first groove, that is, the first groove is located at the edge region of a portion of the thickness of the first photoresist layer, and the bottom surface of the first groove is the material of the first photoresist layer.

[0083] In this embodiment, the first groove is located between the first photoresist layer and the molding layer of the sidewall of the redistribution structure, that is, the first groove is located between the first photoresist layer and the molding protrusion 131.

[0084] In other embodiments, when no molding protrusion 131 is formed, the side of the first groove away from the central region of the first photoresist layer is an open opening.

[0085] refer to Figure 9After the first groove 65 is formed, the first photoresist layer 62a is subjected to initial curing treatment.

[0086] In some embodiments, the initial curing process is a soft-bake process.

[0087] The initial curing process is used to remove some of the solvent in the first photoresist layer 62a and to shape the first photoresist layer 62a to a certain extent, so that the first photoresist layer 62a is not easy to flow.

[0088] In some embodiments, the temperature of the initial curing treatment is 95°C to 140°C.

[0089] In some embodiments, after the first photoresist layer is initially cured, and before the second photoresist layer is coated on the side of the first photoresist layer opposite to the seed layer and in the first groove, the mass concentration of the residual solvent in the first photoresist layer is 5% to 10%.

[0090] refer to Figure 10 , Figure 11 and Figure 12 After initial curing of the first photoresist layer 62a, a second photoresist layer 63 is coated on the side of the first photoresist layer 62a opposite to the seed layer 5 and in the first groove 65.

[0091] The process of coating the second photoresist layer 63 on the side of the first photoresist layer 62a opposite to the seed layer 5 and in the first groove 65 is a spin coating process.

[0092] refer to Figure 10 The photoresist is applied from the center region of the first photoresist layer 62a to the edge region of the first photoresist layer 62a until some of the photoresist flows into the first groove 65; Reference Figure 11 The photoresist flows from the first groove 65 toward the sidewall of the first photoresist layer 62a to the sidewall of the molding protrusion 131. After being blocked at the sidewall of the molding protrusion 131, the photoresist then flows toward the sidewall of the first photoresist layer 62a. (Reference) Figure 12 Sufficient photoresist fills the first groove 65, and a thicker second photoresist layer 63 is formed on the top surface of the first photoresist layer 62a.

[0093] Because the sidewalls of the first groove 65 act as a barrier to the second photoresist layer 63 coated in the first groove 65, flow marks on the top surface of the second photoresist layer 63 in the first groove 65 are reduced. Secondly, during the coating process of forming the second photoresist layer 63, the photoresist is thrown from the top surface of the first photoresist layer 62a to the outer edge. Some photoresist remains on the top surface of the first photoresist layer 62a, while some photoresist that reaches the edge of the top surface of the first photoresist layer 62a overflows into the first groove 65. Therefore, no flow marks exist on the top surface of the first photoresist layer 62a. Thirdly, the process of the photoresist overflowing into the first groove 65 involves impacting the bottom surface of the first groove 65 from top to bottom. The horizontal force experienced by the photoresist overflowing into the first groove 65 is very small, thus further reducing flow marks on the top surface of the second photoresist layer 63 formed in the first groove 65.

[0094] In this embodiment, during the step of coating the second photoresist layer 63 on the surface of the first photoresist layer 62a facing away from the seed layer 5 and in the first groove 65, the edge region of the second photoresist layer 63 has a second protrusion (see reference). Figure 12 ).

[0095] The reason for the formation of the second protrusion is that during the spin coating of the second photoresist layer 63, some photoresist in the edge area of ​​the second photoresist layer 63 was not detached and accumulated in the edge area of ​​the second photoresist layer 63, thus forming the second protrusion.

[0096] In some embodiments, the width of the second protrusion is 1 mm to 1.5 mm.

[0097] When the encapsulation layer 3 located on the side wall of the redistribution structure 2 protrudes from the seed layer 5 on the side surface away from the chip 4, the second protrusion corresponds to the encapsulation layer 3 located on the side wall of the redistribution structure 2.

[0098] In other embodiments, during the step of coating the second photoresist layer 63 on the side of the first photoresist layer 62a opposite to the seed layer 5 and in the first groove 65, the edge region of the second photoresist layer 63 does not have a second protrusion.

[0099] refer to Figure 13 The semiconductor packaging method further includes: performing a third edge washing process on the second photoresist layer 63, wherein the edge washing width of the third edge washing process is smaller than the width of the first groove.

[0100] When the second protrusion is formed, the third edge washing process is used to remove the second protrusion.

[0101] In some embodiments, the edge washing width of the third edge washing process is 1mm to 1.5mm.

[0102] After the third edge washing process, the second photoresist layer and the first photoresist layer are cured.

[0103] The curing temperature is higher than the initial curing temperature.

[0104] Because the flow marks on the top surface of the second photoresist layer are reduced, the upper surface of the second photoresist layer is relatively flat, and the thickness uniformity of the edge region of the second photoresist layer is improved.

[0105] In this embodiment, the method further includes: patterning the first photoresist layer 62a and the second photoresist layer 63 to form a plurality of patterned openings penetrating the first photoresist layer 62a and the second photoresist layer 63, with some of the patterned openings penetrating the second photoresist layer in the first groove 65; and forming electrical terminals (not shown) in the patterned openings.

[0106] Because the thickness uniformity of the edge region of the second photoresist layer is improved, the height uniformity of the patterned opening formed by the patterned first photoresist layer and the first photoresist layer is improved, reducing the probability of abnormalities in electrical terminals and improving yield.

[0107] In some embodiments, the outer edge region of the patterned photoresist layer has an invalid region with a width of 2.5 mm to 3 mm.

[0108] Another embodiment of the present invention also provides a semiconductor packaging structure, see reference. Figure 13 The device includes: a redistribution structure; a chip located on one side of the redistribution structure; a seed layer located on the side of the redistribution structure opposite to the chip; a molding compound layer located on the side of the redistribution structure opposite to the seed layer and encapsulating the chip; a first photoresist layer located on the side of the seed layer opposite to the redistribution structure, the first photoresist layer having a first groove on its periphery; and a second photoresist layer located on the side of the first photoresist layer opposite to the seed layer and in the first groove.

[0109] The bottom of the first groove extends to the surface of the seed layer.

[0110] The width of the first groove is 4mm to 7mm.

[0111] In this embodiment, the molding layer further encapsulates the sidewall of the redistribution structure, and the molding layer located on the sidewall of the redistribution structure protrudes from the seed layer on the side surface away from the chip; the first groove is located between the first photoresist layer and the molding layer of the sidewall of the redistribution structure.

[0112] In other embodiments, the molding layer does not cover the sidewalls of the redistribution structure.

[0113] In some embodiments, the semiconductor package structure further includes: a plurality of patterned openings (not shown), the patterned openings penetrating a first photoresist layer and a second photoresist layer, and a portion of the patterned openings penetrating a second photoresist layer in a first groove; and electrical terminals located in the patterned openings.

[0114] Another embodiment of the present invention also provides a semiconductor packaging method. The difference between the semiconductor packaging method of this embodiment and the semiconductor packaging method of the aforementioned embodiment is that: after performing a third edge washing process on the second photoresist layer 63, a fourth edge washing process is performed on the second photoresist layer 63. The edge washing width of the fourth edge washing process is greater than the edge washing width of the third edge washing process, and the edge washing depth of the fourth edge washing process is greater than the edge washing depth of the third edge washing process, so as to have a second groove on the periphery of the second photoresist layer; after forming the second groove, the second photoresist layer is subjected to an initial curing treatment; after the initial curing treatment of the second photoresist layer, a third photoresist layer is coated on the side surface of the second photoresist layer opposite to the seed layer and in the second groove.

[0115] The dimensional parameters of the second groove are the same as those of the first groove, and will not be described in detail again.

[0116] The second groove penetrates the second photoresist layer or is located in a portion of the thickness of the second photoresist layer.

[0117] The second groove has an open opening on the side opposite to the center region of the second photoresist layer.

[0118] Another embodiment of the present invention provides a semiconductor packaging structure. The difference between the semiconductor packaging structure of this embodiment and the semiconductor packaging structure of the previous embodiment is that: the second photoresist layer has a second groove on its peripheral side; it also includes: a third photoresist layer located on the side surface of the second photoresist layer away from the seed layer and in the second groove; a patterned opening penetrating the first photoresist layer, the second photoresist layer and the third photoresist layer, with a portion of the patterned opening penetrating the second photoresist layer in the first groove and the third photoresist layer in the second groove; and an electrical terminal located in the patterned opening.

[0119] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A semiconductor packaging method, characterized in that, include: An initial package is formed, the initial package comprising: a redistribution structure; a chip located on one side of the redistribution structure; a seed layer located on the side of the redistribution structure opposite to the chip; and a molding compound layer located on the side of the redistribution structure opposite to the seed layer and encapsulating the chip. A first initial photoresist layer is coated on the side of the seed layer opposite to the redistribution structure; At least a portion of the thickness of the first initial photoresist layer is removed from the edge region, such that the first initial photoresist layer forms a first photoresist layer, and the peripheral side of the first photoresist layer has a first groove. After the first groove is formed, the first photoresist layer is subjected to initial curing treatment; After initial curing of the first photoresist layer, a second photoresist layer is coated on the side of the first photoresist layer opposite to the seed layer and in the first groove.

2. The semiconductor packaging method according to claim 1, characterized in that, The step of removing at least a portion of the thickness of the edge region of the first initial photoresist layer includes: performing a first edge washing process on the first initial photoresist layer; and after performing the first edge washing process, performing a second edge washing process on the first initial photoresist layer to form a first photoresist layer, wherein the edge washing width of the second edge washing process is greater than the edge washing width of the first edge washing process, and the edge washing depth of the second edge washing process is greater than the edge washing depth of the first edge washing process.

3. The semiconductor packaging method according to claim 2, characterized in that, The edge washing width of the first edge washing process is 0.2mm-2mm; the edge washing width of the second edge washing process is 4mm-7mm.

4. The semiconductor packaging method according to claim 2, characterized in that, In the step of coating the first initial photoresist layer on the side of the seed layer away from the redistribution structure, the edge region of the first initial photoresist layer has a first protrusion; the first initial photoresist layer is subjected to a first edge washing process to remove the first protrusion.

5. The semiconductor packaging method according to claim 1, characterized in that, Before the second photoresist layer is coated, the bottom of the first groove exposes the seed layer.

6. The semiconductor packaging method according to claim 1, characterized in that, Also includes: A third edge-washing process is performed on the second photoresist layer, and the edge-washing width of the third edge-washing process is smaller than the width of the first groove.

7. The semiconductor packaging method according to claim 6, characterized in that, In the step of coating the second photoresist layer on the side of the first photoresist layer opposite to the seed layer and in the first groove, the edge region of the second photoresist layer has a second protrusion; the third edge washing process is used to remove the second protrusion.

8. The semiconductor packaging method according to claim 6, characterized in that, Also includes: After the third edge washing process, the second photoresist layer and the first photoresist layer are cured.

9. The semiconductor packaging method according to claim 1, characterized in that, The initial curing process is a soft-bake process.

10. The semiconductor packaging method according to claim 1, characterized in that, Also includes: Before coating the first initial photoresist layer on the side of the seed layer away from the redistribution structure, the surface of the seed layer on the side away from the redistribution structure is pre-wetted.

11. The semiconductor packaging method according to claim 1, characterized in that, The molding layer does not cover the sidewalls of the redistribution structure; Alternatively, the molding compound layer may also encapsulate the sidewalls of the redistribution structure, with the molding compound layer located on the sidewalls of the redistribution structure protruding from the seed layer on the side surface opposite to the chip. In the step of coating the first initial photoresist layer on the side of the seed layer away from the redistribution structure, the first initial photoresist layer also covers the molding compound layer located on the sidewall of the redistribution structure; the height of the surface of the first initial photoresist layer away from the seed layer to the seed layer is greater than the height of the molding compound layer located on the sidewall of the redistribution structure protruding from the seed layer. The first groove is located between the first photoresist layer and the molding layer of the sidewall of the redistribution structure.

12. The semiconductor packaging method according to claim 1, characterized in that, Also includes: The first photoresist layer and the second photoresist layer are patterned to form a plurality of patterned openings that penetrate the first photoresist layer and the second photoresist layer, and some of the patterned openings penetrate the second photoresist layer in the first groove. Electrical terminals are formed in the patterned opening.

13. A semiconductor packaging structure, characterized in that, include: Rewiring structure; A chip located on one side of the redistribution structure; A seed layer located on the side surface of the rewiring structure opposite to the chip; A molding layer is located on the side of the redistribution structure opposite to the seed layer and encapsulates the chip. A first photoresist layer is located on the side of the seed layer opposite to the redistribution structure, and the periphery of the first photoresist layer has a first groove. The second photoresist layer is located on the side surface of the first photoresist layer opposite to the seed layer and in the first groove.

14. The semiconductor packaging structure according to claim 13, characterized in that, The bottom of the first groove extends to the surface of the seed layer.

15. The semiconductor packaging structure according to claim 13, characterized in that, The width of the first groove is 4mm to 7mm.

16. The semiconductor packaging structure according to claim 13, characterized in that, The molding layer does not cover the sidewalls of the redistribution structure; Alternatively, the molding compound layer may further encapsulate the sidewall of the redistribution structure, with the molding compound layer on the sidewall of the redistribution structure protruding from the seed layer on the side surface opposite to the chip; the first groove is located between the first photoresist layer and the molding compound layer on the sidewall of the redistribution structure.

17. The semiconductor packaging structure according to claim 13, characterized in that, Also includes: Several patterned openings penetrate the first photoresist layer and the second photoresist layer, and some patterned openings penetrate the second photoresist layer in the first groove. Electrical terminals located in the patterned opening.

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