semiconductor element

Abstract

A semiconductor device is disclosed. The semiconductor device includes a first set of entity alignment marks disposed on a substrate and comprising a first layer of alignment marks disposed on the substrate and a second layer of alignment marks disposed on and offset from the first layer of alignment marks of the first set of entity alignment marks, and a first set of spacer alignment marks disposed on the substrate, distanced from the first set of entity alignment marks, and comprising a first layer of alignment marks disposed on the substrate and distanced from the first layer of alignment marks of the first set of entity alignment marks and a second layer of alignment marks disposed on and offset from the first layer of alignment marks of the first set of spacer alignment marks. The first set of entity alignment marks and the first set of spacer alignment marks comprise a fluorescent material.

Description

Technical Field

[0001] This application claims priority to patent applications Nos. 17 / 676,999 and 17 / 677,358 (i.e., priority date "February 22, 2022"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor element and a method for fabricating the semiconductor element. In particular, it relates to a semiconductor element having alignment marks and a method for fabricating the same. Background Technology

[0003] Semiconductor components are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is continuously shrinking to meet the ever-increasing demands for computing power. However, various problems arise during this shrinking process, and these problems are increasing. Therefore, challenges remain in achieving improvements in quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device including a first group of entity alignment marks and a first group of spacer alignment marks disposed on a substrate. The first group of entity alignment marks includes: a first layer alignment mark disposed on the substrate, and a second layer alignment mark disposed on and offset from the first layer alignment mark. The first group of spacer alignment marks, being distanced from the first group of entity alignment marks, includes: a first layer alignment mark disposed on the substrate and distanced from the first layer alignment mark, and a second layer alignment mark disposed on and offset from the first layer alignment mark. The first group of entity alignment marks and the first group of spacer alignment marks comprise a fluorescent material.

[0006] Another aspect of this disclosure provides a semiconductor device including a first conductive layer disposed on a substrate and a second conductive layer disposed on the first insulating layer; a first group entity alignment mark, including: a first layer alignment mark disposed in the first conductive layer and a second layer alignment mark disposed in the second conductive layer and offset from the first layer alignment mark of the first group entity alignment mark; and a first group spacer alignment mark, including: a first layer alignment mark disposed in the first conductive layer and far from the first layer alignment mark of the first group entity alignment mark and a second layer alignment mark disposed in the second conductive layer and offset from the first layer alignment mark of the first group spacer alignment mark. The first group entity alignment mark and the first group spacer alignment mark include a fluorescent material.

[0007] Another aspect of this disclosure provides a method for fabricating a semiconductor device, the method comprising: providing a substrate; forming a first set of solid alignment marks and a first set of spacer alignment marks on the substrate, which are spaced apart from each other. The first set of solid alignment marks includes a first layer alignment mark formed on the substrate, and a second layer alignment mark formed on top of and offset from the first layer alignment mark. The first set of spacer alignment marks includes a first layer alignment mark formed on the substrate and offset from the first layer alignment mark, and a second layer alignment mark formed on top of and offset from the first layer alignment mark. The first set of solid alignment marks and the first set of spacer alignment marks comprise a fluorescent material.

[0008] Due to the design of the semiconductor device disclosed herein, the alignment marks 111, 113, 115, 117, 121, 123, 125, 127, 131, 133, 135, 137, 141, 143, 145, 147, 211, 213, 215, 217, 221, 223, 225, 227, 231, 233, 235, 237, 241, 243, 245, and 247 of the fluorescent material can improve optical recognition during the wafer fabrication process. Therefore, the yield of semiconductor device 1A can be improved.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0010] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0011] Figure 1 This is a top view illustrating a semiconductor element according to an embodiment of the present disclosure.

[0012] Figure 2 and Figure 3 It is along Figure 1 Sectional views of lines A-A', B-B', C-C' and D-D'.

[0013] Figure 4 This is a top view illustrating a semiconductor element according to another embodiment of the present disclosure.

[0014] Figure 5 and Figure 6 It is along Figure 4 Sectional views of lines A-A', B-B', C-C' and D-D'.

[0015] Figure 7 This is a flowchart illustrating a method for fabricating a semiconductor element according to an embodiment of this disclosure.

[0016] Figure 8 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0017] Figure 9 and Figure 10 It is along Figure 8 The cross-sectional views of lines A-A', B-B', C-C', and D-D' illustrate a portion of the fabrication process of a semiconductor element according to an embodiment of the present disclosure.

[0018] Figure 11 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0019] Figure 12 and Figure 13 It is along Figure 11The cross-sectional views of lines A-A', B-B', C-C', and D-D' illustrate a portion of the fabrication process of a semiconductor element according to an embodiment of the present disclosure.

[0020] Figure 14 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0021] Figure 15 and Figure 16 It is along Figure 14 The cross-sectional views of lines A-A', B-B', C-C', and D-D' illustrate a portion of the fabrication process of a semiconductor element according to an embodiment of the present disclosure.

[0022] Figure 17 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0023] Figure 18 and Figure 19 It is along Figure 17 The cross-sectional views of lines A-A', B-B', C-C', and D-D' illustrate a portion of the fabrication process of a semiconductor element according to an embodiment of the present disclosure.

[0024] Figure 20 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0025] Figure 21 and Figure 22 It is along Figure 20 The cross-sectional views of lines A-A', B-B', C-C', and D-D' illustrate a portion of the fabrication process of a semiconductor element according to an embodiment of the present disclosure.

[0026] Figure 23 This is a flowchart illustrating a method for fabricating a semiconductor element according to another embodiment of this disclosure.

[0027] Figure 24 This is a top view illustrating an intermediate semiconductor element according to another embodiment of the present disclosure.

[0028] Figure 25 and Figure 26 It is along Figure 24 The cross-sectional views of lines A-A', B-B', C-C', and D-D' illustrate a portion of the fabrication process of a semiconductor element according to another embodiment of the present disclosure.

[0029] Figure 27 This is a top view illustrating an intermediate semiconductor element according to another embodiment of the present disclosure.

[0030] Figures 28 to 31 It is along Figure 27The cross-sectional views of lines A-A', B-B', C-C', and D-D' illustrate a portion of the fabrication process of a semiconductor element according to another embodiment of the present disclosure.

[0031] Figure 32 This is a top view illustrating an intermediate semiconductor element according to another embodiment of the present disclosure.

[0032] Figure 33 and Figure 34 It is along Figure 32 The cross-sectional views of lines A-A', B-B', C-C', and D-D' illustrate a portion of the fabrication process of a semiconductor element according to another embodiment of the present disclosure.

[0033] The reference numerals in the attached figures are explained as follows:

[0034] 1A: Semiconductor components

[0035] 1B: Semiconductor components

[0036] 10: Preparation method

[0037] 20: Preparation method

[0038] 110: First group entity alignment mark

[0039] 100-1: First set of entity alignment marks

[0040] 100-2: Second set of entity alignment marks

[0041] 111: First layer alignment mark

[0042] 113: Second layer alignment mark

[0043] 115: Third layer alignment mark

[0044] 117: Fourth layer alignment mark

[0045] 120: Second group entity alignment mark

[0046] 121: First layer alignment mark

[0047] 123: Second layer alignment mark

[0048] 125: Third layer alignment mark

[0049] 127: Fourth layer alignment mark

[0050] 130: Third group entity alignment mark

[0051] 131: First layer alignment mark

[0052] 133: Second layer alignment mark

[0053] 135: Third layer alignment mark

[0054] 137: Fourth layer alignment mark

[0055] 140: Fourth Group Entity Alignment Mark

[0056] 141: First layer alignment mark

[0057] 143: Second layer alignment mark

[0058] 145: Third layer alignment mark

[0059] 147: Fourth layer alignment mark

[0060] 200-1: First set of alignment marks

[0061] 200-2: Second set of alignment marks

[0062] 210: First group interval alignment mark

[0063] 211: First layer alignment mark

[0064] 213: Second layer alignment mark

[0065] 215: Third layer alignment mark

[0066] 217: Fourth layer alignment mark

[0067] 220: Second group interval alignment mark

[0068] 221: First layer alignment mark

[0069] 223: Second layer alignment mark

[0070] 225: Third layer alignment mark

[0071] 227: Fourth layer alignment mark

[0072] 230: Third group interval alignment mark

[0073] 231: First layer alignment mark

[0074] 233: Second layer alignment mark

[0075] 235: Third layer alignment mark

[0076] 237: Fourth layer alignment mark

[0077] 240: Fourth group interval alignment mark

[0078] 241: First layer alignment mark

[0079] 243: Second layer alignment mark

[0080] 245: Third layer alignment mark

[0081] 247: Fourth layer alignment mark

[0082] 301: Base

[0083] 311: First insulating layer

[0084] 313: Second insulating layer

[0085] 315: Third insulation layer

[0086] 317: Fourth Insulation Layer

[0087] 321: First conductive layer

[0088] 323: Second conductive layer

[0089] 325: Third conductive layer

[0090] 327: Fourth conductive layer

[0091] 411: First bottom pad

[0092] 413: Second bottom pad

[0093] 415: Third bottom pad

[0094] 417: Fourth bottom pad

[0095] 421: First top pad

[0096] 423: Second top pad

[0097] 425: Third top pad

[0098] 427: Fourth Top Pad

[0099] A-A': line

[0100] B-B': Line

[0101] C-C': Line

[0102] D-D': Line

[0103] D1: Distance

[0104] D2: Distance

[0105] D3: Distance

[0106] G1: Distance

[0107] L1: Length

[0108] L2: Length

[0109] L3: Length

[0110] S1: First axis of symmetry

[0111] S11: Steps

[0112] S13: Steps

[0113] S15: Steps

[0114] S17: Steps

[0115] S19: Steps

[0116] S2: Second axis of symmetry

[0117] S21: Steps

[0118] S23: Steps

[0119] S25: Steps

[0120] S3: Third axis of symmetry

[0121] TR1: Trench

[0122] TR2: Trench

[0123] TR3: Trench

[0124] TR4: Trench

[0125] W1: Width

[0126] W2: Width

[0127] W3: Width

[0128] X: Direction

[0129] Y: direction

[0130] Z: Direction Detailed Implementation

[0131] The following disclosure provides many different implementations or examples for achieving different features of the provided subject matter. To simplify this disclosure, specific examples of elements and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on a second feature may include implementations where the first and second features are in direct contact, or implementations where additional features can be formed between the first and second features, thus allowing the first and second features to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various implementations. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various implementations and / or configurations discussed.

[0132] It should be understood that although terms such as first, second, etc., are used here to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from another. Thus, for example, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part without departing from the teachings of this disclosure.

[0133] Unless the context otherwise requires, when referring to orientation, layout, location, shape, size, quantity, or other measures, the terms “identical,” “equal,” “planar,” or “coplanar” used herein do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measures, but rather that they include substantially the same orientation, layout, location, shape, size, quantity, or other measures within the range of acceptable variations that may occur, such as due to manufacturing processes. The term “substantially” may be used here to reflect this meaning. For example, items described as “substantially identical,” “substantially equal,” or “substantially planar” can be exactly the same, equal, or planar, or they can be the same, equal, or planar within the range of acceptable variations that may occur, such as due to manufacturing processes.

[0134] Figure 1 This is a top view illustrating a semiconductor element 1A according to an embodiment of the present disclosure. Figure 2 It is along Figure 1 A sectional view of line A-A' and line B-B'. Figure 3 It is along Figure 1 A cross-sectional view of line C-C' and line D-D'.

[0135] Reference Figures 1 to 3 Semiconductor element 1A may include a substrate 301, a first insulating layer 311, a second insulating layer 313, a third insulating layer 315, a fourth insulating layer 317, a first set of physical alignment marks 100-1, a second set of physical alignment marks 100-2, a first set of spacer alignment marks 200-1, and a second set of spacer alignment marks 200-2.

[0136] Reference Figures 1 to 3The substrate 301 may include a bulk semiconductor substrate composed entirely of at least one semiconductor material, multiple element units (not shown for clarity), multiple dielectric layers (not shown for clarity), and multiple conductive features (not shown for clarity). The bulk semiconductor substrate may include, for example, an elemental semiconductor such as silicon or germanium; a compound semiconductor such as silicon-germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V or group II-VI compound semiconductors; or combinations thereof. In some embodiments, the substrate 301 may include a semiconductor-on-insulator structure comprising, from bottom to top, a processing substrate, an insulating layer, and a topmost semiconductor material layer. The processing substrate and the topmost semiconductor material layer may contain the same materials as the bulk semiconductor substrate described above. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride.

[0137] Multiple dielectric layers may be formed on the bulk semiconductor substrate or the uppermost semiconductor material layer, covering the multiple element units. In some embodiments, the multiple dielectric layers may comprise, for example, silicon oxide, borophosphate glass, undoped silicate glass, fluorinated silicate glass, a low-k dielectric material, or combinations thereof. The dielectric constant of the low-k dielectric material may be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-k dielectric material may be less than 2.0.

[0138] The plurality of conductive features may include an interconnect layer and a conductive via. The interconnect layers may be separated from each other and may be horizontally disposed in the plurality of dielectric layers along the Z direction. The conductive via may connect adjacent interconnect layers, as well as adjacent component cells and interconnect layers, along the Z direction. In some embodiments, the conductive via may improve heat dissipation and provide structural support. In some embodiments, the plurality of conductive features may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0139] In some embodiments, the plurality of element units and the plurality of conductive features may be configured together in a functional unit within the substrate 301. In the description of this disclosure, the functional unit generally refers to a function-related circuit that has been divided into a separate unit. In some embodiments, the functional unit may be a typically highly complex circuit, such as a processor core, memory controller, or accelerator unit. In other embodiments, the complexity and functionality of the functional unit may be more or less complex.

[0140] Reference Figures 1 to 3A first insulating layer 311 may be disposed on a substrate 301, a second insulating layer 313 may be disposed on the first insulating layer 311, a third insulating layer 315 may be disposed on the second insulating layer 313, and a fourth insulating layer 317 may be disposed on the third insulating layer 315. The first insulating layer 311, the second insulating layer 313, the third insulating layer 315, and the fourth insulating layer 317 may comprise, for example, silicon oxide, borophosphate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, or combinations thereof. In some embodiments, the first insulating layer 311, the second insulating layer 313, the third insulating layer 315, and the fourth insulating layer 317 may be part of a plurality of dielectric layers of the substrate 301.

[0141] Reference Figures 1 to 3 The first group of entity alignment marks 100-1 may include the first group of entity alignment marks 110 and the second group of entity alignment marks 120. The first group of entity alignment marks 110 may include the first layer alignment mark 111, the second layer alignment mark 113, the third layer alignment mark 115 and the fourth layer alignment mark 117.

[0142] Reference Figures 1 to 3 In some embodiments, the first alignment mark 111 may be linear in a top view. The first alignment mark 111 may extend along the Y direction. The first alignment mark 111 may be disposed in the first insulating layer 311 and on the substrate 301.

[0143] In cross-section, the second alignment mark 113 may be disposed within the second insulating layer 313 and may be offset from the first alignment mark 111. In other words, the second alignment mark 113 may not be directly above the first alignment mark 111. In top view, the second alignment mark 113 may be linear. The second alignment mark 113 may extend along the Y direction and may be separated from the first alignment mark 111 along the X direction.

[0144] In cross-section, the third alignment mark 115 may be disposed within the third insulating layer 315 and may be offset from the second alignment mark 113. In other words, the third alignment mark 115 may not be directly above the second alignment mark 113. From a top view, the third alignment mark 115 may be linear. The third alignment mark 115 may extend along the Y direction and may be separated from the second alignment mark 113 along the X direction. The second alignment mark 113 may be disposed between the first alignment mark 111 and the third alignment mark 115.

[0145] In cross-section, the fourth alignment mark 117 can be disposed within the fourth insulating layer 317 and can be offset from the third alignment mark 115. In other words, the fourth alignment mark 117 may not be directly above the third alignment mark 115. From a top view, the fourth alignment mark 117 can be linear. The fourth alignment mark 117 can extend along the Y direction and can be separated from the third alignment mark 115 along the X direction. The third alignment mark 115 can be disposed between the second alignment mark 113 and the fourth alignment mark 117.

[0146] In some embodiments, the first alignment mark 111, the second alignment mark 113, the third alignment mark 115, and the fourth alignment mark 117 may be aligned with each other along the Y direction.

[0147] In some embodiments, the length L1 and width W1 of the first alignment mark 111 may be different from a top-down view. For example, the length L1 of the first alignment mark 111 may be greater than the width W1 of the first alignment mark 111. In some embodiments, the length L1 and width W1 of the first alignment mark 111 may be substantially the same.

[0148] In some embodiments, the lengths of the second alignment mark 113, the third alignment mark 115, and the fourth alignment mark 117 may be substantially the same as the length L1 of the first alignment mark 111. In some embodiments, the lengths of the second alignment mark 113, the third alignment mark 115, and the fourth alignment mark 117 may be different from the length L1 of the first alignment mark 111. For example, the length L2 of the second alignment mark 113 may be the same as or different from the length L1 of the first alignment mark 111.

[0149] In some embodiments, the widths of the second alignment mark 113, the third alignment mark 115, and the fourth alignment mark 117 may be substantially the same as the width W1 of the first alignment mark 111. In some embodiments, the widths of the second alignment mark 113, the third alignment mark 115, and the fourth alignment mark 117 may be different from the width W1 of the first alignment mark 111. For example, the width W2 of the second alignment mark 113 may be the same as or different from the width W1 of the first alignment mark 111.

[0150] In some embodiments, from a top-down view, the width W1 of the first alignment mark 111 and the distance D1 between the first alignment mark 111 and the second alignment mark 113 may be different. For example, the width W1 of the first alignment mark 111 may be greater than the distance D1 between the first alignment mark 111 and the second alignment mark 113. In some embodiments, the width W1 of the first alignment mark 111 and the distance D1 between the first alignment mark 111 and the second alignment mark 113 may be substantially the same.

[0151] In some embodiments, from a top-down view, the distances D1, D2, and D3 between alignment marks 111, 113, 115, and 117 can be substantially the same. In some embodiments, the distances D1, D2, and D3 between alignment marks 111, 113, 115, and 117 can be different. For example, the distance D1 between the first layer alignment mark 111 and the second layer alignment mark 113 can be greater than or less than the distance D2 between the second layer alignment mark 113 and the third layer alignment mark 115.

[0152] In some embodiments, the first alignment mark 111, the second alignment mark 113, the third alignment mark 115, and the fourth alignment mark 117 may include a fluorescent material. In some embodiments, the fluorescent material may be azobenzene. Alignment marks 111, 113, 115, and 117 including fluorescent material can improve optical recognition during wafer fabrication.

[0153] Reference Figures 1 to 3 The second group of entity alignment marks 120 may include a first layer alignment mark 121, a second layer alignment mark 123, a third layer alignment mark 125, and a fourth layer alignment mark 127.

[0154] Reference Figures 1 to 3 In some embodiments, the first alignment mark 121 may be linear in a top view. The first alignment mark 121 may extend along the Y direction. The second alignment mark 113 may be aligned with the third alignment mark 115 along the X direction and separated from the third alignment mark 115 along the Y direction.

[0155] In cross-section, the second alignment mark 123 may be disposed within the second insulating layer 313 and may be offset from the first alignment mark 121. In other words, the second alignment mark 123 may not be directly above the first alignment mark 121. From a top-down view, the second alignment mark 123 may be linear. The second alignment mark 123 may extend along the Y direction and may be separated from the first alignment mark 121 along the X direction. The second alignment mark 123 may be aligned with the fourth alignment mark 117 along the X direction and separated from the fourth alignment mark 117 along the Y direction.

[0156] In cross-section, the third alignment mark 125 may be disposed within the third insulating layer 315 and may be offset from the second alignment mark 123. In other words, the third alignment mark 125 may not be directly above the second alignment mark 123. From a top view, the third alignment mark 125 may be linear. The third alignment mark 125 may extend along the Y direction and may be distancing itself from the first alignment mark 121 along the X direction. The third alignment mark 125 may be aligned with the first alignment mark 111 along the X direction and separated from the first alignment mark 111 along the Y direction.

[0157] In cross-section, the fourth alignment mark 127 can be disposed within the fourth insulating layer 317 and can be offset from the third alignment mark 125. In other words, the fourth alignment mark 127 may not be directly above the third alignment mark 125. From a top view, the fourth alignment mark 127 can be linear. The fourth alignment mark 127 can extend along the Y direction and can be separated from the third alignment mark 125 along the X direction. For example, the fourth alignment mark 127 can be disposed between the first alignment mark 121 and the third alignment mark 125. As another example, the fourth alignment mark 127 can be aligned with the second alignment mark 113 along the X direction, and the fourth alignment mark 127 can be separated from the second alignment mark 113 along the Y direction.

[0158] In some embodiments, the first alignment mark 121, the second alignment mark 123, the third alignment mark 125 and the fourth alignment mark 127 may be aligned with each other along the Y direction.

[0159] In some embodiments, the width W3 of the first layer alignment mark 121 and the width W1 of the first layer alignment mark 111 may be substantially the same. In some embodiments, the width W3 of the first layer alignment mark 121 and the width W1 of the first layer alignment mark 111 may be substantially the same. In some embodiments, the length L3 of the first layer alignment mark 121 and the length L1 of the first layer alignment mark 111 may be substantially the same. In some embodiments, the length L3 of the first layer alignment mark 121 and the length L1 of the first layer alignment mark 111 may be different.

[0160] In some embodiments, the lengths of the second alignment mark 123, the third alignment mark 125, and the fourth alignment mark 127 may be substantially the same as the length L3 of the first alignment mark 121. In some embodiments, the lengths of the second alignment mark 123, the third alignment mark 125, and the fourth alignment mark 127 may be different from the length L3 of the first alignment mark 121. In some embodiments, the widths of the second alignment mark 123, the third alignment mark 125, and the fourth alignment mark 127 may be substantially the same as the width W3 of the first alignment mark 121. In some embodiments, the widths of the second alignment mark 123, the third alignment mark 125, and the fourth alignment mark 127 may be different from the width W3 of the first alignment mark 121.

[0161] In some embodiments, the length L1 of the first alignment mark 111 and the distance G1 between the third alignment mark 115 and the first alignment mark 121 can be substantially the same. In some embodiments, the length L1 of the first alignment mark 111 and the distance G1 between the third alignment mark 115 and the first alignment mark 121 can be different. For example, the length L1 of the first alignment mark 111 can be greater than the distance G1 between the third alignment mark 115 and the first alignment mark 121.

[0162] In some embodiments, the width W1 of the first alignment mark 111 and the distance G1 between the third alignment mark 115 and the first alignment mark 121 can be substantially the same. In some embodiments, the width W1 of the first alignment mark 111 and the distance G1 between the third alignment mark 115 and the first alignment mark 121 can be different. For example, the width W1 of the first alignment mark 111 can be greater than the distance G1 between the third alignment mark 115 and the first alignment mark 121.

[0163] In some embodiments, the first alignment mark 121, the second alignment mark 123, the third alignment mark 125, and the fourth alignment mark 127 may include a fluorescent material. In some embodiments, the fluorescent material may be azobenzene. Alignment marks 121, 123, 125, and 127 including fluorescent material can improve optical recognition during wafer fabrication.

[0164] Reference Figures 1 to 3In some embodiments, the first set of spacing alignment marks 200-1 can be set as a mirror image of the first set of entity alignment marks 100-1 according to the first axis of symmetry S1. The first set of spacing alignment marks 200-1 may include a first set of spacing alignment marks 210 and a second set of spacing alignment marks 220. The first set of spacing alignment marks 210 and the first set of entity alignment marks 110 can be set as a mirror image of the first axis of symmetry S1. The second set of spacing alignment marks 220 and the second set of entity alignment marks 120 can be set as a mirror image of the first axis of symmetry S1.

[0165] In detail, the first group spacing alignment mark 210 may include a first layer alignment mark 211, a second layer alignment mark 213, a third layer alignment mark 215, and a fourth layer alignment mark 217. The first layer alignment mark 211 and the first layer alignment mark 211 are set in a mirror image according to the first axis of symmetry S1. The second layer alignment mark 213 and the second layer alignment mark 213 are set in a mirror image according to the first axis of symmetry S1. The third layer alignment mark 215 and the third layer alignment mark 215 are set in a mirror image according to the first axis of symmetry S1. The fourth layer alignment mark 217 and the fourth layer alignment mark 217 are set in a mirror image according to the first axis of symmetry S1.

[0166] Similarly, the second group spacing alignment mark 220 may include a first layer alignment mark 221, a second layer alignment mark 223, a third layer alignment mark 225, and a fourth layer alignment mark 227. The first layer alignment mark 221, the second layer alignment mark 223, the third layer alignment mark 225, and the fourth layer alignment mark 227 may be configured respectively and correspondingly according to the first axis of symmetry S1 in a mirror manner of the first layer alignment mark 221, the second layer alignment mark 223, the third layer alignment mark 225, and the fourth layer alignment mark 227.

[0167] Reference Figures 1 to 3 In some embodiments, the second set of entity alignment marks 100-2 can be set as a mirror image of the first set of entity alignment marks 100-1 according to the second axis of symmetry S2. The second set of entity alignment marks 100-2 may include a third set of entity alignment marks 130 and a fourth set of entity alignment marks 140. The third set of entity alignment marks 130 and the first set of entity alignment marks 110 can be set as a mirror image according to the second axis of symmetry S2. The fourth set of entity alignment marks 140 and the second set of entity alignment marks 120 can be set as a mirror image according to the second axis of symmetry S2.

[0168] In detail, the third group of entity alignment marks 130 may include a first-layer alignment mark 131, a second-layer alignment mark 133, a third-layer alignment mark 135, and a fourth-layer alignment mark 137. The first-layer alignment marks 131 and 133 are mirror images of each other based on the second axis of symmetry S2. The second-layer alignment marks 133 and 113 are mirror images of each other based on the second axis of symmetry S2. The third-layer alignment marks 135 and 115 are mirror images of each other based on the second axis of symmetry S2. The fourth-layer alignment marks 137 and 117 are mirror images of each other based on the second axis of symmetry S2.

[0169] Similarly, the fourth group of entity alignment marks 140 may include a first-layer alignment mark 141, a second-layer alignment mark 143, a third-layer alignment mark 145, and a fourth-layer alignment mark 147. The first-layer alignment mark 141, the second-layer alignment mark 143, the third-layer alignment mark 145, and the fourth-layer alignment mark 147 may be configured respectively and correspondingly according to the first axis of symmetry S1 in a mirror manner of the first-layer alignment mark 121, the second-layer alignment mark 123, the third-layer alignment mark 125, and the fourth-layer alignment mark 127.

[0170] Reference Figures 1 to 3 In some embodiments, the second set of spacing alignment marks 200-2 can be set as a mirror image of the second set of entity alignment marks 100-2 according to the first axis of symmetry S1, or the second set of spacing alignment marks 200-2 can be set as a mirror image of the first set of spacing alignment marks 200-1 according to the third axis of symmetry S3. The second set of spacing alignment marks 200-2 may include a third set of spacing alignment marks 230 and a fourth set of spacing alignment marks 240. The third set of spacing alignment marks 230 and the third set of entity alignment marks 130 can be set as a mirror image of the first axis of symmetry S1. The fourth set of spacing alignment marks 240 and the fourth set of entity alignment marks 140 can be set as a mirror image of the first axis of symmetry S1.

[0171] Similarly, the third group spacing alignment mark 230 may include a first layer alignment mark 231, a second layer alignment mark 233, a third layer alignment mark 235, and a fourth layer alignment mark 237. The first layer alignment mark 231, the second layer alignment mark 233, the third layer alignment mark 235, and the fourth layer alignment mark 237 may be configured respectively and correspondingly according to the first axis of symmetry S1 in a mirror manner of the first layer alignment mark 131, the second layer alignment mark 133, the third layer alignment mark 135, and the fourth layer alignment mark 137.

[0172] Similarly, the fourth group spacing alignment mark 240 may include a first layer alignment mark 241, a second layer alignment mark 243, a third layer alignment mark 245, and a fourth layer alignment mark 247. The first layer alignment mark 241, the second layer alignment mark 243, the third layer alignment mark 245, and the fourth layer alignment mark 247 may be configured respectively and correspondingly according to the first axis of symmetry S1 in a mirror manner of the first layer alignment mark 141, the second layer alignment mark 143, the third layer alignment mark 145, and the fourth layer alignment mark 147.

[0173] The first layer alignment marks 131, 141, 211, 221, 231, 241, the second layer alignment marks 133, 143, 213, 223, 233, 243, the third layer alignment marks 135, 145, 215, 225, 235, 245, and the fourth layer alignment marks 137, 147, 217, 227, 237, 247 may include a fluorescent material. In some embodiments, the fluorescent material may be azobenzene. The alignment marks 131, 141, 211, 221, 231, 241, 133, 143, 213, 223, 233, 243, 135, 145, 215, 225, 235, 245, 137, 147, 217, 227, 237, 247 including fluorescent material can improve optical recognition during wafer fabrication.

[0174] Figure 4 This is a top view illustrating a semiconductor element 1B according to another embodiment of the present disclosure. Figure 5 It is along Figure 4 A sectional view of line A-A' and line B-B'. Figure 6 It is along Figure 4 A cross-sectional view of line C-C' and line D-D'.

[0175] Reference Figures 4 to 6 Semiconductor element 1B may include a first conductive layer 321, a second conductive layer 323, a third conductive layer 325, a fourth conductive layer 327, a first set of entity alignment marks 100-1, a second set of entity alignment marks 100-2, a first set of spacer alignment marks 200-1, a second set of spacer alignment marks 200-2, a first bottom pad 411, a second bottom pad 413, a third bottom pad 415, a fourth bottom pad 417, a first top pad 421, a second top pad 423, a third top pad 425, and a fourth top pad 427.

[0176] The substrate 301 may have a similar Figures 1 to 3The structure shown is not described again here. The first conductive layer 321, the second conductive layer 323, the third conductive layer 325, and the fourth conductive layer 327 may be stacked sequentially on the substrate 301. The first conductive layer 321, the second conductive layer 323, the third conductive layer 325, and the fourth top pad 427 may comprise, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum compounds, or combinations thereof. In some embodiments, the first conductive layer 321, the second conductive layer 323, the third conductive layer 325, and the fourth top pad 427 may be part of the conductive features of the substrate 301. In some embodiments, the conductive layers 321, 323, 325, and 327 may be electrically coupled to multiple element units of the substrate 301, but are not limited thereto. In some embodiments, the conductive layers 321, 323, 325, and 327 may be configured as a test circuit.

[0177] Reference Figures 4 to 6 The first group of entity alignment marks 100-1, the second group of entity alignment marks 100-2, the first group of interval alignment marks 200-1, and the second group of interval alignment marks 200-2 can be similar to Figures 1 to 3 The configuration is as shown in the diagram. The difference is that the first layer alignment marks 111, 121, 131, 141, 211, 221, 231, and 241 can be located in the first conductive layer 321; the second layer alignment marks 113, 123, 133, 143, 213, 223, 233, and 243 can be located in the second conductive layer 323; the third layer alignment marks 115, 125, 135, 145, 215, 225, 235, and 245 can be located in the third conductive layer 325; and the fourth layer alignment marks 117, 127, 137, 147, 217, 227, 237, and 247 can be located in the fourth conductive layer 327.

[0178] Reference Figures 4 to 6The first bottom pad 411 can be disposed between the second conductive layer 323 and the first conductive layer 321, between the first layer alignment marks 111, 121, 131, 141, 211, 221, 231, 241 and the first conductive layer 321, and between the first layer alignment marks 111, 121, 131, 141, 211, 221, 231, 241 and the substrate 301. The first top pad 421 can be disposed between the first bottom pad 411 and the second conductive layer 323, and between the first layer alignment marks 111, 121, 131, 141, 211, 221, 231, 241 and the second conductive layer 323. The second bottom pad 413, the third bottom pad 415 and the fourth bottom pad 417 can be disposed in a manner similar to that of the first bottom pad 411, and their description will not be repeated here. The second top pad 423, the third top pad 425, and the fourth top pad 427 can be configured in a manner similar to that of the first top pad 421, and their description will not be repeated here.

[0179] In some embodiments, the first bottom pad 411, the second bottom pad 413, and the fourth bottom pad 417 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or combinations thereof. In some embodiments, the first top pad 421, the second top pad 423, the third top pad 425, and the fourth top pad 427 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or combinations thereof. The bottom pads 411, 413, 415, 417 and the top pads 421, 423, 425, 427 may serve as a barrier layer to prevent the diffusion of fluorescent material in the alignment mark from contaminating adjacent element units.

[0180] It should be noted that, Figure 5 and Figure 6 The bottom pads 411, 413, 415, and 417 that completely cover the conductive layers 321, 323, 325, and 327 are for illustrative purposes only. Some portions of the conductive layers 321, 323, 325, and 327 may be exposed to allow for electrical coupling with other conductive features.

[0181] Figure 7 This is a flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of this disclosure. Figure 8 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 9 It is along Figure 8 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 10 It is along Figure 8The cross-sectional views along lines C-C' and D-D' illustrate a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0182] Reference Figures 7 to 10 In step S11, a substrate 301 may be provided, a first insulating layer 311 may be formed on the substrate 301, and a plurality of trenches TR1, TR2, TR3 and TR4 may be formed in the first insulating layer 311.

[0183] Reference Figures 8 to 10 The fabrication technique for the first insulating layer 311 on the substrate 301 may include, for example, chemical vapor deposition or other suitable deposition processes. The fabrication technique for the plurality of trenches TR1, TR2, TR3, TR4 in the first insulating layer 311 may include lithography and subsequent etching processes. A portion of the substrate 301 may be exposed through the plurality of trenches TR1, TR2, TR3, TR4.

[0184] Figure 11 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 12 It is along Figure 11 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 13 It is along Figure 11 The cross-sectional views along lines C-C' and D-D' illustrate a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0185] Reference Figure 7 and Figures 11 to 13 In step S13, first layer alignment marks 111, 121, 131, 141, 211, 221, 231, and 241 can be formed in multiple trenches TR1, TR2, TR3, and TR4.

[0186] Reference Figures 11 to 13 An insulating layer (not shown) can be deposited to completely fill the multiple trenches TR1, TR2, TR3, TR4. The insulating layer may include a fluorescent material. In some embodiments, the fluorescent material may be azobenzene. In some embodiments, the fabrication technique of the insulating layer may include, for example, chemical vapor deposition. A planarization process, such as chemical mechanical polishing, may be performed until the top surface of the first insulating layer 311 is exposed to remove excess material, provide a substantially flat surface for subsequent processing steps, and simultaneously form the first layer alignment marks 111, 121, 131, 141, 211, 221, 231, 241.

[0187] Figure 14 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 15 It is along Figure 14 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 16 It is along Figure 14 The cross-sectional views along lines C-C' and D-D' illustrate a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0188] Reference Figure 7 and Figures 14 to 16 In step S15, a second insulating layer 313 may be formed on the first insulating layer 311, and second alignment marks 113, 123, 133, 143, 213, 223, 233, and 243 may be formed in the second insulating layer 313.

[0189] Reference Figures 14 to 16 The second insulating layer 313 may have a structure similar to that of the first insulating layer 311, and may be formed using a similar procedure to that of the first insulating layer 311, which will not be described again here. The second layer alignment marks 113, 123, 133, 143, 213, 223, 233, and 243 may be formed using a procedure similar to that of the first layer alignment marks 111, 121, 131, 141, 211, 221, 231, and 241, which will not be described again here.

[0190] Figure 17 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 18 It is along Figure 17 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 19 It is along Figure 17 The cross-sectional views along lines C-C' and D-D' illustrate a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0191] Reference Figure 7 and Figures 17 to 19 In step S17, a third insulating layer 315 may be formed on the second insulating layer 313, and third alignment marks 115, 125, 135, 145, 215, 225, 235, and 245 may be formed in the third insulating layer 315.

[0192] Reference Figures 17 to 19The third insulating layer 315 may have a structure similar to that of the first insulating layer 311, and may be formed using a similar procedure as that of the first insulating layer 311, the description of which will not be repeated here. The alignment marks 115, 125, 135, 145, 215, 225, 235, and 245 of the third layer may be formed using a procedure similar to that of the alignment marks 111, 121, 131, 141, 211, 221, 231, and 241 of the first layer, the description of which will not be repeated here.

[0193] Figure 20 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 21 It is along Figure 20 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 22 It is along Figure 20 The cross-sectional views along lines C-C' and D-D' illustrate a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0194] Reference Figure 7 and Figures 20 to 22 In step S19, a fourth insulating layer 317 may be formed on the third insulating layer 315, and fourth alignment marks 117, 127, 137, 147, 217, 227, 237, and 247 may be formed in the fourth insulating layer 317.

[0195] Reference Figures 20 to 22 The fourth insulating layer 317 may have a structure similar to that of the first insulating layer 311 and may be formed using a similar procedure as that of the first insulating layer 311, the description of which will not be repeated here. The alignment marks 117, 127, 137, 147, 217, 227, 237, and 247 of the fourth layer may be formed using a procedure similar to that of the alignment marks 111, 121, 131, 141, 211, 221, 231, and 241 of the first layer, the description of which will not be repeated here.

[0196] Figure 23 This is a flowchart illustrating a method 20 for fabricating a semiconductor element 1B according to another embodiment of this disclosure. Figure 24 This is a top view illustrating an intermediate semiconductor element according to another embodiment of the present disclosure. Figure 25 It is along Figure 24 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the fabrication process of semiconductor element 1B according to another embodiment of this disclosure. Figure 26 It is along Figure 24 The cross-sectional views along lines C-C' and D-D' illustrate a portion of the fabrication process of semiconductor element 1B according to another embodiment of this disclosure.

[0197] Reference Figures 23 to 26In step S21, a substrate 301 may be provided, a first conductive layer 321 may be formed on the substrate 301, a plurality of trenches TR1, TR2, TR3, TR4 may be formed in the first conductive layer 321, and a first bottom pad 411 may be conformally formed in the plurality of trenches TR1, TR2, TR3, TR4 and on the first conductive layer 321.

[0198] Reference Figures 24 to 26 The substrate 301 can be used in a similar manner. Figures 8 to 10 The procedure described herein will not be repeated here. A first material layer (not shown) may be formed on substrate 301. In some embodiments, the first material may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum nitrides, or combinations thereof. The fabrication technique for the first material layer may include, for example, physical vapor deposition, sputtering, chemical vapor deposition, or other suitable deposition processes. Next, the patterning technique for the first material layer may include lithography and subsequent etching processes to form multiple trenches TR1, TR2, TR3, TR4.

[0199] Reference Figures 24 to 26 The fabrication technique for the first top liner 421 can include, for example, atomic layer deposition (ALD). Generally, ALD involves alternately supplying two (or more) different source gases to a process object (e.g., the first conductive layer 321 and multiple trenches TR1, TR2, TR3, TR4) under predetermined process conditions. This causes chemical species to be adsorbed onto the process object at a single atomic layer level and deposited onto the process object through surface reactions. For example, the first and second source gases are alternately supplied to the process object, flowing along its surface. This causes molecules contained in the first source gas to be adsorbed onto the surface, and molecules contained in the second source gas to react with the adsorbed molecules originating from the first source gas, forming a monolayer-thick film. These process steps are repeated, thus enabling the formation of a high-quality film on the process object.

[0200] Figure 27 This is a top view illustrating an intermediate semiconductor element according to another embodiment of the present disclosure. Figure 28 It is along Figure 27 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the fabrication process of semiconductor element 1B according to another embodiment of this disclosure. Figure 29 It is along Figure 27 The cross-sectional views along lines C-C' and D-D' illustrate a portion of the fabrication process of semiconductor element 1B according to another embodiment of this disclosure. Figure 30 It is along Figure 27 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the fabrication process of semiconductor element 1B according to another embodiment of this disclosure. Figure 31 It is along Figure 27 The cross-sectional views along lines C-C' and D-D' illustrate a portion of the fabrication process of semiconductor element 1B according to another embodiment of this disclosure.

[0201] Reference Figure 23 and Figures 27 to 31 In step S23, first layer alignment marks 111, 121, 131, 141, 211, 221, 231, and 241 can be formed in multiple grooves TR1, TR2, TR3, and TR4, and a first top pad 421 is conformally formed on the first bottom pad 411 and the first layer alignment marks 111, 121, 131, 141, 211, 221, 231, and 241.

[0202] Reference Figures 27 to 29 The first layer alignment marks 111, 121, 131, 141, 211, 221, 231, and 241 can be formed on multiple grooves TR1, TR2, TR3, and TR4 and the first bottom pad 411, in a procedure similar to Figures 11 to 13 As shown, its description will not be repeated here.

[0203] Reference Figure 30 and Figure 31 The fabrication technique of the first top liner 421 may include, for example, atomic layer deposition, the procedure of which is similar to that of the first bottom liner 411, and its description will not be repeated here.

[0204] Figure 32 This is a top view illustrating an intermediate semiconductor element according to another embodiment of the present disclosure. Figure 33 It is along Figure 32 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the fabrication process of semiconductor element 1B according to another embodiment of this disclosure. Figure 34 It is along Figure 32 The cross-sectional views along lines C-C' and D-D' illustrate a portion of the fabrication process of semiconductor element 1B according to another embodiment of this disclosure.

[0205] Reference Figure 23 and Figures 32 to 34 In step S25, the second layer alignment marks 113, 123, 133, 143, 213, 223, 233, 243, the third layer alignment marks 115, 125, 135, 145, 215, 225, 235, 245, and the fourth layer alignment marks 117, 127, 137, 147, 217, 227, 237, 247 can be sequentially formed on the first conductive layer 321.

[0206] Reference Figures 32 to 34A second conductive layer 323 can be formed on the first conductive layer 321. Multiple trenches (not shown) can be formed in the second conductive layer 323. A second bottom pad 413 can be conformally formed on the second conductive layer 323 and in the multiple trenches. Second layer alignment marks 113, 123, 133, 143, 213, 223, 233, and 243 can be formed in the multiple trenches. A second top pad 423 can be conformally formed on the second bottom pad 413 and on the second layer alignment marks 113, 123, 133, 143, 213, 223, 233, and 243, in a manner similar to... Figures 24 to 31 The procedure shown will not be described again here.

[0207] Similarly, the third conductive layer 325, the third bottom pad 415, the third layer alignment marks 115, 125, 135, 145, 215, 225, 235, 245, and the third top pad 425 can be similar to Figures 24 to 31 The procedure shown will not be described again here.

[0208] Similarly, the fourth conductive layer 327, the fourth bottom pad 417, the fourth alignment marks 117, 127, 137, 147, 217, 227, 237, 247, and the fourth top pad 427 can be similar to Figures 24 to 31 The procedure shown is formed, and its description will not be repeated here.

[0209] One aspect of this disclosure provides a semiconductor device including a first group of entity alignment marks and a first group of spacer alignment marks disposed on a substrate. The first group of entity alignment marks includes: a first layer alignment mark disposed on the substrate, and a second layer alignment mark disposed on and offset from the first layer alignment mark. The first group of spacer alignment marks, being distanced from the first group of entity alignment marks, includes: a first layer alignment mark disposed on the substrate and distanced from the first layer alignment mark, and a second layer alignment mark disposed on and offset from the first layer alignment mark. The first group of entity alignment marks and the first group of spacer alignment marks comprise a fluorescent material.

[0210] Another aspect of this disclosure provides a semiconductor device including a first conductive layer disposed on a substrate and a second conductive layer disposed on the first insulating layer; a first group entity alignment mark, including: a first layer alignment mark disposed in the first conductive layer and a second layer alignment mark disposed in the second conductive layer and offset from the first layer alignment mark of the first group entity alignment mark; and a first group spacer alignment mark, including: a first layer alignment mark disposed in the first conductive layer and far from the first layer alignment mark of the first group entity alignment mark and a second layer alignment mark disposed in the second conductive layer and offset from the first layer alignment mark of the first group spacer alignment mark. The first group entity alignment mark and the first group spacer alignment mark include a fluorescent material.

[0211] Another aspect of this disclosure provides a method for fabricating a semiconductor device, the method comprising: providing a substrate; forming a first set of solid alignment marks and a first set of spacer alignment marks on the substrate, which are spaced apart from each other. The first set of solid alignment marks includes a first layer alignment mark formed on the substrate, and a second layer alignment mark formed on top of and offset from the first layer alignment mark. The first set of spacer alignment marks includes a first layer alignment mark formed on the substrate and offset from the first layer alignment mark, and a second layer alignment mark formed on top of and offset from the first layer alignment mark. The first set of solid alignment marks and the first set of spacer alignment marks comprise a fluorescent material.

[0212] Due to the design of the semiconductor device disclosed herein, the alignment marks 111, 113, 115, 117, 121, 123, 125, 127, 131, 133, 135, 137, 141, 143, 145, 147, 211, 213, 215, 217, 221, 223, 225, 227, 231, 233, 235, 237, 241, 243, 245, and 247 of the fluorescent material can improve optical recognition during wafer fabrication. Therefore, the yield of semiconductor device 1A can be improved.

[0213] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0214] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A first set of entity alignment marks, set on a substrate, includes: The first layer of alignment marks of the first group of entity alignment marks is disposed on the substrate; and A second-layer alignment mark of the first group of entity alignment marks is disposed on top of and offset from the first-layer alignment mark of the first group of entity alignment marks; and A first group spacing alignment mark, disposed on the substrate and located away from the first group entity alignment mark, includes: A first layer of alignment marks of the first group of alignment marks is disposed on the substrate and is distanced from the first layer of alignment marks of the first group of entity alignment marks; and A second layer alignment mark of the first group interval alignment mark is disposed on top of and offset from the first layer alignment mark of the first group interval alignment mark; The first group of entity alignment marks and the first group of interval alignment marks include a fluorescent material; The first layer alignment mark of the first group entity alignment mark and the first layer alignment mark of the first group interval alignment mark are set in a mirror manner according to a first axis of symmetry, and the second layer alignment mark of the first group entity alignment mark and the second layer alignment mark of the first group interval alignment mark are set in a mirror manner according to the first axis of symmetry.

2. The semiconductor device of claim 1, wherein the fluorescent material comprises azobenzene.

3. The semiconductor element of claim 2, wherein the first layer alignment mark and the second layer alignment mark of the first group of entity alignment marks are linear, extending along a first direction and separated from each other along a second direction perpendicular to the first direction.

4. The semiconductor element of claim 3, wherein the first axis of symmetry extends along a direction inclined to both the first direction and the second direction.

5. The semiconductor device of claim 4, further comprising: A first insulating layer is disposed on the substrate, wherein a first layer of alignment marks of the first group of entity alignment marks is disposed in the first insulating layer; as well as A second insulating layer is disposed on the first insulating layer, wherein the second layer alignment mark of the first group of entity alignment marks is disposed in the second insulating layer.

6. The semiconductor element of claim 5, wherein the first set of entity alignment marks comprises: A third-layer alignment mark of the first group of entity alignment marks is set on top of and offset from the second-layer alignment mark of the first group of entity alignment marks; A fourth alignment mark of the first group of entity alignment marks is set on top of and offset from the third alignment mark of the first group of entity alignment marks; The third alignment mark of the first group of entity alignment marks is positioned between the second alignment mark and the fourth alignment mark of the first group of entity alignment marks in a top-down view.

7. The semiconductor element of claim 6, further comprising a second set of entity alignment marks, including: The first layer alignment mark of the second group of entity alignment marks is disposed in the first insulating layer, aligned with the third layer alignment mark of the first group of entity alignment marks along the second direction, and moved away from the third layer alignment mark of the first group of entity alignment marks along the first direction; A second layer alignment mark of the second group of entity alignment marks is disposed in the second insulating layer, aligned with the fourth layer alignment mark of the first group of entity alignment marks along the second direction, and moved away from the fourth layer alignment mark of the first group of entity alignment marks along the first direction.

8. The semiconductor element of claim 6, further comprising a third set of entity alignment marks, including: The first layer alignment mark of the third group of entity alignment marks is disposed in the first insulating layer and is separate from the first layer alignment mark of the first group of entity alignment marks; as well as A second layer alignment mark of the third group of entity alignment marks is disposed in the second insulating layer and is separated from the first layer alignment mark of the third group of entity alignment marks along the first direction.

9. The semiconductor element of claim 8, wherein the first layer alignment mark of the third group of entity alignment marks and the first layer alignment mark of the first group of entity alignment marks are arranged in a mirror manner according to a second axis of symmetry, the second layer alignment mark of the third group of entity alignment marks and the second layer alignment mark of the first group of entity alignment marks are arranged in a mirror manner according to the second axis of symmetry, and the second axis of symmetry is perpendicular to the first axis of symmetry.

10. The semiconductor element of claim 9, wherein a width of the first layer alignment mark of the first group of entity alignment marks is substantially the same as a width of the second layer alignment mark of the first group of entity alignment marks.

11. The semiconductor element of claim 9, wherein a width of the first layer alignment mark of the first group of entity alignment marks is different from a width of the second layer alignment mark of the first group of entity alignment marks.

12. The semiconductor element of claim 9, wherein a width of the first layer alignment mark of the first group of entity alignment marks is substantially the same as a distance between the first layer alignment mark of the first group of entity alignment marks and the second layer alignment mark of the first group of entity alignment marks.

13. The semiconductor element of claim 9, wherein a width of the first layer alignment mark of the first group of entity alignment marks is different from a distance between the first layer alignment mark of the first group of entity alignment marks and the second layer alignment mark of the first group of entity alignment marks.

14. The semiconductor element of claim 9, wherein a length of the first layer alignment mark of the first group of entity alignment marks is substantially the same as a length of the second layer alignment mark of the first group of entity alignment marks.

15. The semiconductor element of claim 9, wherein a length of the first layer alignment mark of the first group of entity alignment marks is different from a length of the second layer alignment mark of the first group of entity alignment marks.

16. The semiconductor element of claim 7, wherein a length of the first layer alignment mark of the first group of entity alignment marks is substantially the same as a distance between the third layer alignment mark of the first group of entity alignment marks and the first layer alignment mark of the second group of entity alignment marks.

17. The semiconductor element of claim 7, wherein a length of the first layer alignment mark of the first group of entity alignment marks is different from a distance between the third layer alignment mark of the first group of entity alignment marks and the first layer alignment mark of the second group of entity alignment marks.

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