Semiconductor device, integrated circuit, and method for manufacturing semiconductor device

Abstract

The application provides a semiconductor device, an integrated circuit and a method for manufacturing a semiconductor device. The semiconductor device includes a semiconductor substrate. A semiconductor epitaxial layer is disposed on one side of the semiconductor substrate. A metal layer is disposed on a side of the semiconductor epitaxial layer away from the semiconductor substrate. The semiconductor epitaxial layer has a doped region on a side thereof away from the semiconductor substrate. The metal layer is in contact with the doped region. The doped region includes a first doped region and a second doped region. The first doped region is disposed on a side of the second doped region close to the semiconductor substrate, and the first doped region covers the second doped region. The second doped region includes a trench disposed on a surface of the semiconductor epitaxial layer away from the semiconductor substrate. The first doped region and the second doped region are both P-type doped regions or N-type doped regions, and a doping concentration of the second doped region is greater than a doping concentration of the first doped region. The doping concentration of the second doped region can be adjusted independently, so that the ohmic contact characteristics can be improved without affecting the surface state of other regions.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device, an integrated circuit, and a method for manufacturing a semiconductor device. Background Technology

[0002] Silicon carbide (SiC) materials offer advantages over traditional silicon (Si) materials, including a wide bandgap, high critical breakdown field strength, high thermal conductivity, and high intrinsic operating temperature. Semiconductor devices made from SiC materials, such as Schottky barrier diodes (SBDs) and metal-oxide-semiconductor field-effect transistors (MOSFETs), exhibit low power consumption and ultra-high speed, and are widely used in power factor correction (PFC) rectification, photovoltaic inverters, and automotive electric drive systems.

[0003] Forward surge current reflects the surge current tolerance of a semiconductor device and is one of its important current characteristics. The forward surge current primarily depends on the current-carrying capacity of the doped region, which is limited by the contact resistance, and the contact resistance is related to the ohmic contact characteristics of the doped region. In other words, the better the ohmic contact characteristics, the lower the contact resistance, and the stronger the current-carrying capacity of the doped region. Currently, improvements in ohmic contact characteristics are mainly achieved by increasing the surface doping concentration of the doped region.

[0004] However, the diffusion coefficient of doped impurities in SiC materials is low, requiring multiple ion implantation processes. After multiple ion implantation processes, not only is the surface of the doped region damaged, but ion scattering may also occur within the doped region. These problems cannot be completely eliminated in subsequent processes such as annealing, resulting in poor overall performance of the semiconductor device. Summary of the Invention

[0005] This application provides a semiconductor device, an integrated circuit, and a method for fabricating a semiconductor device, to adjust the surface doping concentration of a doped region, thereby improving the ohmic contact characteristics of the semiconductor device without affecting the surface state of other regions.

[0006] In a first aspect, this application provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor epitaxial layer, and a metal layer, wherein the semiconductor epitaxial layer is disposed on one side of the semiconductor substrate, and the metal layer is disposed on the side of the semiconductor epitaxial layer away from the semiconductor substrate. Specifically, the side of the semiconductor epitaxial layer away from the semiconductor substrate may have a doped region. The doped region includes a first doped region and a second doped region. The first doped region is disposed on the side of the second doped region closer to the semiconductor substrate, and the first doped region covers the second doped region. The second doped region includes a trench disposed on the surface of the semiconductor epitaxial layer on the side away from the semiconductor substrate. Both the first and second doped regions are P-type doped regions, or both are N-type doped regions; and the doping concentration of the second doped region is greater than the doping concentration of the first doped region. The metal layer may contact the doped regions to form an ohmic contact.

[0007] In the aforementioned semiconductor device, the metal layer contacts the first doped region, forming a first contact resistance; the metal layer contacts the second doped region, forming a second contact resistance. Since the doping concentration of the second doped region is greater than that of the first doped region, the second contact resistance is less than the first contact resistance. When the semiconductor device is turned on, electrons in the second doped region tunnel through the Schottky barrier more easily, thereby guiding the forward current more quickly from the second doped region into the semiconductor device, thus improving the ohmic contact characteristics of the semiconductor device. Furthermore, the doping concentration of the second doped region can be adjusted independently without affecting the surface state of other areas of the semiconductor epitaxial layer.

[0008] The depth of the trench along the direction perpendicular to the semiconductor substrate can be specifically set according to the doping concentration of the doped region. For example, in some technical solutions, the trench depth can be greater than or equal to 30 nanometers, such as 30 nanometers, 35 nanometers, 43 nanometers, 50 nanometers, or 56 nanometers, etc., which will not be listed here.

[0009] In a specific technical solution, the semiconductor device can be a Schottky barrier diode. Specifically, both the first and second doped regions can be P-type doped regions. The metal layer can be used as the positive electrode metal layer for electrical connection with the positive electrode of the integrated circuit. When the PN junction of the Schottky barrier diode is turned on, electrons in the second doped region can more easily tunnel through the Schottky barrier, thereby guiding the forward surge current to quickly enter the Schottky barrier diode from the second doped region, achieving better surge current withstand capability of the Schottky barrier diode.

[0010] In another specific technical solution, the semiconductor device can be a field-effect transistor (FET). Specifically, both the first and second doped regions can be P-type doped regions or both N-type doped regions. In this technical solution, the metal layer can be used as a drain metal layer or a source metal layer. When the FET is turned on, electrons in the second doped region tunnel through the Schottky barrier more easily, thereby guiding current from the second doped region into the FET, achieving better current carrying capacity of the FET.

[0011] In the above technical solution, the type of the semiconductor epitaxial layer can be the same as the type of the first doped region. For example, the semiconductor epitaxial layer can be a P-type epitaxial layer, and the first doped region is a P-type doped region; or the semiconductor epitaxial layer can be an N-type epitaxial layer, and the first doped region is an N-type doped region. Alternatively, the type of the semiconductor epitaxial layer can be different from the type of the first doped region. For example, the semiconductor epitaxial layer can be an N-type epitaxial layer, and the first doped region is a P-type doped region; or the semiconductor epitaxial layer can be a P-type epitaxial layer, and the first doped region is an N-type doped region.

[0012] Furthermore, there are no specific restrictions on the materials of the semiconductor substrate and the semiconductor epitaxial layer. For example, the semiconductor substrate can be a silicon substrate or a silicon carbide substrate, and the semiconductor epitaxial layer can be a silicon epitaxial layer, a silicon carbide epitaxial layer, a gallium nitride (GaN) epitaxial layer, or a gallium arsenide (GaAs) epitaxial layer.

[0013] Secondly, this application provides an integrated circuit. The integrated circuit includes a circuit board and a semiconductor device as described in the first aspect. The semiconductor device is disposed on the circuit board. When the integrated circuit is turned on, a forward current enters the semiconductor device. Specifically, since the doping concentration of the second doped region is greater than that of the first doped region, electrons in the second doped region can more easily tunnel through the Schottky barrier, thereby guiding current from the second doped region into the semiconductor device, achieving better surge current withstand capability of the semiconductor device. Furthermore, the doping concentration of the second doped region can be adjusted independently without affecting the surface state of other regions of the semiconductor epitaxial layer, thereby achieving adjustment of the surface doping concentration of the doped region to improve the ohmic contact characteristics of the semiconductor device.

[0014] Thirdly, this application provides a method for fabricating the semiconductor device of the first aspect. The method includes:

[0015] Fabrication of semiconductor substrates;

[0016] Epitaxial growth of a semiconductor epitaxial layer on a semiconductor substrate;

[0017] Ions are implanted into a designated region on the side of the semiconductor epitaxial layer away from the semiconductor substrate to form a first doped region;

[0018] Trenches are fabricated on the surface of the first doped region;

[0019] Ions are implanted into the inner wall surface of the trench to form a second doped region;

[0020] A metal layer is formed on the side of the semiconductor epitaxial layer away from the semiconductor substrate, so that the metal layer is in contact with the first doped region and the second doped region.

[0021] Using the above method to fabricate semiconductor devices, a first doped region and a second doped region can be formed in different ion implantation steps. Furthermore, the formation of the second doped region does not affect the state of other surfaces of the semiconductor epitaxial layer. This allows for the individual adjustment of the surface doping concentration of the doped region to improve the ohmic contact characteristics of the semiconductor device without affecting the surface state of other regions. Attached Figure Description

[0022] Figure 1 A schematic diagram of a silicon carbide Schottky barrier diode;

[0023] Figure 2 This is a schematic diagram showing how the doping concentration in the doped region changes with depth.

[0024] Figure 3 This is a schematic diagram of the structure of a semiconductor device in an embodiment of this application;

[0025] Figure 4 This is a flowchart of a method for fabricating a semiconductor device in an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of another structure of the semiconductor device in the embodiments of this application;

[0027] Figure 6 Examples of embodiments in this application Figure 5 A schematic diagram of the doping concentration in the doped region;

[0028] Figure 7 This is a schematic diagram of another structure of the semiconductor device in the embodiments of this application.

[0029] Figure label:

[0030] 01-Silicon carbide Schottky barrier diode; 011-N-type silicon carbide substrate;

[0031] 012 - N-type silicon carbide epitaxial layer; 013 - Anode metal layer;

[0032] 014 - Field oxide layer; 015 - Passivation layer;

[0033] 016 - Polyimide layer; 017 - Ohmic contact layer;

[0034] 018 - Cathode metal layer; 0121 - P-type doped region;

[0035] 30 - Semiconductor device; 31 - Semiconductor substrate;

[0036] 32 - Semiconductor epitaxial layer; 33 - Metal layer;

[0037] 51 - N-type ohmic contact layer; 52 - Cathode metal layer;

[0038] 71 - Gate; 321 - First doped region;

[0039] 322 - Second doped region; 323 - Trench;

[0040] 331 - First metal layer; 332 - Second metal layer. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the application will be described in further detail below with reference to the accompanying drawings. To facilitate understanding of the semiconductor devices provided in the embodiments of this application, some terminology will be introduced first.

[0042] A Schottky contact refers to a situation where, when a metal and a semiconductor material come into contact, the energy bands of the semiconductor material bend at the interface, forming a Schottky barrier. The presence of this Schottky barrier results in a relatively high resistance at the interface.

[0043] An ohmic contact is a contact where, when a metal and a doped semiconductor material come into contact, electrons can tunnel through the potential barrier due to the high doping concentration of the semiconductor, thus forming an ohmic contact with a low resistance.

[0044] Inrush current refers to the instantaneous peak current flowing into a device at the moment the power is switched on. Typically, inrush current is greater than the steady-state input current.

[0045] The following explanation uses a silicon carbide Schottky barrier diode as an example.

[0046] Figure 1 This is a schematic diagram of a silicon carbide Schottky barrier diode. Figure 1As shown, the silicon carbide Schottky barrier diode 01 includes an N-type silicon carbide substrate 011. An N-type silicon carbide epitaxial layer 012 is disposed on one side of the N-type silicon carbide substrate 011. The N-type silicon carbide epitaxial layer 012 has a P-type doped region 0121. An anode metal layer 013, a field oxide layer 014, a passivation layer 015, and a polyimide (PI) layer 016 are disposed on the side of the N-type silicon carbide epitaxial layer 012 away from the N-type silicon carbide substrate 011. The anode metal layer 013 and the field oxide layer 014 are in contact with the surface of the N-type silicon carbide epitaxial layer 012, respectively. The passivation layer 015 and the polyimide layer 016 partially cover the anode metal layer 013 and completely cover the field oxide layer 014, respectively. The polyimide layer 016 is disposed on the side of the passivation layer 015 away from the N-type silicon carbide epitaxial layer 012 and covers the passivation layer 015. An ohmic contact layer 017 and a cathode metal layer 018 are disposed on the other side of the N-type silicon carbide substrate 011. The cathode metal layer 018 is disposed on the side of the ohmic contact layer 017 away from the N-type silicon carbide substrate 011 and is in contact with the ohmic contact layer 017.

[0047] It should be noted that in this application, in layers and regions prefixed with N, electrons are represented as the majority carriers; in layers and regions prefixed with P, holes are represented as the majority carriers.

[0048] In the aforementioned silicon carbide Schottky barrier diode 01, the anode metal layer 013 contacts the undoped region of the N-type silicon carbide epitaxial layer 012, forming a Schottky contact. The anode metal layer 013 contacts the P-type doped region 0121 of the N-type silicon carbide epitaxial layer 012, forming an ohmic contact. The anode metal layer 013 is connected to the positive terminal of the integrated circuit, and the cathode metal layer 018 is connected to the negative terminal of the integrated circuit. When the silicon carbide Schottky barrier diode 01 is forward-biased, the higher the doping concentration of the P-type doped region 0121, the lower the contact resistance at the ohmic contact, making it easier for electrons to tunnel through the Schottky barrier. This guides the forward surge current from the ohmic contact into the silicon carbide Schottky barrier diode 01, achieving better surge current withstand capability for the silicon carbide Schottky barrier diode 01.

[0049] In fabricating the aforementioned silicon carbide Schottky barrier diode 01, multiple ion implantation processes are typically required to achieve a high concentration of P-type doped regions 0121 in the N-type silicon carbide epitaxial layer 012. After ion implantation, the surface ion distribution of the P-type doped region 0121 is determined by the implanted beam current density (the number of ions per square centimeter) and the implantation time. Furthermore, the specific location of ions within the P-type doped region 0121 is related to ion energy, the crystal orientation of the N-type silicon carbide epitaxial layer 012, and the ion stopping mechanism.

[0050] Figure 2 This is a schematic diagram illustrating the variation of doping concentration with depth in the doped region. For example...Figure 2 As shown, the horizontal axis represents the depth from the surface of the epitaxial layer furthest from the substrate, along the direction closer to the substrate; the vertical axis represents the doping concentration at each depth after ion implantation. Figure 2 It can be seen that after ion implantation, the doping concentration at the surface of the epitaxial layer (as shown at point A) is not the maximum doping concentration; the maximum doping concentration is reached at a certain depth h (as shown at point B). Therefore, after ion implantation, the doping concentration in the doped region is not uniform. When the surface doping concentration of the doped region reaches the predetermined doping concentration, the doping concentration at a certain depth within the doped region is higher than the surface doping concentration, which is detrimental to improving the ohmic contact characteristics.

[0051] Furthermore, during ion implantation, collisions between incident ions and the epitaxial layer can cause damage to the crystal structure of the epitaxial layer, such as lattice damage, damage clusters, and vacancy-interstitial structures. These damages cannot be completely eliminated in subsequent processes such as annealing and rapid thermal processing (RTP), thus affecting the overall performance of the Schottky barrier diode.

[0052] Therefore, this application provides a semiconductor device, an integrated circuit, and a method for manufacturing a semiconductor device to adjust the surface doping concentration of a doped region without affecting the surface state of other regions, thereby improving the ohmic contact characteristics of the semiconductor device.

[0053] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in another embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0054] Figure 3 This is a schematic diagram of a semiconductor device structure in an embodiment of this application. For example... Figure 3As shown, the semiconductor device 30 may include a semiconductor substrate 31, a semiconductor epitaxial layer 32, and a metal layer 33. The semiconductor epitaxial layer 32 is disposed on one side of the semiconductor substrate 31; the metal layer 33 is disposed on the side of the semiconductor epitaxial layer 32 away from the semiconductor substrate 31 and is in contact with the surface of the semiconductor epitaxial layer 32. In this application, the semiconductor device 30 may be a Schottky barrier diode, a junction barrier Schottky diode (JBS), a merged PIN Schottky diode (MPS), a bipolar junction transistor (BJT), a MOSFET, a junction field effect transistor (JFET), or a complementary metal oxide semiconductor (CMOS), etc., and the specific type is not limited.

[0055] The specific material of the semiconductor substrate 31 is not limited; for example, the semiconductor substrate 31 can be a silicon carbide substrate or a silicon substrate. The specific type of the semiconductor substrate 31 is also not limited; for example, the semiconductor substrate 31 can be a P-type semiconductor substrate or an N-type semiconductor substrate.

[0056] Furthermore, the semiconductor epitaxial layer 32 can be made of materials such as silicon, silicon carbide, gallium nitride, or gallium arsenide, and this application does not impose specific limitations. Additionally, the specific type of the semiconductor epitaxial layer 32 is not limited; for example, the semiconductor epitaxial layer 32 can be a P-type semiconductor epitaxial layer or an N-type semiconductor epitaxial layer. In the embodiments of this application, the semiconductor substrate 31 and the semiconductor epitaxial layer 32 can be of the same type; for example, the semiconductor substrate 31 can be an N-type substrate, and the semiconductor epitaxial layer 32 can be an N-type epitaxial layer; or, the semiconductor substrate 31 can be a P-type substrate, and the semiconductor epitaxial layer 32 can be a P-type epitaxial layer. Alternatively, the semiconductor substrate 31 and the semiconductor epitaxial layer 32 can be of different types; for example, the semiconductor substrate 31 can be an N-type semiconductor substrate, and the semiconductor epitaxial layer 32 can be a P-type semiconductor epitaxial layer; or, the semiconductor substrate 31 can be an N-type semiconductor substrate, and the semiconductor epitaxial layer 32 can be a P-type semiconductor epitaxial layer.

[0057] Please continue to refer to this. Figure 3The semiconductor epitaxial layer 32 may include doped regions disposed on the side away from the semiconductor substrate 31. Specifically, the doped regions may include a first doped region 321 and a second doped region 322, wherein the first doped region 321 is disposed on the side of the second doped region 322 closer to the semiconductor substrate 31, and the first doped region 321 covers the second doped region 322. In other words, in the doped regions, except for the side of the second doped region 322 away from the semiconductor substrate 31, all other regions adjacent to the second doped region 322 are the first doped region 321. The second doped region 322 includes trenches 323 disposed on the surface of the semiconductor epitaxial layer 32. The type of the first doped region 321 is the same as the type of the second doped region 322; for example, the first doped region 321 and the second doped region 322 may both be P-type doped regions, or both may both be N-type doped regions. The doping concentration of the second doped region 322 is greater than the doping concentration of the first doped region 321. When the semiconductor device 30 is turned on, a first contact resistance is formed at the contact between the metal layer 33 and the first doped region 321, and a second contact resistance is formed at the contact between the metal layer 33 and the second doped region 322. Because the second doped region 322 has a higher doping concentration, the second contact resistance is lower than the first contact resistance, making it easier for electrons in the second doped region 322 to tunnel through the Schottky barrier. This guides forward current from the second doped region 322 into the semiconductor device 30, thereby improving the ohmic contact characteristics of the semiconductor device 30.

[0058] In the above structure, since the surface of the semiconductor epitaxial layer 32 has a trench 323 of a certain depth, after ion implantation, the doping concentration of the second doped region 322 can be greater than that of the first doped region 321, thereby achieving a higher surface doping concentration, which can improve the ohmic contact characteristics between the semiconductor epitaxial layer 32 and the metal layer 33; and the surface state of other areas of the semiconductor epitaxial layer 32, except for the surface of the doped region, is not affected by ion implantation.

[0059] In the above embodiments, the depth of trench 323 refers to the trench 323 along a direction perpendicular to the semiconductor substrate 31 (e.g., ...). Figure 3 The dimensions (in the direction indicated by the middle arrow). The depth of trench 323 can be set according to the concentration distribution of doped impurities in the semiconductor epitaxial layer 32. In some embodiments of this application, the depth of trench 323 can be greater than or equal to 30 nanometers, for example, the depth can be 30 nanometers, 35 nanometers, 43 nanometers, 50 nanometers or 56 nanometers, etc.

[0060] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figure 4 As shown, this application also provides a method for fabricating the above-described semiconductor device 30, the method comprising:

[0061] Step S401: Fabricate a semiconductor substrate.

[0062] Step S402: Epitaxially grow a semiconductor epitaxial layer on a semiconductor substrate.

[0063] Step S403: Ions are implanted into a designated region on the side of the semiconductor epitaxial layer away from the semiconductor substrate to form a first doped region.

[0064] In step S403, a first ion implantation process is performed on the designated region, wherein the first ion implantation process may include multiple ion implantations to form a first doped region 321 with a first designated doping concentration.

[0065] Step S404: Create a trench on one side surface of the first doped region.

[0066] In step S404, while forming the trench 323, the region with a low surface doping concentration in the first doped region 321 can be removed.

[0067] Step S405: Ions are implanted into the inner wall surface of the trench to form a second doped region.

[0068] In step S405, a second ion implantation process is performed on the inner wall surface of the trench 323. This second ion implantation process may include multiple ion implantations to form a second doped region 322 with a second predetermined doping concentration. This allows for a second doped region 322 with a higher surface doping concentration, and the first doped region 321 to cover the second doped region 322.

[0069] Specifically, before performing the second ion implantation process, a masking layer can be provided on the side of the semiconductor epitaxial layer 32 away from the semiconductor substrate 31, in addition to the trench 323, to prevent the second ion implantation process from affecting the state of other surface areas.

[0070] Step S406: A metal layer is formed on the side of the semiconductor epitaxial layer away from the semiconductor substrate, so that the metal layer is in contact with the first doped region and the second doped region.

[0071] When the semiconductor device 30 is fabricated using the above method, the doping concentration of the second doped region 322 can be greater than that of the first doped region 321. In addition to the doped regions, the crystal state of the side of the semiconductor epitaxial layer 32 away from the semiconductor substrate 31 is not affected by the first ion implantation process and the second ion implantation process. Furthermore, the surface doping concentration of the second doped region 322 can be adjusted independently without affecting the surface state of the first doped region 321.

[0072] Figure 5 This is a schematic diagram of another structure of the semiconductor device in an embodiment of this application. For example...Figure 5 As shown, in a specific embodiment, the semiconductor device 30 is a Schottky barrier diode. Specifically, the metal layer 33 serves as the anode metal layer and is electrically connected to the positive electrode of the integrated circuit. The first doped region 321 and the second doped region 322 are P-type doped regions. A field oxide layer 014, a passivation layer 015, and a polyimide layer 016 are also disposed on the side of the semiconductor epitaxial layer 32 away from the semiconductor substrate 31. The Schottky barrier diode may also include an N-type ohmic contact layer 51 and a cathode metal layer 52. The N-type ohmic contact layer 51 is disposed on the side of the semiconductor substrate 31 away from the semiconductor epitaxial layer 32, and the cathode metal layer 52 is disposed on the side of the N-type ohmic contact layer 51 away from the semiconductor substrate 31. The cathode metal layer 52 is electrically connected to the negative electrode of the integrated circuit.

[0073] Figure 6 Examples of embodiments in this application Figure 5 A schematic diagram showing the doping concentration of the doped region in the image. (See diagram below.) Figure 6 As shown, the horizontal axis represents the depth starting from the surface of the semiconductor epitaxial layer 32 away from the semiconductor substrate 31, along the direction close to the semiconductor substrate 31; the vertical axis represents the doping concentration at each depth after ion implantation. Figure 6 It can be seen that in the region along the tangent E of the doped region (i.e., the first doped region 321), the doping concentration reaches its maximum at depth d1; in the region along the tangent F of the doped region (i.e., the second doped region 322), the doping concentration reaches its maximum at depth d2. Depth d2 is less than depth d1, and the doping concentration at depth d2 is greater than that at depth d1. Thus, on the one hand, when the Schottky barrier diode is forward-biased, due to the higher doping concentration in the second doped region 322, electrons in the second doped region 322 can more easily tunnel through the Schottky barrier, thereby guiding the forward surge current to quickly enter the Schottky barrier diode from the second doped region 322, achieving better surge current withstand capability for the Schottky barrier diode. On the other hand, the number of ion implantations on the surfaces of the first doped region 321 and the second doped region 322 is reduced, which can improve the surface damage of the doped regions, and allows for individual adjustment of the surface doping concentration of the second doped region 322. In some other embodiments, the semiconductor device 30 may also be a junction barrier Schottky diode or a hybrid PIN Schottky diode. Similarly, the metal layer 33 may be used as the anode metal layer. Further details are omitted here.

[0074] Figure 7 This is a schematic diagram of another structure of the semiconductor device in an embodiment of this application. For example... Figure 7As shown, in a specific embodiment, the semiconductor device 30 is a field-effect transistor (FET). Specifically, the FET may include a semiconductor substrate 31, a semiconductor epitaxial layer 32, a first metal layer 331, a second metal layer 332, and a gate 71. The semiconductor epitaxial layer 32 has multiple doped regions. The first metal layer 331 and the second metal layer 332 are disposed on the side of the semiconductor epitaxial layer 32 away from the semiconductor substrate 31 and are in contact with the doped regions, respectively. The first metal layer 331 can be used as a source metal layer, and the doped region in contact with the first metal layer 331 serves as the source doped region. The second metal layer 332 can be used as a drain metal layer, and the doped region in contact with the second metal layer 332 serves as the drain doped region. When the field-effect transistor is turned on, the first metal layer 331 is connected to the second doped region 322 of the source doped region, and the second metal layer 332 is connected to the second doped region 322 of the drain doped region, so that current can enter the field-effect transistor through the second doped region 322, thereby achieving better current carrying capacity of the field-effect transistor.

[0075] The terminology used in the above embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise.

[0076] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, It includes a semiconductor substrate, and a semiconductor epitaxial layer and a metal layer disposed on one side of the semiconductor substrate, wherein: The semiconductor epitaxial layer has a doped region on the side away from the semiconductor substrate, the doped region including a first doped region and a second doped region; the first doped region is disposed on the side of the second doped region close to the semiconductor substrate, and the first doped region covers the second doped region; the second doped region includes a trench, the trench is disposed on the surface of the semiconductor epitaxial layer away from the semiconductor substrate and extends towards the semiconductor substrate, the second doped region surrounding the sidewalls and bottom of the trench; both the first doped region and the second doped region are P-type doped regions, or both the first doped region and the second doped region are N-type doped regions; the doping concentration of the second doped region is greater than the doping concentration of the first doped region; The metal layer is disposed on the side of the semiconductor epitaxial layer away from the semiconductor substrate and is in contact with the first doped region and the second doped region.

2. The semiconductor device as claimed in claim 1, characterized in that, The trench has a depth of 30 nanometers or more along the direction perpendicular to the semiconductor substrate.

3. The semiconductor device as described in claim 1 or 2, characterized in that, The semiconductor device is a Schottky barrier diode, and both the first doped region and the second doped region are P-type doped regions.

4. The semiconductor device as described in claim 1 or 2, characterized in that, The semiconductor device is a field-effect transistor; Both the first doped region and the second doped region are P-type doped regions; or, both the first doped region and the second doped region are N-type doped regions.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The first doped region is a P-type doped region, and the semiconductor epitaxial layer is an N-type epitaxial layer; or, the first doped region is an N-type doped region, and the semiconductor epitaxial layer is a P-type epitaxial layer.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The semiconductor substrate includes a silicon substrate or a silicon carbide substrate, and the semiconductor epitaxial layer is a silicon epitaxial layer, a silicon carbide epitaxial layer, a gallium nitride epitaxial layer, or a gallium arsenide epitaxial layer.

7. An integrated circuit, characterized in that, It includes a circuit board and a semiconductor device as described in any one of claims 1 to 6, wherein the semiconductor device is disposed on the circuit board.

8. A method for manufacturing a semiconductor device as described in any one of claims 1 to 6, characterized in that, The method includes: Fabrication of semiconductor substrates; A semiconductor epitaxial layer is epitaxially grown on the semiconductor substrate; Ions are implanted into a designated region on the side of the semiconductor epitaxial layer away from the semiconductor substrate to form a first doped region; Trenches are formed on the surface of the first doped region; Ions are implanted into the inner wall surface of the trench to form a second doped region; A metal layer is formed on the side of the semiconductor epitaxial layer away from the semiconductor substrate, such that the metal layer is in contact with the first doped region and the second doped region.

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