Semiconductor device

Abstract

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductor, a gate electrode, and a second electrode. The first semiconductor region is provided over the first electrode. The second semiconductor region is provided over the first semiconductor region. The third semiconductor region is provided over a part of the second semiconductor region. The conductor is provided in the first semiconductor region through an insulating portion. A lower surface of the conductor includes a first surface parallel to a second direction orthogonal to a first direction from the first electrode toward the first semiconductor region, and a second surface connected to the first surface and inclined with respect to the first direction and the second direction. The gate electrode is provided in the insulating portion and faces the second semiconductor region with a gate insulating layer interposed therebetween in the second direction. The second electrode is provided over the second semiconductor region and the third semiconductor region.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2022-21444 (filed on February 15, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention generally relate to semiconductor devices. Background Technology

[0004] Semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) are used for power conversion. For semiconductor devices, reducing leakage current is a requirement. Summary of the Invention

[0005] The implementation provides a semiconductor device capable of reducing leakage current.

[0006] According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a conductor, a gate electrode, and a second electrode. The first semiconductor region is disposed on and electrically connected to the first electrode. The second semiconductor region is disposed on the first semiconductor region. The third semiconductor region is disposed on a portion of the second semiconductor region. The conductor is disposed in the first semiconductor region via an insulating portion. The lower surface of the conductor includes a first surface and a second surface. The first surface is parallel to a second direction orthogonal to a first direction from the first electrode toward the first semiconductor region, and the second surface is connected to the first surface and inclined relative to both the first and second directions. The gate electrode is disposed in the insulating portion and faces the second semiconductor region in the second direction via a gate insulating layer. The second electrode is disposed on and electrically connected to both the second and third semiconductor regions. Attached Figure Description

[0007] Figure 1 This is a perspective cross-sectional view showing a portion of the semiconductor device according to the embodiment.

[0008] Figure 2 It is Figure 1 A magnified sectional view of a portion of the document.

[0009] Figure 3 (a) and (b) Figure 4 (a) and (b) Figure 5 (a) and (b) Figure 6(a) and (b) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0010] Figure 7 This is a cross-sectional view showing a portion of the semiconductor device of the reference example.

[0011] Figure 8 It is a line diagram that schematically represents the characteristics of a semiconductor device.

[0012] Figure 9 This is a perspective cross-sectional view showing a portion of a semiconductor device according to a modified embodiment.

[0013] Figure 10 This is a perspective cross-sectional view showing a portion of a semiconductor device according to a modified embodiment. Detailed Implementation

[0014] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0015] The accompanying drawings are schematic or conceptual, and the relationships between the thicknesses and widths of the parts, as well as the ratios between the sizes of the parts, may not be the same as in reality. Even when representing the same parts, there may be differences in the dimensions and ratios shown in the accompanying drawings.

[0016] In this application specification and figures, elements that are the same as those already described are labeled with the same reference numerals and detailed descriptions are omitted where appropriate.

[0017] In the following description and accompanying figures, n + n - p + The symbols "p" and "n" indicate the relative levels of impurity concentration. Specifically, a "+" symbol indicates a relatively higher impurity concentration compared to a symbol without either "+" or "-", while a "-" symbol indicates a relatively lower impurity concentration compared to a symbol without either. In cases where both p-type and n-type impurities are present in each region, these symbols indicate the relative levels of the net impurity concentration after these impurities have compensated for each other.

[0018] The embodiments described below can also be implemented by reversing the p-type and n-type of each semiconductor region.

[0019] Figure 1 This is a perspective cross-sectional view showing a portion of the semiconductor device according to the embodiment.

[0020] like Figure 1 As shown, the semiconductor device 100 of the embodiment includes n -Type 1 (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n-type + Type source region 3 (third semiconductor region), p + Type contact area 4, n + The device 100 comprises a drain region 5, a conductor 10, an insulating portion 21, a gate electrode 30, a drain electrode 41 (first electrode), and a source electrode 42 (second electrode). The semiconductor device 100 is, for example, a MOSFET.

[0021] In the description of the implementation method, an XYZ orthogonal coordinate system will be used. The direction from the drain electrode 41 towards n... - The direction of the drift region 1 is defined as the Z direction (first direction). A direction orthogonal to the Z direction is defined as the X direction (second direction). A direction orthogonal to both the X and Z directions is defined as the Y direction. Furthermore, here, the direction from the drain electrode 41 towards n... - The direction of drift region 1 is called "up," and the opposite direction is called "down." These directions are based on the drain electrode 41 and n. - The direction of the relative positional relationship of the drift region 1 is independent of the direction of gravity.

[0022] The drain electrode 41 is disposed on the lower surface of the semiconductor device 100. + The drain region 5 is disposed on the drain electrode 41 and is electrically connected to the drain electrode 41. - Type-Drift Region 1 is set at n + Above the drain region 5. - The concentration of n-type impurities in drift region 1 is higher than that of n-type impurities. + The n-type impurity concentration is low in the drain region 5. - Type-drift region 1 via n + The drain region 5 is electrically connected to the drain electrode 41.

[0023] p-type base region 2 is located at n - Above drift region 1. + The p-type source region 3 is located on a portion of the p-type base region 2. + The p-type contact region 4 is located on another portion of the p-type base region 2. + The concentration of p-type impurities in the p-type contact region 4 is higher than that in the p-type base region 2.

[0024] Conductor 10 is disposed at n via insulating part 21 -In the p-type drift region 1, the gate electrode 30 is disposed in the insulating portion 21 and is located above the conductor 10. The gate electrode 30 is disposed in the insulating portion 21 and is opposite to the p-type base region 2 in the X direction, separated by a gate insulating layer 31. The gate insulating layer 31 is part of the insulating portion 21. In the illustrated example, the gate electrode 30 and the n-type base region 2 are... - Part of type drift region 1 and n + A portion of the source pole region 3 is also relatively.

[0025] Source electrode 42 is located at n + Type source pole region 3 and p + Above type contact area 4, and with n + Type source pole region 3 and p + Type contact region 4 is electrically connected. In the illustrated example, a portion of the source electrode 42 extends downward and is disposed on a pair of n electrodes arranged along the X direction. + The p-type source regions 3 are adjacent to each other. The p-type base region 2 is connected via p... + The contact region 4 is electrically connected to the source electrode 42. The gate electrode 30 is electrically separated from the source electrode 42 through the gate insulating layer 31.

[0026] p-type base region 2, n + Type source pole region 3, p + The contact area 4, the conductor 10, and the gate electrode 30 extend along the Y direction, and multiple of them are provided in the X direction. The end of the conductor 10 in the Y direction is raised upward and electrically connected to the source electrode 42. Alternatively, the insulating portion 21 may not be provided between the conductor 10 and the gate electrode 30, and the conductor 10 may be electrically connected to the gate electrode 30.

[0027] Figure 2 It is Figure 1 A magnified sectional view of a portion of the document.

[0028] like Figure 2 As shown, the lower surface of the conductor 10 includes a first surface S1, a second surface S2, and a third surface S3. The first surface S1 is parallel to the XY plane. The second surface S2 and the third surface S3 are connected to the first surface S1 and are inclined relative to the X and Z directions, respectively. The position of the first surface S1 in the X direction is between the positions of the second surface S2 and the third surface S3 in the X direction.

[0029] More specifically, the conductor 10 includes a first conductive portion 11, a second conductive portion 12, and a third conductive portion 13. The first conductive portion 11 is located at the lower end of the conductor 10. The second conductive portion 12 is disposed above the first conductive portion 11. The third conductive portion 13 is disposed above the second conductive portion 12.

[0030] The first conductive portion 11 has a first surface S1 to a third surface S3. The width (length in the X direction) W1 of the first conductive portion 11 is longer than the width W2 of the second conductive portion 12. The width W2 of the second conductive portion 12 is shorter than the width W3 of the third conductive portion 13. The width W2 of the second conductive portion 12 may also be the same as the width W3 of the third conductive portion 13.

[0031] The first conductive portion 11 includes a first portion 11a and a second portion 11b. The first portion 11a has a first surface S1 to a third surface S3. The second portion 11b is disposed on top of the first portion 11a. The width of the first portion 11a increases towards the top. The width of the second portion 11b decreases towards the top. For example, the length of the first portion 11a in the Z direction is shorter than the length of the second portion 11b in the Z direction.

[0032] As shown in the figure, an inner cavity V may also be provided in the first conductive part 11. The inner cavity V provided in the first conductive part 11 extends in the Y direction. Alternatively, multiple inner cavities V may be distributed in the Y direction.

[0033] The operation of the semiconductor device 100 will be explained.

[0034] When a positive voltage is applied to the drain electrode 41 relative to the source electrode 42, a voltage above a threshold value is applied to the gate electrode 30. This forms a trench (inversion layer) in the p-type base region 2, and the semiconductor device 100 becomes conductive. Electrons flow from the source electrode 42 to the drain electrode 41 through the trench. If the voltage applied to the gate electrode 30 becomes lower than the threshold value, the trench in the p-type base region 2 disappears, and the semiconductor device 100 becomes cut off.

[0035] If the semiconductor device 100 switches to the off state, the positive voltage applied to the drain electrode 41 relative to the source electrode 42 increases. At this time, due to the potential difference between the drain electrode 41 and the source electrode 42, or the potential difference between the drain electrode 41 and the gate electrode 30, the depletion layer dissipates from the insulating portion 21 and the n - The interface of type drift region 1 is oriented towards n - The drift region 1 is extended. By extending this depletion layer, the withstand voltage of the semiconductor device 100 can be improved. Alternatively, the withstand voltage of the semiconductor device 100 can be increased while maintaining this voltage. - The concentration of n-type impurities in the n-type drift region 1 reduces the on-resistance of the semiconductor device 100.

[0036] An example of the material of each component of the semiconductor device 100 will be described.

[0037] n - Type 1 drift region, p-type base region 2, n + Type source pole region 3, p+ Type contact area 4 and n + The drain region 5 contains a semiconductor material. Silicon, silicon carbide, gallium nitride, or gallium arsenide can be used as the semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity.

[0038] The insulating portion 21 contains an insulating material. For example, the insulating portion 21 contains silicon oxide, silicon nitride, or silicon oxynitride. The conductor 10 and the gate electrode 30 contain conductive materials such as polysilicon. n-type or p-type impurities may also be added to the conductor 10 and the gate electrode 30. The drain electrode 41 and the source electrode 42 contain metals such as titanium, tungsten, or aluminum.

[0039] Figures 3-6 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0040] Reference Figures 3-6 An example of a method for manufacturing the semiconductor device 100 according to the embodiment will be described. First, prepare a semiconductor device containing n + The semiconductor substrate Sub with semiconductor layer 5a. (e.g., ...) Figure 3 As shown in (a), in n + On top of the semiconductor layer 5a, an n-type semiconductor is formed by epitaxial growth of silicon. - Type semiconductor layer 1a.

[0041] like Figure 3 As shown in (b), through photolithography and reactive ion etching (RIE), in n - Multiple trenches T1 are formed on the upper surface of the semiconductor layer 1a. During RIE (Reverse Etching), a mild, anisotropic etching gas is used. This allows the lower surface of the trenches T1 to be bent. On this bent surface, the {100} plane, {110} plane, etc., of silicon appear. Sulfur hexafluoride (SF6) can be used as the etching gas.

[0042] like Figure 4 As shown in (a), along n - An insulating layer 21a is formed on the upper surface of the semiconductor layer 1a and the inner surface of the trench T1. The insulating layer 21a is formed by thermal oxidation. At this time, oxidation is performed along the

[100] direction and the

[110] direction of silicon. As a result, a flat surface S1a, an inclined surface S2a, and an inclined surface S3a are formed on the lower surface of the trench T2 surrounded by the insulating layer 21a. On the flat surface S1a, the {100} surface of silicon oxide appears. On the inclined surfaces S2a and S3a, the {110} surface of silicon oxide appears. In addition, when the insulating layer 21a is formed, the width of the bottom of the trench T2 is larger than that of its upper part. As will be described later, this is believed to be due to the stress during thermal oxidation.

[0043] Furthermore, for silicon and silicon oxide, the {100} facet represents one of the mutually equivalent (100) facets, (010) facets, or (001) facets. Additionally, the {110} facet represents one of the mutually equivalent (110) facets, (011) facets, or (101) facets.

[0044] A conductive layer 10a is formed on top of the insulating layer 21a, embedded in the trench T2. The conductive layer 10a is formed by chemical vapor deposition (CVD) of a conductive material such as polycrystalline silicon. During the formation of the conductive layer 10a, an inner cavity V is formed at the bottom of the trench T2. A portion of the conductive layer 10a is removed by chemical dry etching (CDE) or the like, causing the upper surface of the conductive layer 10a to recede. Thus, multiple conductive layers 10a are formed in a discontinuous manner within multiple trenches T2. Figure 4 As shown in (b), an insulating layer 21b is formed by CVD over an insulating layer 21a and a plurality of conductive layers 10a. The conductive layers 10a have a first surface S1 that is in contact with a flat surface S1a. In addition, the conductive layers 10a have a second surface S2 and a third surface S3 that are in contact with inclined surfaces S2a and S3a, respectively.

[0045] By wet etching, the upper surfaces of insulating layer 21a and insulating layer 21b are retracted. Thus, n - The upper surface of the semiconductor layer 1a and a portion of the sidewalls of trench T1 are exposed. Through thermal oxidation, the exposed n... - An insulating layer 31a is formed on the upper surface of the semiconductor layer 1a and the sidewalls of the trench T1. The thickness of the insulating layer 31a is smaller than the thickness of the insulating layer 21a. A conductive layer 30a is formed on top of the insulating layer 31a. Figure 5 As shown in (a), the upper surface of the conductive layer 30a is retracted by CDE or wet etching, and the conductive layer 30a is formed inside each trench T1.

[0046] n between the grooves T1 - The upper part of the semiconductor layer 1a is sequentially ion implanted with p-type impurities and n-type impurities to form p-type semiconductor regions 2a and n-type semiconductor regions 2a and 2a. + Semiconductor region 3a. (e.g., [missing information]) Figure 5 As shown in (b), an insulating layer 31b is formed that covers multiple conductive layers 30a.

[0047] Forming a through insulating layer 31b, an insulating layer 31a, and n + The opening OP of the p-type semiconductor region 2a is reached from the p-type semiconductor region 3a. For example... Figure 6 As shown in (a), p-type impurities are implanted into the p-type semiconductor region 2a through the opening OP to form p-type semiconductors. + Type semiconductor region 4a.

[0048] A metal layer 42a with an embedded opening OP is formed on top of the insulating layer 31b. Then, the lower surface of the semiconductor substrate Sub is ground until n... + The semiconductor layer 5a is changed to a specified thickness. For example... Figure 6 As shown in (b), a metal layer 41a is formed on the ground lower surface. Through the above processes, a product is manufactured. Figure 1 The semiconductor device 100 shown.

[0049] Figure 6 n shown in (b) - Type semiconductor layer 1a and Figure 1 The n shown - The p-type drift region 1 corresponds to the p-type semiconductor region 2a, which corresponds to the p-type base region 2. + Type semiconductor regions 3a and n + Type source pole region 3 corresponds to. p + Type semiconductor regions 4a and p + Type contact area 4 corresponds to n. + Type semiconductor layer 5a and n + Type 5 drain region corresponds to. Conductive layer 10a corresponds to conductor 10. Insulating layer 21a and 21a correspond to insulating portion 21. Conductive layer 30a corresponds to gate electrode 30. Insulating layers 31a and 31b correspond to gate insulating layer 31. Metal layer 41a corresponds to drain electrode 41. Metal layer 42a corresponds to source electrode 42.

[0050] The advantages of the semiconductor device described in the embodiment will be explained.

[0051] Figure 7 This is a cross-sectional view showing a portion of the semiconductor device of the reference example.

[0052] exist Figure 7 In the semiconductor device 100r shown, the conductor 10r has a bottom surface BS, a side surface SS1, and a side surface SS2. The bottom surface BS is parallel to the XY plane. The side surfaces SS1 and SS2 are parallel to the YZ plane. Therefore, the angle between the bottom surface BS and the side surface SS1, and the angle between the bottom surface BS and the side surface SS2, are right angles.

[0053] When the semiconductor device 100r is in the off state, due to the potential difference between the drain electrode 41 and the source electrode 42, in n - An electric field is generated between the drift region 1 and the conductor 10r. At this time, the electric field concentrates at the corner of the lower end of the conductor 10r. The large electric field causes leakage current to flow into the insulating part 21.

[0054] Figure 8 It is a line diagram that schematically represents the characteristics of a semiconductor device.

[0055] exist Figure 8 In the diagram, the horizontal axis represents the voltage Vds of the drain electrode 41 relative to the source electrode 42. The vertical axis represents the current Id flowing between the drain electrode 41 and the source electrode 42. The solid line represents the characteristics of the semiconductor device in the reference example. The dashed line represents the characteristics of the desired semiconductor device.

[0056] In the desired semiconductor device, the current Id is relatively small before the voltage reaches the breakdown voltage Vbd. If the voltage reaches the breakdown voltage Vbd, the current Id increases sharply. On the other hand, in the semiconductor device 100r of the reference example, the current Id begins to rise at voltage V1. Voltage V1 is smaller than the breakdown voltage Vbd. This is caused by the leakage current flowing through the insulating portion 21. Furthermore, if the voltage Vds further rises to reach voltage V2, the current Id increases sharply. This is because avalanche breakdown occurs starting from the portion of the insulating portion 21 with a higher electric field strength. Figure 8 As shown, due to the leakage current flowing through the insulation portion 21, the actual withstand voltage of the semiconductor device 100 decreases from the original breakdown voltage Vbd to voltage V2.

[0057] Regarding this issue, in the semiconductor device 100 of the embodiment, the lower surface of the conductor 10 includes a first surface S1 and a second surface S2. The first surface S1 is parallel to the X direction. The second surface S2, which is connected to the first surface S1, is inclined relative to both the X and Z directions. Therefore, the angle between the first surface S1 and the second surface S2 is less than 90 degrees. As a result, compared to the semiconductor device 100r, the electric field strength near the lower end of the conductor 10 can be reduced. Consequently, leakage current flowing into the insulating portion 21 can be suppressed, and the withstand voltage of the semiconductor device 100 can be improved.

[0058] If the angle between the first surface S1 and the second surface S2 is large, the effect of reducing the electric field strength is weakened. On the other hand, if the angle is small, the width of the lower end of the conductor 10 becomes longer. As a result, it is difficult to miniaturize the conductor 10, the insulating part 21, etc., and the on-resistance of the semiconductor device 100 may increase. Therefore, this angle is preferably greater than 30 degrees and less than 60 degrees.

[0059] Furthermore, the lower surface of the conductor 10 includes a third surface S3 connected to the first surface S1. The third surface S3 is inclined with respect to both the X and Z directions. Therefore, the angle between the first surface S1 and the third surface S3 is less than 90 degrees. This allows for a further reduction in the electric field strength near the lower end of the conductor 10. Preferably, the angle between the first surface S1 and the third surface S3 is greater than 30 degrees and less than 60 degrees.

[0060] like Figure 2As shown, the conductor 10 includes a first conductive portion 11 and a second conductive portion 12. In the X direction, the length of the first conductive portion 11 is longer than the length of the second conductive portion 12. That is, the lower end of the conductor 10 is bulging. According to this structure, which is the same as the structure of the first surface S1 to the third surface S3, the electric field strength near the first conductive portion 11 can be reduced.

[0061] like Figure 1 as well as Figure 2 As shown, the first conductive portion 11 preferably includes an inner cavity V. With the inner cavity V provided, the conductor 10 is more prone to deformation due to the stress of the insulating portion 21 compared to the case where the inner cavity V is not provided. Therefore, the stress on the insulating portion 21 is reduced. The stress applied to n from the insulating portion 21... - The stress in drift region 1 is reduced. As a result, the stress-induced n-type drift can be suppressed. - The generation of crystallization defects in drift region 1.

[0062] The inner cavity V preferably extends along the Y direction. In this case, compared with the case where multiple inner cavities V are distributed along the Y direction, the volume of the inner cavity V becomes larger. As a result, the stress of the insulating portion 21 is further reduced.

[0063] Furthermore, in the semiconductor device 100, the bottom of the insulating portion 21 is located in the Z direction between the conductor 10 and n. - Between type drift region 1. The side of insulating part 21 is located in the X direction between conductor 10 and n. - Between the drift regions 1. According to the embodiment, the thickness T2a of the bottom of the insulating portion 21 can be increased, and the difference between the thickness T1a and the thickness T2a of the side portion of the insulating portion 21 can be reduced. As a result, the electric field strength of the insulating portion 21 can be reduced, and the leakage current flowing through the insulating portion 21 can be reduced.

[0064] The reason for the increased thickness T2a can be considered as follows: During the formation of the insulating portion 21, a large compressive stress is generated at the bottom of the insulating portion 21. Figure 7 In the semiconductor device 100r shown, the angle between the bottom surface BS and the side surface SS1 is approximately a right angle, making it difficult to disperse the compressive stress at the bottom of the insulating portion 21. As a result, in the semiconductor device 100r, the thickness T2b at the bottom of the insulating portion 21 decreases, while the difference between the thickness T1b and the thickness T2b at the side surface of the insulating portion 21 increases. On the other hand, in the semiconductor device 100, the second surface S2, which is connected to the first surface S1, is inclined relative to the X and Z directions. The dispersion of compressive stress is difficult to be hindered by the right angle. As a result, the compressive stress at the bottom of the insulating portion 21 decreases, while the thickness T2a increases.

[0065] In particular, for silicon oxide, the compressive stress in the

[110] direction is smaller than that in the

[100] direction. When the insulating portion 21 contains silicon oxide, a {110} surface of silicon oxide exists at the contact surface of the insulating portion 21 that contacts the second surface S2. As a result, the compressive stress in the portion of the insulating portion 21 that contacts the second surface S2 is reduced. Consequently, the compressive stress at the bottom of the insulating portion 21 is more easily dispersed, and the thickness T2a increases.

[0066] (Modified Example)

[0067] Figure 9 as well as Figure 10 This is a perspective cross-sectional view showing a portion of the semiconductor device according to the embodiment.

[0068] The structure other than the lower end of the conductor 10, the structure of the gate electrode 30, etc., are not limited to... Figure 1 The example shown can be modified appropriately. For example, it could also be as follows: Figure 9 As shown in the semiconductor device 110, a plurality of gate electrodes 30 are disposed in an insulating portion 21. In the illustrated example, the pair of gate electrodes 30 are disposed higher than the conductor 10. When viewed from the Z direction, the conductor 10 is located between the pair of gate electrodes 30 in the X direction.

[0069] Or, it can be like Figure 10 As shown in the semiconductor device 120, the upper part of the conductor 10 is positioned between a pair of gate electrodes 30 in the X direction.

[0070] In any of these methods, by making the lower surface of the conductor 10 include the first surface S1 to the third surface S3, leakage current flowing into the insulating portion 21 can be suppressed, thereby increasing the withstand voltage of the semiconductor device.

[0071] The specific shape of the lower surface of the conductor 10 is not limited to the examples described above. For example, the lower surface of the conductor 10 may also have a curved shape to replace the first surface S1, the second surface S2, and the third surface S3. In this case, the electric field strength near the lower end of the conductor 10 can also be reduced.

[0072] In the embodiments described above, the relative levels of impurity concentrations between semiconductor regions can be confirmed, for example, using a scanning electrostatic capacitance microscope (SCM). Furthermore, the carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using SCM. The impurity concentration in each semiconductor region can be determined using secondary ion mass analysis (SIMS).

[0073] In determining the crystal orientation of the insulating portion 21 in contact with the lower surface of the conductor 10, electron backscatter diffraction (EBSD) can be used. For example, EBSD can be used to analyze the area near the interface between the conductor 10 and the insulating portion 21. When the lower surface of the conductor 10 includes a first surface S1 to a third surface S3, the peak intensity corresponding to the {100} surface of silicon oxide is greater than the peak intensity corresponding to other surfaces in the analysis results. When the lower surface of the conductor 10 has a curved shape, multiple peaks appear in the analysis results, each corresponding to a different surface of silicon oxide.

[0074] The above embodiments of the present invention have been illustrated, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents. Furthermore, the foregoing embodiments can be implemented in combination with each other.

Claims

1. A semiconductor device, characterized in that, have: First electrode; A first semiconductor region of a first conductivity type is disposed on the first electrode and electrically connected to the first electrode. A second semiconductor region of a second conductivity type is disposed on the first semiconductor region; A third semiconductor region of a first conductivity type is disposed on a portion of the second semiconductor region; A conductor disposed in the first semiconductor region with an insulating portion between it and the conductor. The lower surface of the conductor includes a first surface and a second surface. The first surface is parallel to a second direction orthogonal to a first direction from the first electrode toward the first semiconductor region. The second surface is connected to the first surface and is inclined relative to both the first and second directions. The conductor includes a first conductive portion having the first surface and the second surface, and a second conductive portion disposed on the first conductive portion. In the second direction, the length of the first conductive portion is longer than the length of the second conductive portion. The first conductive portion includes: a first part having the first surface and the second surface, and the length of the first part in the second direction increases upwards; and a second part disposed on the first part, and the length of the second part in the second direction decreases upwards. A gate electrode is disposed in the insulating portion and is opposite to the second semiconductor region in the second direction, separated by a gate insulating layer; as well as The second electrode is disposed on the second semiconductor region and the third semiconductor region, and is electrically connected to the second semiconductor region and the third semiconductor region.

2. The semiconductor device according to claim 1, characterized in that, The conductor further includes a third conductive portion disposed on the second conductive portion. In the second direction, the length of the second conductive part is shorter than the length of the third conductive part.

3. The semiconductor device according to claim 1 or 2, characterized in that, The insulating part has a {100} surface of silicon oxide on the surface that contacts the first surface. The surface of the insulating part that is in contact with the second surface has a {110} surface of silicon oxide.

4. A semiconductor device, characterized in that, have: First electrode; A first semiconductor region of a first conductivity type is disposed on the first electrode and electrically connected to the first electrode. A second semiconductor region of a second conductivity type is disposed on the first semiconductor region; A third semiconductor region of a first conductivity type is disposed on a portion of the second semiconductor region; A conductor disposed in the first semiconductor region via an insulating portion, the lower surface of the conductor including a first surface and a second surface, the first surface being parallel to a second direction orthogonal to a first direction from the first electrode toward the first semiconductor region, the second surface being connected to the first surface and inclined relative to the first direction and the second direction, a silicon oxide {100} surface being present on the surface of the insulating portion that is in contact with the first surface, and a silicon oxide {110} surface being present on the surface of the insulating portion that is in contact with the second surface; A gate electrode is disposed in the insulating portion and is opposite to the second semiconductor region in the second direction, separated by a gate insulating layer; as well as The second electrode is disposed on the second semiconductor region and the third semiconductor region, and is electrically connected to the second semiconductor region and the third semiconductor region.

5. The semiconductor device according to claim 4, characterized in that, The conductor includes a first conductive portion having a first surface and a second surface, and a second conductive portion disposed on the first conductive portion. In the second direction, the length of the first conductive part is longer than the length of the second conductive part.

6. The semiconductor device according to claim 5, characterized in that, The conductor further includes a third conductive portion disposed on the second conductive portion. In the second direction, the length of the second conductive part is shorter than the length of the third conductive part.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, An inner cavity is provided at the lower end of the conductor.

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