Silicon-based solar cell and method of making the same
By forming a tunneling oxide layer and an amorphous silicon layer in silicon-based solar cells, and combining boron diffusion and laser ablation processes, the front recombination problem of interdigitated back-contact solar cells was solved, improving conversion efficiency and open-circuit voltage, and simplifying the process flow.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG AIKO SOLAR ENERGY TECH CO LTD
- Filing Date
- 2023-06-01
- Publication Date
- 2026-07-31
AI Technical Summary
Existing interdigitated back contact solar cells have a high front recombination rate, and when undoped, the disorder of electrons and holes inside the cell leads to a high bulk recombination rate. Conventional boron diffusion surface treatment cannot effectively remove the dead zone of the boron-rich layer.
The method involves forming a tunneling oxide layer and an amorphous silicon layer on the front and back sides of the silicon wafer, and forming a P+ polycrystalline silicon layer through a boron diffusion process. Combined with laser ablation and alkaline polishing processes, this reduces surface recombination and forms a floating junction to lower the electron barrier height and avoid the formation of dead zones in the boron-rich layer.
It effectively reduces surface recombination, improves the conversion efficiency of solar cells, increases open-circuit voltage, simplifies the process, and avoids the formation of dead zones in the boron-rich layer.
Smart Images
Figure CN116646424B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solar cell technology, and in particular to a silicon-based solar cell and its fabrication method. Background Technology
[0002] Interdigitated back contact (IBC) solar cells offer advantages such as high conversion efficiency, unobstructed front side, attractive appearance, and simple and diverse module encapsulation. Their front side typically utilizes Al₂O₃. x Layers and SiN x The layer is passivated, but the positive surface recombination is still high. In addition, the disorder of electrons and holes inside the cell when there is no doping leads to high bulk recombination. Although the formation of the front surface field FSF by phosphorus doping can reduce surface recombination, it is not conducive to alumina coating (the charge polarity is opposite). Conventional B diffusion surface BSG and boron-rich layer cannot be effectively removed. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a method for preparing silicon-based solar cells, which has a simple process, avoids the generation of dead zones in boron-rich layers, reduces positive surface recombination, and improves the conversion efficiency of solar cells.
[0004] Another technical problem that this invention aims to solve is to provide a silicon-based solar cell with high conversion efficiency.
[0005] To address the aforementioned technical problems, this invention provides a method for fabricating a silicon-based solar cell, comprising the following steps:
[0006] (1) Provide silicon wafers and texturize them to form a textured surface;
[0007] (2) Polish the back side of the texturized silicon wafer;
[0008] (3) A first tunneling oxide layer and a first amorphous silicon layer are formed on the front and back sides of the silicon wafer;
[0009] (4) The first amorphous silicon layer on the front and back sides of the silicon wafer is converted into a P+ polycrystalline silicon layer by B diffusion process, and a BSG layer is formed on it; in addition, B diffusion is performed on the front side of the silicon wafer to form a P++ silicon layer on the textured surface.
[0010] (5) The preset area on the back of the silicon wafer is etched to form an N-type region, and the unetched area is a P-type region;
[0011] (6) A second tunneling oxide layer and a second amorphous silicon layer are formed on the front and back sides of the silicon wafer obtained in step (5);
[0012] (7) The second amorphous silicon layer on the front and back sides of the silicon wafer is converted into an N+ polycrystalline silicon layer by the P diffusion process, and a PSG layer is formed on it; wherein the temperature of P diffusion is 50-100℃ lower than the temperature of B diffusion.
[0013] (8) Laser ablation of the PSG layer of a preset width on the surface of the P-type region and between the P-type and N-type regions;
[0014] (9) Remove the second tunneling oxide layer and N+ polysilicon layer exposed on the back side of the silicon wafer in step (8) to achieve electrical isolation between the P-type region and the N-type region;
[0015] (10) Remove the PSG layer, N+ polysilicon layer, second tunneling oxide layer, BSG layer, P+ polysilicon layer and first tunneling oxide layer on the front side of the silicon wafer, and retain the P++ silicon layer;
[0016] (11) AlO is formed on the front and back sides of the silicon wafer obtained in step (10). x layer;
[0017] (12) Form SiN on the front and back sides of the silicon wafer obtained in step (11). x layer;
[0018] (13) An N electrode is formed in the N-type region and a P electrode is formed in the P-type region.
[0019] As an improvement to the above technical solution, step (1) includes:
[0020] (1.1) Provide silicon wafers and texturing them to form a textured surface;
[0021] (1.2) The texturized silicon wafer is treated with hydrogen peroxide or ozone to make its surface hydrophilic.
[0022] As an improvement to the above technical solution, in step (3), the first tunneling oxide layer and the first amorphous silicon layer are prepared by LPCVD, and the deposition temperature of the first amorphous silicon layer is 550-600℃.
[0023] In step (6), the second tunneling oxide layer and the second amorphous silicon layer are prepared by LPCVD, and the deposition temperature of the second amorphous silicon layer is 550-600℃.
[0024] As an improvement to the above technical solution, in step (4), the diffusion temperature of B is 850-1000℃;
[0025] In step (7), the temperature for P diffusion is 800℃~900℃.
[0026] As an improvement to the above technical solution, step (6) includes:
[0027] (6.1) The silicon wafer obtained in step (5) is subjected to alkaline polishing to remove laser damage in the N-type region; at the same time, the BSG layer protects the first tunneling oxide layer and the P+ polysilicon layer on the P-type region from damage.
[0028] (6.2) A second tunneling oxide layer and a second amorphous silicon layer are formed on the front and back sides of the silicon wafer obtained in step (6.1).
[0029] As an improvement to the above technical solution, in step (9), alkaline polishing is used to remove the second tunneling oxide layer and the N+ polysilicon layer.
[0030] As an improvement to the above technical solution, in step (11), ALD is used to form the AlO. x The layer has a thickness of 1–20 nm;
[0031] In step (12), the SiN is formed using PECVD. x The layer has a thickness of 60–110 nm.
[0032] As an improvement to the above technical solution, the doping concentration of the P++ silicon layer is 5E18~5E19 cm⁻¹. -3 The P++ silicon layer forms a floating junction with the silicon wafer, and the junction depth is 0.1 to 1 μm.
[0033] As an improvement to the above technical solution, the thickness of the N+ polycrystalline silicon layer is 40–300 nm, and the doping concentration is 3E19–1E21 cm⁻¹. -3 ;
[0034] The thickness of the P+ polycrystalline silicon layer is 40–300 nm, and the doping concentration is 5E19–1E21 cm⁻¹. -3 .
[0035] Accordingly, the present invention also discloses a silicon-based solar cell, which includes a silicon wafer, and a P++ silicon layer and an AlO layer sequentially disposed on the front side of the silicon wafer. x Layers and SiN x layer;
[0036] The back side of the silicon wafer has intersecting N-type and P-type regions. The N-type region includes a second tunneling oxide layer, an N+ polysilicon layer, and an AlO layer arranged sequentially. x Layer, SiN x The P-type region includes a first tunneling oxide layer, a P+ polysilicon layer, and an AlO layer, which are electrically connected to the N+ polysilicon layer. x Layer, SiN x The layer and the P electrode, wherein the P electrode is electrically connected to the P+ polycrystalline silicon layer.
[0037] Implementing this invention has the following beneficial effects:
[0038] The method for fabricating silicon-based solar cells of the present invention involves simultaneously forming a first tunneling passivation layer and a first amorphous silicon layer on both the front and back sides of a silicon wafer, followed by the formation of a P+ polycrystalline silicon layer through boron diffusion. During boron diffusion, boron diffuses into the silicon substrate from the front side, forming a P++ silicon layer, thereby effectively reducing surface recombination. Furthermore, the P++ silicon layer forms a floating PN junction (FFE) with the silicon substrate. Due to the built-in electric field effect of the PN junction, the electron barrier height on the N-region side of the P++ / N front surface is reduced, and the pumping effect unique to FFE is formed, thereby reducing bulk recombination and increasing the open-circuit voltage of the cell. Moreover, based on this fabrication method, a separate boron diffusion process is not required, reducing the dead zone of the boron-rich layer that occurs during boron diffusion, further reducing surface recombination, and further improving the open-circuit voltage of the cell. Attached Figure Description
[0039] Figure 1 This is a flowchart of the method for preparing silicon-based solar cells according to the present invention;
[0040] Figure 2 This is a schematic diagram of the silicon wafer structure after step S3;
[0041] Figure 3 This is a schematic diagram of the silicon wafer structure after step S4;
[0042] Figure 4 This is a schematic diagram of the silicon wafer structure after step S5;
[0043] Figure 5 This is a schematic diagram of the silicon wafer structure after step S6;
[0044] Figure 6 This is a schematic diagram of the silicon wafer structure after step S7;
[0045] Figure 7 This is a schematic diagram of the silicon wafer structure after step S9;
[0046] Figure 8 This is a schematic diagram of the silicon wafer structure after step S10;
[0047] Figure 9 This is a schematic diagram of the silicon wafer structure after step S12;
[0048] Figure 10 This is a schematic diagram of the structure of a silicon-based solar cell in one embodiment of the present invention. Detailed Implementation
[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It is hereby declared that the directional terms such as up, down, left, right, front, back, inside, and outside used in this text are based solely on the accompanying drawings and are not intended to specifically limit the invention.
[0050] See Figure 1 This invention provides a method for preparing a silicon-based solar cell, comprising the following steps:
[0051] S1: Provide silicon wafer 1 and texturize it to form a textured surface;
[0052] Specifically, silicon wafer 1 is an N-type silicon wafer with a thickness of 50 to 250 μm, exemplarily 60 μm, 80 μm, 100 μm, 150 μm, 180 μm, 220 μm or 240 μm, but not limited to these.
[0053] Specifically, texturing is a common process in this field. By texturing, a pyramid light-trapping structure can be formed on the surface of the silicon wafer, thereby improving the light conversion efficiency.
[0054] Preferably, in one embodiment of the present invention, after texturing is completed, the silicon wafer 1 is treated with hydrogen peroxide or ozone-containing deionized water to make its surface hydrophilic.
[0055] S2: Polish the back side of the texturized silicon wafer 1;
[0056] Specifically, the back of the silicon wafer is polished using acid polishing or alkaline polishing processes to create a surface with a reflectivity of 20-40%. Acid polishing can be performed using a mixed solution of hydrofluoric acid, nitric acid, and sulfuric acid, or a mixed solution of hydrofluoric acid and nitric acid, but is not limited to these. Alkaline polishing can be performed using NaOH solution or KOH solution, but is not limited to these.
[0057] S3: A first tunneling oxide layer 2 and a first amorphous silicon layer 3a are formed on the front and back sides of silicon wafer 1;
[0058] Specifically, the first tunneling oxide layer 2 can be prepared by thermal nitric acid oxidation, ultraviolet ozone oxidation, PECVD-N2O method, ozone oxidation method, or LPCVD method, but is not limited thereto. Preferably, in one embodiment of the present invention, the first tunneling oxide layer 2 is prepared by LPCVD.
[0059] Specifically, the first amorphous silicon layer 3a can be formed by PECVD or LPCVD, but is not limited thereto. Preferably, in one embodiment of the present invention, the first amorphous silicon layer 3a is formed by LPCVD at a deposition temperature of 550–600°C, exemplary values being 560°C, 570°C, 580°C, or 590°C, but not limited thereto. (See reference...) Figure 2 The thickness of the first amorphous silicon layer 3a is 40 to 300 nm, and exemplary thicknesses are 55 nm, 80 nm, 120 nm, 180 nm, 230 nm, 250 nm or 280 nm, but not limited thereto.
[0060] S4: The first amorphous silicon layer 3a is transformed into a P+ polycrystalline silicon layer 3 by B diffusion process, and a BSG layer 3b is formed on it; B diffusion is carried out on the front side of silicon wafer 1 to form a P++ silicon layer 11.
[0061] The diffusion temperature for B is 850–1000°C, with examples of 880°C, 920°C, 950°C, or 970°C, but not limited to these. Through the B diffusion process, the first amorphous silicon layer 3a on the front and back sides of silicon wafer 1 can be transformed into a P+ polycrystalline silicon layer 3, and a BSG layer 3b is formed on the P+ polycrystalline silicon layer 3. Furthermore, based on the B diffusion process, the B diffusion on the front side of silicon wafer 1 expands inward, forming a P++ silicon layer 11 on the textured surface (see reference). Figure 3 Based on the above process, a separate boron diffusion process is not required, which reduces the dead zone of the boron-rich layer that occurs during boron diffusion, reduces positive surface recombination, and further improves the open-circuit voltage of the solar cell.
[0062] Specifically, the doping concentration of the P+ polysilicon layer 3 is 5E19~1E21cm. -3 An example is 7E19cm -3 9E19cm -3 2E20cm -3 4E20cm -3 6E20cm -3 Or 8E20cm -3 However, it is not limited to this.
[0063] Specifically, the doping concentration of the P++ silicon layer 11 is 5E18~5E19 cm⁻¹. -3 An example is 7E18cm -3 9E18cm -3 1E19cm -3 2E19cm -3 Or 4E19cm -3 However, it is not limited to this. The P++ silicon layer 11 forms a floating junction (FFE) with the silicon wafer 1 (N-type silicon wafer), and the junction depth is 0.1 to 1 μm, exemplarily 0.3 μm, 0.5 μm, 0.7 μm or 0.9 μm, but not limited to this.
[0064] S5: Etch a preset area on the back of the silicon wafer to form an N-type region;
[0065] In this process, photolithography or laser ablation etching can be used to form N-type regions on the first tunneling oxide layer 2 and P+ polysilicon layer 3 on the back side of the silicon wafer, while the unetched areas are P-type regions; P-type and N-type regions are alternately arranged (see reference). Figure 4 ).
[0066] Preferably, in one embodiment of the present invention, the first tunneling oxide layer 2 and the P+ polysilicon layer 3 on the back side of the silicon wafer are ablated by laser, and the silicon wafer is partially ablated to form an N-type region.
[0067] S6: A second tunneling oxide layer 4 and a second amorphous silicon layer 5a are formed on the front and back sides of the silicon wafer obtained in step S5;
[0068] Specifically, the second tunneling oxide layer 4 can be prepared by thermal nitric acid oxidation, ultraviolet ozone oxidation, PECVD-N2O method, ozone oxidation method, or LPCVD method, but is not limited thereto. Preferably, in one embodiment of the present invention, the second tunneling oxide layer 4 is prepared by LPCVD.
[0069] Specifically, the second amorphous silicon layer 5a can be formed by PECVD or LPCVD (see reference). Figure 5 However, this is not the only possibility. Preferably, in one embodiment of the present invention, the second amorphous silicon layer 5a is formed by LPCVD at a deposition temperature of 550–600°C, exemplarily 560°C, 570°C, 580°C, or 590°C, but not limited thereto. The thickness of the second amorphous silicon layer 5a is 40–300 nm, exemplarily 55 nm, 80 nm, 120 nm, 180 nm, 230 nm, 250 nm, or 280 nm, but not limited thereto.
[0070] Preferably, in one embodiment of the present invention, step S6 includes:
[0071] S61: The silicon wafer obtained in step S5 is subjected to alkaline polishing to remove laser damage in the N-type region; at the same time, the BSG layer protects the first tunneling oxide layer 2 and the P+ polysilicon layer 3 on the P-type region from damage.
[0072] Specifically, KOH solution or NaOH solution can be used for alkaline polishing, but it is not limited to these.
[0073] S62: A second tunneling oxide layer 4 and a second amorphous silicon layer 5a are formed on the front and back sides of the silicon wafer obtained in step S61.
[0074] S7: The second amorphous silicon layer 5a is converted into an N+ polycrystalline silicon layer 5 using a P diffusion process, and a PSG layer 5b is formed on it.
[0075] The P-diffusion temperature is 50–100°C lower than the B-diffusion temperature. Based on this control, the first amorphous silicon layer 2 and the P+ polycrystalline silicon layer 3 are essentially undamaged. Specifically, the P-diffusion temperature is 800–900°C, with exemplary values of 820°C, 840°C, 860°C, 880°C, or 890°C, but not limited to these. Through the P-diffusion process, the second amorphous silicon layer 5a on both the front and back sides of the silicon wafer can be converted into an N+ polycrystalline silicon layer 5, and a PSG layer 5b is formed on the N+ polycrystalline silicon layer 5 (see figure). Figure 6 ).
[0076] Specifically, the doping concentration of the N+ polysilicon layer 5 is 3E19~1E21cm. -3 An example is 5E19cm -3 7E19cm -3 9E19cm -3 2E20cm -3 4E20cm -3 6E20cm -3 Or 8E20cm -3 However, it is not limited to this.
[0077] S8: Laser ablation of the PSG layer of a preset width on the surface of the P-type region and between the P-type and N-type regions;
[0078] Specifically, removing the PSG layer 5b on the surface of the P-type region by laser ablation provides a good foundation for the subsequent removal of the second tunneling oxide layer 4 and the N+ polysilicon layer 5 on the P-type region. Removing the PSG layer 5b of a predetermined width between the P-type and N-type regions provides a good foundation for the electrical isolation between the P-type and N-type regions.
[0079] Specifically, the preset width is 100 to 3000 nm, with examples being 300 nm, 800 nm, 1300 nm, 1700 nm, 2200 nm, 2600 nm or 2800 nm, but not limited to these.
[0080] S9: Remove the second tunneling oxide layer and N+ polysilicon layer exposed on the back side of the silicon wafer;
[0081] The second tunneling oxide layer 4 and the N+ polysilicon layer 5 can be removed by laser ablation and alkaline polishing, but are not limited thereto. Preferably, in one embodiment of the present invention, the second tunneling oxide layer 4 and the N+ polysilicon layer 5 are removed by alkaline polishing. Specifically, the alkaline polishing process conditions are polishing with a KOH solution containing TMAH (2-5 wt%) at 50-70°C for 1.5-3 minutes.
[0082] It should be noted that the first tunneling oxide layer 2 and the P+ polysilicon layer 3 in the P-type region are not removed during alkaline polishing due to the protection of the BSG layer 3b. Correspondingly, a portion of the second tunneling oxide layer 4 and the N+ polysilicon layer 5 in the N-type region are not removed during alkaline polishing due to the protection of the PSG layer 5b (see [reference]). Figure 7 ).
[0083] S10: Remove the PSG layer, N+ polysilicon layer, second tunneling oxide layer, BSG layer, P+ polysilicon layer and first tunneling oxide layer from the front side of the silicon wafer, and retain the P++ silicon layer.
[0084] Specifically, the PSG layer 5b, N+ polysilicon layer 5, second tunneling oxide layer 4, BSG layer 3b, P+ polysilicon layer 3 and first tunneling oxide layer 2 on the front side of silicon wafer 1 can be removed by laser ablation and alkaline polishing processes, but not limited to these.
[0085] Preferably, in one embodiment of the present invention, the PSG layer 5b, N+ polysilicon layer 5, second tunneling oxide layer 4, BSG layer 3b, P+ polysilicon layer 3, and first tunneling oxide layer 2 on the front side of silicon wafer 1 are removed by a chain polishing process. Specifically, this includes: firstly, polishing with a mixed solution of HF, HNO3, and H2O (mass ratio of 1:1 to 2:1 to 2) at 50 to 80°C for 1 to 3 minutes to remove the PSG layer 5b; then, polishing with a KOH solution containing TMAH (2 to 5 wt%) at 50 to 70°C for 1.5 to 3 minutes to remove the N+ polysilicon layer 5 and the second tunneling oxide layer. Next, a mixed solution of HF, HNO3, and H2O (mass ratio of 1:1 to 2:1 to 2) is used for polishing at 50 to 80°C for 1 to 3 minutes to remove the BSG layer 5b. Then, a KOH solution containing TMAH (2 to 5 wt%) is used for polishing at 50 to 70°C for 1.5 to 3 minutes to remove the P+ polycrystalline silicon layer 3 and the first tunneling oxide layer 2 (see reference). Figure 8 ).
[0086] S11: AlO is formed on the front and back sides of the silicon wafer obtained in step S10. x Layer 6;
[0087] Specifically, AlO2 can be formed using PECVD, ALD, and MOCVD methods. x Layer 6, but not limited thereto. Preferably, in one embodiment of the invention, AlO is formed using ALD. x Layer 6 has a thickness of 1 to 20 nm, exemplarily 4 nm, 8 nm, 10 nm, 13 nm, 16 nm or 18 nm, but is not limited thereto.
[0088] S12: SiN is formed on the front and back sides of the silicon wafer obtained in step S11. x Layer 7;
[0089] Specifically, SiN can be formed using PECVD, ALD, and MOCVD methods. x Layer 7 (refer to) Figure 9 However, this is not the only possibility. Preferably, in one embodiment of the invention, ALD is used to form SiN. x Layer 7 has a thickness of 60–110 nm, exemplarily 66 nm, 72 nm, 80 nm, 88 nm, 96 nm, 103 nm, or 108 nm, but is not limited thereto.
[0090] S13: Form N electrode 8 in N-type region and P electrode 9 in P-type region;
[0091] Specifically, the N electrode 8 can be an Al electrode, but is not limited to this. The P electrode 9 can be an Ag electrode, a Cu electrode, a Ni electrode, or a composite of several metals, but is not limited to this.
[0092] Specifically, N-electrodes or P-electrodes can be formed using electroplating or screen printing processes, but are not limited to these.
[0093] Specifically, in one embodiment of the present invention, a burn-through slurry can be used to burn through SiN. x Layer 7 and AlO x Layer 6 is used to electrically connect the N-electrode 8 and the N+ polysilicon layer 5, and the P-electrode 9 and the P+ polysilicon layer 3. In another embodiment of the invention, laser can be used to remove SiN from certain areas. x Layer 7 and AlO x Layer 6 is formed, followed by N-electrode 8 and P-electrode 9.
[0094] Accordingly, see Figure 9 The present invention also provides a silicon-based solar cell, which is prepared by the above-described preparation method, comprising a silicon wafer 1, and a P++ silicon layer 11 and an AlO layer sequentially disposed on the front side of the silicon wafer 1. x Layer 6 and SiN x Layer 7;
[0095] The back side of silicon wafer 1 has intersecting N-type and P-type regions. The N-type region includes a second tunneling oxide layer 4, an N+ polysilicon layer 5, and an AlO layer arranged sequentially. x Layer 6, SiN x Layer 7 and N electrode 8, N electrode 8 is electrically connected to N+ polysilicon layer 5; P-type region includes a first tunneling oxide layer 2, P+ polysilicon layer 3, and AlO2 layer sequentially disposed thereon. x Layer 6, SiN x Layer 7 and P electrode 9, P electrode 9 is electrically connected to P+ polycrystalline silicon layer 3.
[0096] Based on the fabrication process of this invention, the conversion efficiency of silicon-based solar cells can reach 23.7-24.1%, while that of traditional PERC cells is only 21-22%.
[0097] The above description is merely a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.
Claims
1. A method for fabricating a silicon-based solar cell, characterized in that, Includes the following steps: (1) Provide silicon wafers and texturize them to form a textured surface; (2) Polish the back side of the texturized silicon wafer; (3) A first tunneling oxide layer and a first amorphous silicon layer are formed on the front and back sides of the silicon wafer; (4) The first amorphous silicon layer on the front and back sides of the silicon wafer is converted into a P+ polycrystalline silicon layer by using the B diffusion process, and a BSG layer is formed on it. In addition, the front side B of the silicon wafer is expanded inward to form a P++ silicon layer on the textured surface. (5) The preset area on the back of the silicon wafer is etched to form an N-type region, and the unetched area is a P-type region; (6) A second tunneling oxide layer and a second amorphous silicon layer are formed on the front and back sides of the silicon wafer obtained in step (5); (7) The second amorphous silicon layer on the front and back sides of the silicon wafer is converted into an N+ polycrystalline silicon layer by the P diffusion process, and a PSG layer is formed on it; wherein the temperature of P diffusion is 50-100℃ lower than the temperature of B diffusion. (8) Laser ablation of the PSG layer of a preset width on the surface of the P-type region and between the P-type and N-type regions; (9) Remove the second tunneling oxide layer and N+ polysilicon layer exposed on the back side of the silicon wafer in step (8) to achieve electrical isolation between the P-type region and the N-type region; (10) Remove the PSG layer, N+ polysilicon layer, second tunneling oxide layer, BSG layer, P+ polysilicon layer and first tunneling oxide layer on the front side of the silicon wafer, and retain the P++ silicon layer. (11) forming AlOx layers on the front and back surfaces of the silicon wafer obtained in step (10) x layer; (12) Form SiN on the front and back sides of the silicon wafer obtained in step (11). x layer; (13) An N electrode is formed in the N-type region and a P electrode is formed in the P-type region.
2. The method for preparing a silicon-based solar cell as described in claim 1, characterized in that, Step (1) includes: (1.1) Provide silicon wafers and texturing them to form a textured surface; (1.2) The texturized silicon wafer is treated with hydrogen peroxide or ozone to make its surface hydrophilic.
3. The method for preparing a silicon-based solar cell as described in claim 1, characterized in that, In step (3), the first tunneling oxide layer and the first amorphous silicon layer are prepared by LPCVD, and the deposition temperature of the first amorphous silicon layer is 550-600℃. In step (6), the second tunneling oxide layer and the second amorphous silicon layer are prepared by LPCVD, and the deposition temperature of the second amorphous silicon layer is 550-600℃.
4. The method for preparing a silicon-based solar cell as described in claim 1, characterized in that, In step (4), the diffusion temperature of B is 850–1000℃; In step (7), the temperature for P diffusion is 800℃~900℃.
5. The method for preparing a silicon-based solar cell as described in claim 1, characterized in that, Step (6) includes: (6.1) The silicon wafer obtained in step (5) is subjected to alkaline polishing to remove laser damage in the N-type region; at the same time, the BSG layer protects the first tunneling oxide layer and the P+ polysilicon layer on the P-type region from damage. (6.2) A second tunneling oxide layer and a second amorphous silicon layer are formed on the front and back sides of the silicon wafer obtained in step (6.1).
6. The method for preparing a silicon-based solar cell as described in claim 1, characterized in that, In step (9), alkaline polishing is used to remove the second tunneling oxide layer and the N+ polysilicon layer.
7. The method for preparing a silicon-based solar cell as described in claim 1, characterized in that, In step (11), the AlO is formed using ALD. x The layer has a thickness of 1–20 nm; In step (12), the SiN is formed using PECVD. x The layer has a thickness of 60–110 nm.
8. The method for preparing a silicon-based solar cell as described in claim 1, characterized in that, The doping concentration of the P++ silicon layer is 5E18~5E19 cm⁻¹. -3 The P++ silicon layer forms a floating junction with the silicon wafer, and the junction depth is 0.1 to 1 μm.
9. The method for preparing a silicon-based solar cell as described in claim 1, characterized in that, The thickness of the N+ polycrystalline silicon layer is 40–300 nm, and the doping concentration is 3E19–1E21 cm⁻¹. -3 ; The thickness of the P+ polycrystalline silicon layer is 40–300 nm, and the doping concentration is 5E19–1E21 cm⁻¹. -3 .
10. A silicon-based solar cell, characterized in that, Including a silicon wafer, with a P++ silicon layer and an AlO layer sequentially disposed on the front side of the silicon wafer. x Layers and SiN x layer; The back side of the silicon wafer has intersecting N-type and P-type regions. The N-type region includes a second tunneling oxide layer, an N+ polysilicon layer, and an AlO layer arranged sequentially. x Layer, SiN x The P-type region includes a first tunneling oxide layer, a P+ polysilicon layer, and an AlO layer, which are electrically connected to the N+ polysilicon layer. x Layer, SiN x The layer and the P electrode, wherein the P electrode is electrically connected to the P+ polycrystalline silicon layer.