Class-c voltage controlled oscillator applied to low-jitter sub-sampling phase-locked loop

Abstract

The application discloses a class-C voltage-controlled oscillator applied to a low-jitter sub-sampling phase-locked loop, relates to the integrated circuit technical field and comprises a power supply circuit, an energy storage circuit, a PMOS biasing circuit, an NMOS biasing circuit, a first RC network, a second RC network, a complementary PMOS circuit, a complementary NMOS circuit, a switched capacitor array and a differential oscillation tank. The NMOS biasing circuit is used for providing a common-mode biasing level to the complementary NMOS circuit, the first RC network is used for providing a differential-mode biasing level to the complementary NMOS circuit, and the complementary NMOS circuit is used for transmitting a current pulse to the differential oscillation tank. The PMOS biasing circuit is used for providing a common-mode biasing level to the complementary PMOS circuit, the second RC network is used for providing a differential-mode biasing level to the complementary PMOS circuit, and the complementary PMOS circuit is used for transmitting a current pulse to the differential oscillation tank. The switched capacitor array is used for adjusting the capacitance accessed to the differential oscillation tank to control the output signal of the differential oscillation tank. The application has the advantages of low power consumption, low phase noise, large output swing, wide tuning range and the like.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a Class C voltage-controlled oscillator applied to a low-jitter subsampling phase-locked loop. Background Technology

[0002] With the continuous development and advancement of communication technology, high-performance systems and applications such as wireless communication, wired communication, and high-speed data conversion require efficient synthesis of low-jitter reference frequencies and clocks. Phase-Locked Loops (PLLs), as integrated circuit components capable of generating high-precision clock signals, have wide applications in the integrated circuit field. Subsampling PLLs, by employing subsampling phase detectors and eliminating the frequency divider structure, achieve higher loop gain and lower power consumption, demonstrating a better trade-off between power consumption and jitter, thus becoming a new frontier in PLL research.

[0003] The voltage-controlled oscillator (VCO) is the core module in a phase-locked loop (PLL). Its main function is to provide the PLL with an output oscillation signal after multiplying the reference clock. It can be said that the performance of the VCO directly determines the overall performance of the PLL. The power consumption of the VCO usually accounts for 80% of the PLL's power consumption, which determines the overall power consumption of the chip. Moreover, its phase noise becomes the main noise contributor to the overall circuit after passing through the PLL. Lower VCO phase noise directly leads to lower clock jitter. For subsampling PLLs, due to their high loop gain, they often need to be paired with a lower VCO phase noise to better highlight the suppression effect.

[0004] Therefore, in order to obtain a low-power, low-jitter phase-locked loop, it is essential to design a voltage-controlled oscillator with lower power consumption and lower phase noise. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a Class C voltage-controlled oscillator with low power consumption, low phase noise, large output swing, and wide tuning range for use in low-jitter subsampling phase-locked loops.

[0006] To address the aforementioned technical problems, this invention provides a Class C voltage-controlled oscillator (VCO) for a low-jitter subsampling phase-locked loop (PLL), comprising a power supply circuit, an energy storage circuit, a PMOS bias circuit, an NMOS bias circuit, a first RC network, a second RC network, a complementary PMOS circuit, a complementary NMOS circuit, a switched capacitor array, and a differential oscillation slot. The power supply circuit is connected to the complementary NMOS circuit to provide operating current. The energy storage circuit is connected to the complementary NMOS circuit to maintain a constant voltage at the source node of the complementary NMOS circuit. The complementary NMOS circuit is connected to the NMOS bias circuit, the first RC network, and the differential oscillation slot, respectively. The NMOS bias circuit provides power to the complementary NMOS circuit. A common-mode bias level is provided. The first RC network is used to provide a differential-mode bias level to the complementary NMOS circuit, which is used to transmit current pulses to the differential oscillator slot. The complementary PMOS circuit is connected to the PMOS bias circuit, the second RC network, and the differential oscillator slot. The PMOS bias circuit is used to provide a common-mode bias level to the complementary PMOS circuit, and the second RC network is used to provide a differential-mode bias level to the complementary PMOS circuit. The complementary PMOS circuit is used to transmit current pulses to the differential oscillator slot. The switched capacitor array is connected to the differential oscillator slot and is used to adjust the capacitor connected to the differential oscillator slot to control the output signal of the differential oscillator slot.

[0007] As an improvement to the above scheme, the gate node of the complementary NMOS circuit is connected to the NMOS bias circuit and the first RC network respectively, and the drain node of the complementary NMOS circuit is connected to the differential oscillation tank and the drain node of the complementary PMOS circuit respectively; the gate node of the complementary PMOS circuit is connected to the PMOS bias circuit and the second RC network respectively, and the drain node of the complementary PMOS circuit is connected to the differential oscillation tank.

[0008] As an improvement to the above scheme, the common-mode bias level provided by the NMOS bias circuit to the complementary NMOS circuit is lower than the common-mode voltage of the differential oscillator; the common-mode bias level provided by the PMOS bias circuit to the complementary PMOS circuit is higher than the common-mode voltage of the differential oscillator.

[0009] As an improvement to the above scheme, the zero-peak differential voltage swing across the differential oscillation slot is less than or equal to the voltage threshold of the complementary NMOS circuit and the complementary PMOS circuit.

[0010] As an improvement to the above scheme, the NMOS transistor is turned on when the gate voltage of the NMOS transistor in the complementary NMOS circuit is equal to the threshold voltage of the NMOS transistor in the complementary NMOS circuit.

[0011] As an improvement to the above scheme, under steady-state conditions, the two ends of the differential oscillation slot output a constant sine wave.

[0012] As an improvement to the above scheme, under steady-state conditions, the current conduction angle and current pulse shape of the complementary NMOS circuit are the same as those of the complementary PMOS circuit.

[0013] As an improvement to the above scheme, the output voltage, current conduction angle, and current pulse shape of the complementary NMOS circuit are related to the ratio of the width to the length of the NMOS transistor in the complementary NMOS circuit; the output voltage, current conduction angle, and current pulse shape of the complementary PMOS circuit are related to the ratio of the width to the length of the PMOS transistor in the complementary PMOS circuit.

[0014] As an improvement to the above scheme, the capacitance value connected to the differential oscillation slot is inversely proportional to the oscillation frequency of the output signal of the differential oscillation slot.

[0015] As an improvement to the above scheme, the energy storage circuit is located between the source node and the ground node of the complementary NMOS circuit, so as to keep the voltage of the source node of the complementary NMOS circuit constant.

[0016] To address the trade-offs among various performance parameters of voltage-controlled oscillators (VCOs) in low-jitter subsampling phase-locked loops, such as phase noise, output swing, tuning range, and power consumption, this invention designs a Class C VCO with push-pull bias. Implementing this invention offers the following advantages:

[0017] This invention employs a Class C structure and modulates the current conduction angle through a large load capacitor at the tail end, providing lower phase noise performance under the same power consumption.

[0018] This invention enables adaptive adjustment of the bias voltage of complementary NMOS and complementary PMOS circuits through a push-pull structure, providing a larger output swing.

[0019] This invention uses a switched capacitor array to obtain a wider tuning range. When applied to a subsampling phase-locked loop, it can effectively improve the accuracy, swing, and frequency range of the output clock. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of an embodiment of the present invention applied to a Class C voltage-controlled oscillator with a low-jitter subsampling phase-locked loop;

[0021] Figure 2 This is a waveform diagram of the node voltage and node current of the complementary PMOS circuit in this invention.

[0022] Figure 3This is a schematic diagram of an embodiment of the switched capacitor array in this invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0024] See Figure 1 , Figure 1 The diagram illustrates the specific structure of a Class C voltage-controlled oscillator applied to a low-jitter subsampling phase-locked loop according to the present invention. It includes a power supply circuit 1, an energy storage circuit 2, a PMOS bias circuit 3, an NMOS bias circuit 4, a first RC network 5, a second RC network 6, a complementary PMOS circuit 7, a complementary NMOS circuit 8, a switched capacitor array 9, and a differential oscillation slot 10. Specifically:

[0025] The power supply circuit 1 is connected to the complementary NMOS circuit 8 to provide operating current;

[0026] The energy storage circuit 2 is connected to the complementary NMOS circuit 8 to keep the voltage of the source node of the complementary NMOS circuit 8 constant.

[0027] The complementary NMOS circuit 8 is connected to the NMOS bias circuit 4, the first RC network 5 and the differential oscillation slot 10 respectively. The NMOS bias circuit 4 is used to provide a common-mode bias level to the complementary NMOS circuit 8, the first RC network 5 is used to provide a differential-mode bias level to the complementary NMOS circuit 8, and the complementary NMOS circuit 8 is used to transmit current pulses to the differential oscillation slot 10.

[0028] The complementary PMOS circuit 7 is connected to the PMOS bias circuit 3, the second RC network 6 and the differential oscillator 10 respectively. The PMOS bias circuit 3 is used to provide a common-mode bias level to the complementary PMOS circuit 7, the second RC network 6 is used to provide a differential-mode bias level to the complementary PMOS circuit 7, and the complementary PMOS circuit 7 is used to transmit current pulses to the differential oscillator 10.

[0029] The switched capacitor array 9 is connected to the differential oscillator 10. The switched capacitor array 9 is used to adjust the capacitor connected to the differential oscillator 10 to control the output signal of the differential oscillator 10.

[0030] As can be seen from the above, the C-type voltage-controlled oscillator of the present invention adopts a C-type structure. By adding RC networks (i.e., the first RC network 5 and the second RC network 6) to the existing LC voltage-controlled oscillator, a differential bias level is provided for the complementary MOS transistor pair (i.e., the complementary NMOS circuit 8 and the complementary PMOS circuit 7) that act as negative resistance.

[0031] Accordingly, the gate node of the complementary NMOS circuit 8 is connected to the NMOS bias circuit 4 and the first RC network 5, respectively; the drain node of the complementary NMOS circuit 8 is connected to the differential oscillation tank 10 and the drain node of the complementary PMOS circuit 7, respectively; the gate node of the complementary PMOS circuit 7 is connected to the PMOS bias circuit 3 and the second RC network 6, respectively; and the drain node of the complementary PMOS circuit 7 is connected to the differential oscillation tank 10.

[0032] When the circuit is operating normally, the NMOS transistor in the complementary NMOS circuit 8 turns on when the gate voltage of the NMOS transistor equals its threshold voltage. This condition only occupies a small portion of the oscillation cycle, so the stored current is primarily composed of narrow-pulse, high-peak-value current pulses. To maintain the pulse current shape, it is crucial that the NMOS transistor does not enter the transistor region. Therefore, to maximize the output swing, a DC-blocking RC network is needed to provide a differential-mode bias level to the gate nodes of the complementary MOS transistor pair.

[0033] Therefore, the main objective of this invention is to provide a relatively constant bias voltage for the complementary MOS transistor pair (i.e., the complementary NMOS circuit 8 and the complementary PMOS circuit 7) that varies with the Class C voltage-controlled oscillator. Specifically, the DC level generated by the bias circuit (i.e., the PMOS bias circuit 3 and the NMOS bias circuit 4) is used as the common-mode bias level. At the same time, a differential-mode bias level that varies with the output of the Class C voltage-controlled oscillator is also required. Since the voltage swing of the gate node of the complementary MOS transistor pair is directly equal to the output swing of the Class C voltage-controlled oscillator when directly connected by wires, the differential range is too large. Therefore, this invention uses an RC network (i.e., the first RC network 5 and the second RC network 6) to filter the output of the Class C voltage-controlled oscillator, reduce the swing, and add it as a differential-mode component to the common-mode level generated by the bias circuit. The two are used as a whole to bias the complementary MOS transistor pair.

[0034] The current changes of the Class C voltage-controlled oscillator circuit during operation are as follows: After the Class C voltage-controlled oscillator starts oscillating, the complementary NMOS circuit 8 transmits the current pulse to the differential oscillation slot 10, and makes the same pulse flow through the cross-coupled complementary PMOS circuit 7.

[0035] like Figure 2As shown, line a represents the gate node voltage of NMOS transistor MN1, line b represents the gate node voltage of NMOS transistor MN2, line c represents the drain node current of NMOS transistor MN1, line d represents the drain node current of NMOS transistor MN2, and line e represents the source node voltages of NMOS transistors MN1 and MN2. Under steady-state conditions, the voltage waveforms across differential oscillator slot 10 (i.e., the gate nodes of complementary NMOS circuit 8 and complementary PMOS circuit 7) remain stable, outputting a constant sine wave. At this time, the tail current source (i.e., the source node of complementary NMOS circuit 8) exhibits a narrow and high peak in current conduction angle and current pulse shape due to the presence of a large load capacitance C0, thereby improving current utilization efficiency. Furthermore, complementary NMOS circuit 8 and complementary PMOS circuit 7 have identical current conduction angles and current pulse shapes; that is, the current conduction angle and current pulse shape of complementary NMOS circuit 8 are the same as those of complementary PMOS circuit 7.

[0036] The following sections provide further detailed descriptions of the power supply circuit 1, energy storage circuit 2, PMOS bias circuit 3, NMOS bias circuit 4, first RC network 5, second RC network 6, complementary PMOS circuit 7, complementary NMOS circuit 8, switched capacitor array 9, and differential oscillation slot 10:

[0037] I. Power Supply Circuit

[0038] In this invention, an NMOS transistor MN0 is used as the power supply circuit, which can provide the operating current for the main circuit of the entire Class C voltage-controlled oscillator.

[0039] II. Energy Storage Circuit

[0040] An energy storage circuit is disposed between the source node and the ground node of the complementary NMOS circuit 8 to keep the voltage of the source node of the complementary NMOS circuit 8 constant. Preferably, the energy storage circuit is a storage capacitor C0.

[0041] Therefore, by setting a relatively large energy storage capacitor C0 between the source node and the ground node of the complementary NMOS circuit 8, the voltage of the source node can be kept almost constant.

[0042] III. PMOS Bias Circuit

[0043] The PMOS bias circuit includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4. The current branch formed by the third PMOS transistor MP3 and the fourth PMOS transistor MP4 can provide a common-mode bias level higher than the common-mode voltage of the differential oscillator 10. In other words, the common-mode bias level provided by the PMOS bias circuit 3 to the complementary PMOS circuit 7 is higher than the common-mode voltage of the differential oscillator 10.

[0044] IV. NMOS Bias Circuit

[0045] The NMOS bias circuit includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4. The current branch formed by the third NMOS transistor MN3 and the fourth NMOS transistor MN4 can provide a common-mode bias level lower than the common-mode voltage of the differential oscillating tank 10. In other words, the common-mode bias level provided by the NMOS bias circuit 4 to the complementary NMOS circuit 8 is lower than the common-mode voltage of the differential oscillating tank 10.

[0046] For example, if the output level of a Class C voltage-controlled oscillator is 0–1.2V, then the center level is 0.6V. In this case, the bias of the NMOS bias circuit 4 should be less than 0.6V (e.g., 0.5V) to ensure that the common-mode bias level provided by the NMOS bias circuit 4 to the complementary NMOS circuit 8 is lower than the common-mode voltage of the differential oscillator slot 10. Meanwhile, the bias of the PMOS bias circuit 3 should be greater than 0.6V (e.g., 0.7V) to ensure that the common-mode bias level provided by the PMOS bias circuit 3 to the complementary PMOS circuit 7 is higher than the common-mode voltage of the differential oscillator slot 10.

[0047] V. First RC Network

[0048] The first RC network 5 includes a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2. The first capacitor C1, the second capacitor C2, the first resistor R1, and the second resistor R2 together serve to block DC and conduct AC, which can suppress the DC component of the output and no longer provide a common-mode bias level for the complementary NMOS circuit 8.

[0049] VI. Second RC Network

[0050] The second RC network 6 includes a third capacitor C3, a fourth capacitor C4, a third resistor R3, and a fourth resistor R4. The third capacitor C3, the fourth capacitor C4, the third resistor R3, and the fourth resistor R4 together serve to block DC and conduct AC, which can suppress the DC component of the output and no longer provide a common-mode bias level for the complementary PMOS circuit 7.

[0051] VII. Complementary PMOS Circuit

[0052] The PMOS circuit 7 includes a first PMOS transistor MP1 and a second PMOS transistor MP2; wherein, the first PMOS transistor MP1 and the second PMOS transistor MP2 are complementary PMOS pairs, which can provide negative resistance for the differential oscillation slot 10, thereby maintaining the oscillation continuously without decaying, and playing the role of output limiting.

[0053] It should be noted that the output voltage, current conduction angle, and current pulse shape of the complementary PMOS circuit 7 are related to the ratio of the width to the length of the PMOS transistor in the complementary PMOS circuit 7.

[0054] VIII. Complementary NMOS Circuit

[0055] The NMOS circuit 8 includes a first NMOS transistor MN1 and a second NMOS transistor MN2; wherein, the first NMOS transistor MN1 and the second NMOS transistor MN2 are complementary NMOS pairs, which can also provide negative resistance for the differential oscillation slot 10, thereby maintaining the oscillation continuously without decaying and playing the role of output limiting.

[0056] It should be noted that the output voltage, current conduction angle, and current pulse shape of the complementary NMOS circuit 8 are related to the ratio of the width to the length of the NMOS transistor in the complementary NMOS circuit 8.

[0057] 9. Switch Capacitor Array (SCA)

[0058] like Figure 3 As shown, since it is difficult to adjust the inductance value in integrated circuits, the frequency tuning of a Class C voltage-controlled oscillator can be achieved by adjusting the capacitance value of a variable capacitor and the number of switched capacitors connected in the array. To widen the tuning range of the Class C voltage-controlled oscillator and output more different frequencies, this invention uses a switched capacitor array for adjustment.

[0059] 10. Differential Oscillating Tank

[0060] The inductor L, the first voltage-controlled capacitor Cv1, and the second voltage-controlled capacitor Cv2 together form a differential oscillation slot 10 (i.e., an LC resonant slot). The first voltage-controlled capacitor Cv1 and the second voltage-controlled capacitor Cv2 are adjustable capacitors that can effectively control the time constant of the resonance of the Class C voltage-controlled oscillator, thereby controlling the oscillation frequency of the output signal.

[0061] like Figure 3 As shown, the capacitance value connected to the differential oscillator 10 can be controlled by giving different control bits, thereby changing the resonance time constant; wherein, the capacitance value connected to the differential oscillator 10 is inversely proportional to the oscillation frequency of the output signal of the differential oscillator 10, that is, the more capacitors connected, the lower the oscillation frequency.

[0062] More preferably, the zero-peak differential voltage swing across the differential oscillator 10 is less than or equal to the voltage threshold of the complementary NMOS circuit 8 and the complementary PMOS circuit 7.

[0063] To minimize the impact of phase noise, the zero-peak differential voltage swing across the differential oscillator slot 10 must be equal to or lower than the voltage threshold of the complementary CMOS pair (i.e., complementary NMOS circuit 8 and complementary PMOS circuit 7). Therefore, this invention employs an improved push-pull structure to generate the bias voltage for the circuit. Its advantage lies in its ability to accommodate larger voltage swings. By introducing additional RC networks (first RC network 5 and second RC network 6), a differential bias level is provided to the gate nodes of the CMOS pair (i.e., complementary NMOS circuit 8 and complementary PMOS circuit 7), allowing for a larger oscillator output swing before the complementary CMOS pair (i.e., complementary NMOS circuit 8 and complementary PMOS circuit 7) is pushed into the transistor region. In the NMOS bias circuit 4 and PMOS bias circuit 3, both the NMOS and PMOS transistors function as level shifters, with the common-mode portion of the output voltage adaptively adjusting the bias voltage. This effectively maintains the oscillator slot impedance at a low common-mode bias level, thereby obtaining a more stable common-mode voltage.

[0064] In summary, considering the trade-offs among various performance parameters of voltage-controlled oscillators (VCOs) in low-jitter subsampling phase-locked loops (PLLs), this invention designs a Class C VCO with push-pull bias. This invention can provide lower phase noise than other types of oscillators while maintaining low power consumption. The push-pull structure enables adaptive adjustment of the bias voltages of complementary NMOS and PMOS circuits, providing a larger output swing. Furthermore, the use of a switched capacitor array achieves a wider tuning range. When applied to subsampling PLLs, this invention can effectively improve the accuracy, swing, and frequency range of the output clock.

[0065] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A Class C voltage-controlled oscillator applied to a low-jitter subsampling phase-locked loop, characterized in that, It includes a power supply circuit, an energy storage circuit, a PMOS bias circuit, an NMOS bias circuit, a first RC network, a second RC network, a complementary PMOS circuit, a complementary NMOS circuit, a switched capacitor array, and a differential oscillation slot. The power supply circuit is connected to the complementary NMOS circuit to provide operating current; The energy storage circuit is connected to the complementary NMOS circuit to keep the voltage of the source node of the complementary NMOS circuit constant. The complementary NMOS circuit is connected to the NMOS bias circuit, the first RC network and the differential oscillator slot respectively. The NMOS bias circuit is used to provide a common-mode bias level to the complementary NMOS circuit, the first RC network is used to provide a differential-mode bias level to the complementary NMOS circuit, and the complementary NMOS circuit is used to transmit current pulses to the differential oscillator slot. The complementary PMOS circuit is connected to the PMOS bias circuit, the second RC network, and the differential oscillator slot, respectively. The PMOS bias circuit is used to provide a common-mode bias level to the complementary PMOS circuit, the second RC network is used to provide a differential-mode bias level to the complementary PMOS circuit, and the complementary PMOS circuit is used to transmit current pulses to the differential oscillator slot. The switched capacitor array is connected to the differential oscillator slot, and the switched capacitor array is used to adjust the capacitor connected to the differential oscillator slot to control the output signal of the differential oscillator slot; The gate node of the complementary NMOS circuit is connected to the NMOS bias circuit and the first RC network, respectively; the drain node of the complementary NMOS circuit is connected to the differential oscillation tank and the drain node of the complementary PMOS circuit, respectively; the gate node of the complementary PMOS circuit is connected to the PMOS bias circuit and the second RC network, respectively; and the drain node of the complementary PMOS circuit is connected to the differential oscillation tank. The common-mode bias level provided by the NMOS bias circuit to the complementary NMOS circuit is lower than the common-mode voltage of the differential oscillator; the common-mode bias level provided by the PMOS bias circuit to the complementary PMOS circuit is higher than the common-mode voltage of the differential oscillator.

2. The Class C voltage-controlled oscillator applied to a low-jitter subsampling phase-locked loop as described in claim 1, characterized in that, The zero-peak differential voltage swing across the differential oscillation slot is less than or equal to the voltage threshold of the complementary NMOS circuit and the complementary PMOS circuit.

3. The Class C voltage-controlled oscillator applied to a low-jitter subsampling phase-locked loop as described in claim 1, characterized in that, The NMOS transistor is turned on when the gate voltage of the NMOS transistor in the complementary NMOS circuit is equal to the threshold voltage of the NMOS transistor in the complementary NMOS circuit.

4. The Class C voltage-controlled oscillator applied to a low-jitter subsampling phase-locked loop as described in claim 1, characterized in that, Under steady-state conditions, the differential oscillating slot outputs a constant sine wave at both ends.

5. The Class C voltage-controlled oscillator applied to a low-jitter subsampling phase-locked loop as described in claim 1, characterized in that, Under steady-state conditions, the current conduction angle and current pulse shape of the complementary NMOS circuit are the same as those of the complementary PMOS circuit.

6. The Class C voltage-controlled oscillator applied to a low-jitter subsampling phase-locked loop as described in claim 1, characterized in that, The output voltage, current conduction angle, and current pulse shape of the complementary NMOS circuit are related to the ratio of the width to the length of the NMOS transistor in the complementary NMOS circuit. The output voltage, current conduction angle, and current pulse shape of the complementary PMOS circuit are related to the ratio of the width to the length of the PMOS transistor in the complementary PMOS circuit.

7. The Class C voltage-controlled oscillator applied to a low-jitter subsampling phase-locked loop as described in claim 1, characterized in that, The capacitance value connected to the differential oscillation slot is inversely proportional to the oscillation frequency of the output signal of the differential oscillation slot.

8. The Class C voltage-controlled oscillator applied to a low-jitter subsampling phase-locked loop as described in claim 1, characterized in that, The energy storage circuit is located between the source node and the ground node of the complementary NMOS circuit to keep the voltage of the source node of the complementary NMOS circuit constant.

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