Integrated inductive-capacitive resonant cavity with third order harmonic trapping

Abstract

An integrated inductor-capacitor resonant cavity with third harmonic trapping, comprising a primary 8-shaped inductor and a series inductor-capacitor network, the primary 8-shaped inductor and the series inductor-capacitor network being connected in parallel across a first node and a second node and using a multilayer structure layout fabricated on a substrate, wherein: due to the layout symmetry, the magnetic coupling between the primary 8-shaped inductor and the series inductor-capacitor network is mitigated, and the resonant frequency of the series inductor-capacitor network is equal to three times the resonant frequency of the inductor-capacitor resonant cavity.

Description

Technical Field

[0001] This disclosure generally relates to integrated inductor-capacitor resonators, and more particularly to integrated inductor-capacitor resonators with third-order harmonic trap. Background Technology

[0002] An LC (inductor-capacitor) resonant cavity (LC tank) comprises a parallel connection of an inductor and a capacitor and is configured to provide high impedance at the resonant frequency. In a particular case of interest to those skilled in the art, where the LC resonant cavity is fabricated on a single substrate, it is referred to as an integrated LC resonant cavity, and the cost of an integrated LC resonant cavity is determined by the layout area. Integrated LC resonant cavities are typically used as a load to receive a fundamental frequency current signal generated by a gain device and are configured to convert that current signal into a voltage signal with high gain, where the fundamental frequency is approximately equal to the resonant frequency. In one embodiment, the gain device is an amplifier; in another embodiment, the gain device is a mixer. Nonlinearity of the gain device typically results in a perceptible third harmonic component in the current signal. Third harmonic components are generally detrimental and can further lead to other undesirable spurious frequency components through various mixing mechanisms in subsequent circuitry. Third harmonic filters can be used to suppress third harmonic components, but can introduce several problems. First, third harmonic filters may introduce perceptible insertion loss into the current signal. Secondly, the third harmonic filter may occupy a considerable layout area and significantly increase the cost of the integrated LC resonator. Thirdly, there may be a strong interaction between the third harmonic filter and the integrated LC resonator, which may adversely affect the response of the integrated LC resonator at the fundamental frequency.

[0003] What those skilled in the art need is an integrated LC filter that can effectively suppress third harmonic components without requiring a large layout area, introducing significant insertion loss, or adversely affecting the response at the fundamental frequency. Summary of the Invention

[0004] In one embodiment, an LC (inductor-capacitor) resonant cavity includes a primary octagonal inductor and a series LC network connected in parallel, spanning between a first node and a second node, and is fabricated on a substrate using a multilayer structure layout, wherein: due to the symmetrical layout, the magnetic coupling between the primary octagonal inductor and the series LC network is reduced, and the resonant frequency of the series LC network is equal to three times the resonant frequency of the LC resonant cavity.

[0005] In one embodiment, an LC (inductor-capacitor) resonant cavity includes a primary octagonal inductor and a series LC network. The primary octagonal inductor and the series LC network are connected in parallel, spanning between a first node and a second node, and are fabricated on a substrate using a multilayer structure layout. The primary octagonal inductor includes a first quadrant inductor, a second quadrant inductor, a third quadrant inductor, and a fourth quadrant inductor connected in series. The series inductor-capacitor network includes a first half-inductor, a series capacitor, and a second half-inductor connected in series. The third quadrant inductor and the first quadrant inductor are substantially mirror images of each other with respect to a plane of symmetry. The second quadrant inductor and the fourth quadrant inductor are substantially mirror images of each other with respect to the plane of symmetry. The first half-inductor is substantially symmetrical about the plane of symmetry. Attached Figure Description

[0006] Figure 1A A schematic diagram of an LC resonant cavity according to an embodiment of the present disclosure is shown.

[0007] Figure 1B An embodiment according to the present disclosure is shown. Figure 1A The layout of the LC resonant cavity.

[0008] Figure 2 Showing Figure 1A A schematic diagram of the application circuit of an LC resonant cavity.

[0009] Figure 3 Showing Figure 1A Another application circuit diagram of the LC resonant cavity.

[0010] Symbol Explanation

[0011] 100: LC resonant cavity

[0012] 110: Series LC network

[0013] 210: Differential Amplifier

[0014] 211, 212, 311, 312: NMOS transistors

[0015] 200, 300: Application Circuits

[0016] 301: First internal node

[0017] 302: Second internal node

[0018] 310: Mixer

[0019] 321, 322, 323, 324: Switches

[0020] V DD Power supply node

[0021] L1: Primary 8-type inductor

[0022] C1: Primary capacitor

[0023] N1: First node

[0024] N2: Second node

[0025] L 1a : Lower left inductor

[0026] L 1b Top right inductor

[0027] L 1c Top left inductor

[0028] L 1d Right lower inductor

[0029] L 2p Left inductor

[0030] C2: Series capacitor

[0031] L 2n Right inductor

[0032] CT1: Primary central tap

[0033] I1: First current

[0034] I2: Second current

[0035] f0: Fundamental frequency

[0036] Z 100 Z 110 :impedance

[0037] 3f0: Third harmonic frequency

[0038] f: Frequency variable

[0039] C2: Equivalent capacitor

[0040] M1: First metal layer

[0041] M2: Second metal layer

[0042] GCP: Geometric Center Point

[0043] CT1: Primary central tap

[0044] J1: First contact point

[0045] V12: Contact Layer

[0046] L3: Secondary 8-type inductor

[0047] C3: Secondary capacitor

[0048] N3: Third Node

[0049] N4: Fourth Node

[0050] L 3a L 3b L 3c L 3d Inductor

[0051] CT2: Secondary central tap

[0052] I3: Third Current

[0053] V1, V2, X1, X2, Y1, Y2: Voltage signals Detailed Implementation

[0054] This disclosure relates to LC resonant cavities. Although the specification describes several exemplary embodiments of this disclosure that are considered advantageous modes for carrying out the invention, it should be understood that the invention can be implemented in many ways and is not limited to the specific examples described below or the particular manner in which any feature of these examples is implemented. In other instances, existing details are not shown or described to avoid obscuring parts of this disclosure.

[0055] Those skilled in the art to which this invention pertains will understand the microelectronics-related terms and basic concepts used in this disclosure, such as "voltage," "current," "signal," "frequency," "amplifier," "mixer," "load," "impedance," "resonance," "series connection," "parallel connection," "switch," "inductor," "capacitor," "circuit node," "ground," "DC (direct current)," "power supply," "MOS (metal-oxide-semiconductor) transistor," "CMOS (complementary metal-oxide-semiconductor) process technology," "NMOS (n-channel metal-oxide-semiconductor) transistor," and "PMOS (p-channel metal-oxide-semiconductor) transistor." When used in the context of microelectronics, such terms and basic concepts will be readily apparent to those skilled in the art and will therefore not be explained in detail herein.

[0056] Those skilled in the art to which this invention pertains understand how to calculate the impedance of inductors and capacitors, and understand Ohm's law and the relationship between voltage, current, and impedance.

[0057] Those skilled in the art to which this invention pertains can read circuit diagrams containing electronic components such as inductors, capacitors, resistors, NMOS transistors, and PMOS transistors without needing to describe in detail how one component is connected to another. Those skilled in the art can also identify ground symbols, capacitor symbols, inductor symbols, resistor symbols, and the symbols for PMOS and NMOS transistors, and identify their "source terminal," "gate terminal," and "drain terminal." Regarding MOS transistors, for simplicity, in the following text, "source terminal" will be simply referred to as "source," "gate terminal" as "gate," and "drain terminal" as "drain."

[0058] A circuit is a collection of transistors, capacitors, resistors, and / or other electronic devices that are interconnected in some way to perform a certain function.

[0059] In this disclosure, "circuit node" is generally simply referred to as "node" when its meaning is clear from the context.

[0060] A signal is a voltage or current with a variable level that carries specific information and can change over time. The signal level at a given moment indicates the signal state at that moment.

[0061] A network is a circuit or a set of circuits.

[0062] The power supply node is essentially a circuit node with a steady-state voltage, as is the ground node. Both the power supply node and the ground node are DC (direct current) nodes, but their voltage levels differ; that is, the voltage level of the power supply node is higher than that of the ground node. Following the convention widely used in the literature, in this disclosure, "V" is used in the circuit... DD This indicates the power supply node. Although the DC level of the ground node is typically 0V, it is not necessarily 0V. What matters is the voltage difference between the power supply node and the ground node. For a given circuit, if the DC voltage levels of all nodes are increased by the same amount, the circuit's behavior remains unchanged.

[0063] A logic signal is a voltage signal with two states: low and high. A logic signal is in a high state when its voltage level is above a breakpoint, and in a low state otherwise. The low state is also called the "0" state, and the high state is also called the "1" state. For a logic signal Q, when we say "Q is high" or "Q is low," we mean "Q is in a high state" or "Q is in a low state." Similarly, when we say "Q is 1" or "Q is 0," we mean "Q is in a 1 state" or "Q is in a 0 state."

[0064] The first logic signal does not necessarily have the same breakpoint as the second logic signal.

[0065] If the first logic signal and the second logic signal are always in opposite states, then the first logic signal is called the logical inverse of the second logic signal. That is, when the first logic signal is low, the second logic signal is high; and when the first logic signal is high, the second logic signal is low. When the first logic signal is considered the logical inverse of the second logic signal, the first logic signal and the second logic signal are said to be complementary to each other.

[0066] Logic signals are typically used as control signals to enable or disable circuit functions. When a logic signal is in a logic state that enables the circuit function, the logic signal is said to be "asserted"; otherwise, the logic signal is said to be "de-asserted". When a logic signal is "asserted" when it is high, it is called "active high"; when a logic signal is "asserted" when it is low, it is called "active low".

[0067] A switch is used in this disclosure. The switch is configured as a means of conditionally connecting a first node to a second node according to the control of a logic signal; when the logic signal is established, the switch is opened and behaves as a short circuit; and when the logic control signal is de-established, the switch is closed and behaves as an open circuit.

[0068] When an NMOS transistor is biased in the saturation region where the gate-to-source voltage is higher than the threshold voltage but the gate-to-drain voltage is lower than the threshold voltage, the NMOS transistor can be used as an amplifier.

[0069] If an NMOS transistor is in the transistor region (where both the gate-to-source and gate-to-drain voltages are above the threshold voltage) when the control signal is established, and in the cutoff region (where both the gate-to-source and gate-to-drain voltages are below the threshold voltage) when the control signal is deactivated, then the NMOS transistor can be used as a switch controlled by the control signal.

[0070] The first objective of this disclosure is to have an LC resonant cavity that has a very high impedance at the fundamental frequency but a very low impedance at the third harmonic frequency.

[0071] The second objective is to minimize (if any) the conflict between having very low impedance at the third harmonic frequency and very high impedance at the fundamental frequency. In other words, reducing (i.e., improving) the impedance at the third harmonic frequency does not compromise (i.e., reduce) the impedance at the fundamental frequency.

[0072] The third goal is that LC can be layout-efficient and does not require a large layout area.

[0073] Figure 1A The diagram illustrates a schematic of an LC resonant cavity 100 according to an embodiment of the present disclosure. The LC resonant cavity 100 includes a primary 8-shape inductor L1, a primary capacitor C1, and a serial LC network 110. The primary 8-shape inductor L1, the primary capacitor C1, and the serial LC network 110 are connected in parallel, spanning a first node N1 and a second node N2. The primary 8-shape inductor L1 comprises four inductors connected in series, including a lower left inductor L... 1a (referred to as the first quadrant inductor), upper right inductor L 1b (referred to as the second quadrant inductor), upper left inductor L 1c (referred to as the third quadrant inductor) and the lower right inductor L 1d (referred to as the fourth quadrant inductor), and the series LC network 110 includes the left inductor L 2p (referred to as the first half-inductor), series capacitor C2, and right inductor L 2n (Referred to as the second half-inductor) in series connection. Upper right inductor L 1b Connect the upper left inductor L at the primary center tap CT1. 1c Inductor L (lower left) 1a The layout is essentially the upper left inductor L. 1c Mirror image relative to the plane of symmetry. Upper right inductor L 1b The layout is essentially the lower right inductor L. 1d The mirror image relative to the plane of symmetry.

[0074] Left inductor L 2p and right inductor L 2n They are arranged to be substantially symmetrical with respect to the plane of symmetry. When the first current I1 flows from N1 to N2 through the primary octet inductor L1, L... 1a L 1b L 1c and L 1d Each of them is excited and coupled to the left inductor L. 2p and right inductor L 2n The magnetic field induces a second current I2. Due to the substantially symmetrical layout, from the lower left inductor L... 1a To the left inductor L 2p (Right inductor L) 2n The magnetic coupling is essentially transferred from the upper left inductor L. 1c To the left inductor L 2p (Right inductor L) 2n The magnetic coupling is canceled out, similarly from the upper right inductor L. 1bTo the left inductor L 2p (Right inductor L) 2n The magnetic coupling is essentially from the lower right inductor L. 1d To the left inductor L 2p (Right inductor L) 2n The magnetic coupling is canceled out. Therefore, the net magnetic coupling between the primary octet inductor L1 and the series LC network 110 can be effectively reduced; that is, the second current I2 flowing through the series LC network 110 based on the magnetic field excited by the primary octet inductor L1 can be very small.

[0075] In one embodiment, the LC resonant cavity 100 is configured to provide an impedance (e.g., measured via N1 and N2) to Z 100 This indicates that the impedance is high at a fundamental frequency f0, but low at its third harmonic frequency 3f0. From the primary octet L1 to the left inductor L... 2p (Right inductor L) 2n There is no obvious magnetic coupling, and, given that both C1 and L1 have very high quality factors in their first-order approximations, Z 100 It can be expressed by the following formula:

[0076]

[0077] Here, f represents the frequency variable, Z 110 The impedance of the series LC network 110 can be expressed by the following formula:

[0078] Z 110 =j2πf(L 2p +L 2n )-j / (2πfC2) (2)

[0079] Clearly, Z is true if the following conditions are met. 110 It is approximately zero at the third harmonic frequency 3f0:

[0080] 6πf0(L 2p +L 2n )=1 / (6πf0C2) (3)

[0081] Or equivalently,

[0082]

[0083] When the condition of equation (4) holds, the series LC network 110 forms a series resonance at the third harmonic frequency, where L 2p and L 2pThe combined impedance of Z110 is equal in magnitude to that of C2, but opposite in polarity; therefore, Z110 is almost zero at the third harmonic frequency 3f0. 100 The same applies. In this case, the third harmonic frequency component will be effectively "trapped" by the cascaded LC network 110.

[0084] From equations (2) and (4), we can derive Z at the fundamental frequency f0. 110 The value is:

[0085]

[0086] Therefore, at the fundamental frequency f0, the series LC network 110 behaves like an equivalent capacitor C′2 with a capacitance of 9C² / 8, and at the fundamental frequency Z 100 The value can be written as:

[0087]

[0088] Where C′2≡9C2 / 8.

[0089] Therefore, Z is true if the following conditions are met. 100 It is very large at the fundamental frequency f0:

[0090] 2πf0(C1+C′2)=1 / (2πf0L1) (7)

[0091] Or equivalently,

[0092]

[0093] Therefore, Z was achieved. 100 The first target can be very high at f0, and very low at 3f0.

[0094] It also achieves a second objective: minimal conflict (if any) between having very low impedance at the third harmonic frequency and very high impedance at the fundamental frequency. This is because Z 100 The value at 3f0 can be very low, depending on the condition that equation (4) is satisfied, while Z 100 The value at f0 can be very high, depending on the condition that equation (8) is satisfied, and these two conditions are independent and therefore can be satisfied simultaneously. 100 How low it is at 3f0 is mainly determined by the limiting factor L. 2p and L 2n The limitations of Z, and 100 The high value at f0 is mainly restricted by the constraint factor L1, and there is no conflict between the two.

[0095] From equation (8), the important factor is (C1 + C′2), which is the sum of the capacitance values ​​of the primary capacitor C1 and the equivalent capacitor C′2. Therefore, C1 can be intentionally eliminated (i.e., C1 = 0, corresponding to an open circuit), and the selection of C2 (and consequently C′2) depends entirely on equations (4) and (8). 2p L 2n An appropriate combination of the values ​​of L1 and L2 is needed to achieve a high impedance at the fundamental frequency f0 and a low impedance at the third harmonic frequency 3f0.

[0096] In one embodiment, an LC resonant cavity 100 is fabricated using a multilayer structure disposed on a substrate. The multilayer structure includes multiple metal layers, including a first metal layer denoted as "M1", a second metal layer denoted as "M2", and a set of lower metal layers that can be used to efficiently arrange inter-digitating multi-finger MOM (metal-oxide-metal) capacitors, and multiple interconnect contact layers, including a via layer denoted as "V12", which provides interconnection between "M1" and "M2". Figure 1B An exemplary layout of an LC resonant cavity 100 according to an embodiment of the present disclosure is shown. Description, top view, and side view are shown herein.

[0097] From the top view, the primary 8-type inductor L1 is composed of L... 1a L 1b L 1c and L 1d Series connection; L 1a It is positioned on M1, between N1 and the geometric center point GCP; L 1b It is positioned on M1, between the geometric center point GCP and the primary center tap CT1; L 1c Located between the primary center tap CT1 and the geometric center point GCP, a large portion of it is located on M1, but a smaller portion, forming the upper half of a cross-over bridge centered on the geometric center point GCP, is located on M2. Additionally, the first connection point J1 is on V12; L 1d Located between the geometric center point GCP and N2, a large section of the bridge is located on M1, but a small section, which forms the lower half of the crossbridge centered on the geometric center point GCP, is located on M2. Additionally, the second junction J2 is located on V12.

[0098] Furthermore, C1 is a MOM capacitor laid out across N1 and N2. C2 is also a MOM capacitor, with one side connected to L. 2p Connected, the other side is connected to L 2n Connected. Clearly, L 1c In essence, it is L 1a The mirror image of the plane of symmetry, and L 1b In essence, it is L 1d The mirror image relative to the plane of symmetry. L 2p and L 2n All are arranged on M1, and are substantially symmetrical with respect to the plane of symmetry. L 2p The lower half of L 1a The main parts are adjacent and parallel, while L 2p The upper part and L 1c The main parts are adjacent and parallel. L 2n The lower half of L 1d The main parts are adjacent and parallel, while L 2n The upper part and L 1b The main parts are adjacent and parallel. When the first current I1 flows from N1 to N2 through L1, it flows clockwise through L... 1a Then it flows counterclockwise through L 1b Then it flows counterclockwise through L 1c Finally, it flows clockwise through L 1d Simultaneously stimulates L 2p and L 2n Coupled magnetic fields. However, due to symmetry, from L 1a To L 2p and L 2n The magnetic coupling between the two is essentially equal to that from L 1c To L 2p and L 2n The two are magnetically coupled, but their polarities are opposite, thus they are essentially canceled out. Similarly, from L... 1b To L 2p and L 2n Magnetic coupling is essentially equal to that from L 1d To L 2p and L 2n The magnetic coupling is opposite in polarity, so it is essentially canceled out. Therefore, from the primary octagonal inductor L1 to L... 2p and L 2n The net magnetic coupling is very small. Using the reciprocity theorem, from L... 2p and L 2n The net magnetic coupling to the primary type 8 inductor L1 is also very small.

[0099] Because of L 2p and L 2nThe inductor is arranged to surround the primary octagonal inductor L1, so the layout area occupied by the primary octagonal inductor L1 is reduced by L. 2p and L 2n Reusability. Thus, the third goal of efficient LC resonator layout is achieved.

[0100] In an alternative embodiment not shown in the accompanying drawings but which is clear to those skilled in the art, L 2p and L 2n It is positioned on "M2" instead of "M1". In this alternative embodiment, symmetry also holds, therefore, the primary octagonal inductor L1 and L... 2p and L 2n The result that the net magnetic coupling between the two is very small also holds true.

[0101] Now refer to Figure 1A In an alternative embodiment, not shown in the figures but clear to those skilled in the art: C2 is removed (i.e., becomes short-circuited) and replaced with two capacitors of twice the capacitance, one of which is inserted into L. 2p Between N1 and L, another capacitor is inserted. 2n Between and N2. Thus, Z 110 It remains unchanged.

[0102] In a further embodiment, the LC resonant cavity 100 further includes a secondary 8-shape inductor L3 and a secondary capacitor C3, the secondary 8-shape inductor L3 and the secondary capacitor C3 being connected in parallel across a third node N3 and a fourth node N4, wherein the secondary 8-shape inductor L3 comprises four inductors connected in series, the four inductors including inductor L 3a Inductor L 3b Inductor L 3c and inductor L 3d Inductor L 3b Connect inductor L at the secondary center tap CT2. 3c Inductor L 3a It is arranged as an inductor L 3c The mirror image of the inductor L relative to the plane of symmetry. 3b It is arranged as an inductor L 3d Relative to the mirror image of the plane of symmetry. When the third current I3 flows from N3 to N4 through the secondary octet inductor L3, L... 3a L 3b L 3c and L 3d Each of them excites coupling to the left inductor L 2p and right inductor L 2n The magnetic field. Due to its essentially symmetrical layout, from L3a To L 2p (L 2n The magnetic coupling of ) is essentially removed from L 3c To L 2p (L 2n The magnetic coupling cancels out, and similarly, from L 3b To L 2p (L 2n The magnetic coupling of ) is essentially removed from L 3d To L 2p (L 2n The magnetic coupling is canceled out. Therefore, the net magnetic coupling between the secondary octet inductor L3 and the series LC network 110 can be effectively reduced.

[0103] On the other hand, the secondary octagonal inductor L3 is arranged to have strong mutual coupling with the primary octagonal inductor L1, such that the first current I1 on the primary octagonal inductor L1 can be effectively coupled to the third current I3 on ​​the secondary octagonal inductor L3. This can be achieved by employing a transformer layout, for example, by using a different metal layer than M1 and M2 to arrange L3, which substantially overlaps with L1 when viewed from above but is separated from L1 when viewed from the side. In this way, L3 has the same symmetry as L1, and due to the overlap, the coupling between L3 and L1 can be very strong. As long as the symmetry is maintained, those skilled in the art can employ any layout such that from L1 (and L3, if applicable) to L... 2p and L 2n The net magnetic coupling can be effectively reduced.

[0104] like Figure 2 As shown, an application circuit 200 according to an embodiment of this disclosure includes: a differential amplifier 210 comprising two NMOS transistors 211 and 212, the differential amplifier 210 being configured to receive a differential signal and use an LC resonant cavity 100 as a load to establish an output. The differential amplifier 210 includes two NMOS transistors 211 and 212, and the differential signal includes two voltage signals V1 and V2. The source, gate, and drain of NMOS transistor 211 are connected to ground, the voltage signal V1 of the LC resonant cavity 100, and the first node N1 of the LC resonant cavity 100, respectively. The source, gate, and drain of NMOS transistor 212 are connected to ground, the voltage signal V2 of the LC resonant cavity 100, and the second node N2 of the LC resonant cavity 100, respectively. The primary center tap CT1 of the LC resonant cavity 100 is connected to the power supply node V. DD The output of application circuit 200 is the voltage difference between N1 and N2. If the LC resonant cavity 100 further includes a secondary octet inductor L3 ( Figure 1A As shown), the output can be the third node N3 and the fourth node N4. Figure 1AThe voltage difference between the two terminals (shown) and the secondary center tap CT2 is connected to a DC (direct current) node, which determines the DC value of the output. Application circuit 200 is readily understood by those skilled in the art to which this invention pertains and therefore will not be described further.

[0105] like Figure 3 As shown, another application circuit 300 according to an embodiment of the present disclosure includes a mixer 310. The mixer 310 is configured to mix a first differential signal containing two voltage signals X1 and X2 and a second differential signal containing additional voltage signals Y1 and Y2, and uses an LC resonant cavity 100 as a load to establish the output. The mixer 310 includes two NMOS transistors 311 and 312 and four switches 321, 322, 323, and 324. The source, gate, and drain of NMOS transistor 311 are connected to ground, voltage signal X1, and a first internal node 301, respectively. The source, gate, and drain of NMOS transistor 312 are connected to ground, voltage signal X2, and a second internal node 302, respectively. The first node N1 of the LC resonant cavity 100 is connected to the first internal node 301 via switch 321 controlled by voltage signal Y1, and to the second internal node 302 via switch 323 controlled by voltage signal Y2, wherein Y1 and Y2 are complementary logic signals. The second node N2 of the LC resonant cavity 100 is connected to the first internal node 301 via a switch 322 controlled by voltage signal Y2, and to the second internal node 302 via a switch 324 controlled by voltage signal Y1. The primary center tap CT1 of the LC resonant cavity 100 is connected to the power supply node V. DD The output of application circuit 300 is the voltage difference between N1 and N2. If the LC resonant cavity 100 also includes a secondary octet inductor L3 (such as...), Figure 1A As shown), the output can be the third node N3 and the fourth node N4 (see...). Figure 1A The voltage difference between the two signals is determined by the secondary center tap CT2, which is connected to a DC (direct current) node that determines the DC value of the output. Mixer 310 is referred to in the prior art as a "Gilbert cell," and the application circuit 200 is readily understood by those skilled in the art to which this invention pertains, and therefore will not be described further. In one embodiment, the fundamental frequency of the second differential signal (including Y1 and Y2) is approximately equal to the resonant frequency of the LC resonant cavity 100. Mixer 310 belongs to the category of mixers known as "double side-band mixers." Those skilled in the art to which this invention pertains may substitute mixer 310 for a "single side-band mixer," which still falls within the scope of this disclosure.

[0106] Those skilled in the art will readily observe that various modifications and alterations can be made to the apparatus and method while retaining the content of this disclosure. Therefore, the above disclosure should not be construed as being limited solely by the scope of the appended claims.

Claims

1. An inductor-capacitor resonant cavity, comprising a primary octagonal inductor and a series inductor-capacitor network, the primary octagonal inductor and the series inductor-capacitor network being connected in parallel, spanning between a first node and a second node, and fabricated on a substrate using a multilayer structure layout, wherein: The primary 8-type inductor includes a first quadrant inductor, a second quadrant inductor, a third quadrant inductor, and a fourth quadrant inductor connected in series. The series inductor-capacitor network includes a first half-inductor, a series capacitor, and a second half-inductor connected in series. The third quadrant inductor and the first quadrant inductor are mirror images of each other with respect to a plane of symmetry; The second quadrant inductor and the fourth quadrant inductor are mirror images of each other with respect to the plane of symmetry; The first half-inductor is symmetrical about the plane of symmetry; and, The second half-inductor is symmetrical about the plane of symmetry. The multilayer structure includes a first metal layer, a second metal layer, and an interconnection point layer configured to provide a connection between the first metal layer and the second metal layer.

2. The inductor-capacitor resonant cavity as described in claim 1, wherein: The first quadrant inductor is disposed on the first metal layer, between the first node and a geometric center point; the second quadrant inductor is disposed on the first metal layer, between the geometric center point and a primary center tap; the third quadrant inductor is disposed between the primary center tap and the geometric center point, with a large portion of its main section disposed on the first metal layer and a smaller portion forming the first half of a crossbridge centered on the geometric center point disposed on the second metal layer; and the fourth quadrant inductor is disposed between the geometric center point and the second node, with a large portion of its main section disposed on the first metal layer and a smaller portion forming the second half of the crossbridge centered on the geometric center point disposed on the second metal layer.

3. The inductor-capacitor resonant cavity as claimed in claim 2, wherein a front half of the first half-inductor is adjacent to and parallel to a main portion of the first quadrant inductor, a rear half of the first half-inductor is adjacent to and parallel to a main portion of the third quadrant inductor, a front half of the second half-inductor is adjacent to and parallel to a main portion of the second quadrant inductor, and a rear half of the second half-inductor is adjacent to and parallel to a main portion of the fourth quadrant inductor.

4. The inductor-capacitor resonant cavity of claim 3, wherein a value of the series capacitor is selected such that the series inductor-capacitor network resonates at three times a fundamental frequency.

5. The inductor-capacitor resonant cavity as claimed in claim 4, wherein the inductor-capacitor resonant cavity resonates at the fundamental frequency.

6. The inductor-capacitor resonant cavity of claim 5, wherein the inductor-capacitor resonant cavity is configured as a load of a differential amplifier, the differential amplifier being configured to receive a voltage signal having the fundamental frequency.

7. The inductor-capacitor resonant cavity of claim 5, wherein the inductor-capacitor resonant cavity is configured as a load of a mixer, the mixer being configured to mix a first differential signal and a second differential signal, wherein the second differential signal has the fundamental frequency.

8. An inductor-capacitor resonant cavity, comprising a primary octet inductor and a series inductor-capacitor network, the primary octet inductor and the series inductor-capacitor network being connected in parallel, spanning between a first node and a second node, and fabricated on a substrate using a multilayer structure layout, wherein: Due to the symmetrical layout, the magnetic coupling between the primary octet inductor and the series inductor-capacitor network is reduced, and the resonant frequency of the series inductor-capacitor network is equal to three times the resonant frequency of the inductor-capacitor resonant cavity.

9. The inductor-capacitor resonant cavity as claimed in claim 8, wherein the primary 8-shaped inductor comprises a first quadrant inductor, a second quadrant inductor, a third quadrant inductor, and a fourth quadrant inductor connected in series, wherein the third quadrant inductor and the first quadrant inductor are mirror images of each other with respect to a plane of symmetry; and the second quadrant inductor and the fourth quadrant inductor are mirror images of each other with respect to the plane of symmetry.

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