Large-scale low-latency, high-bandwidth channel simulation devices and methods

Abstract

This application discloses a large-scale, low-latency, high-bandwidth channel simulation device and method, belonging to the field of wireless information transmission technology. This channel simulation device, by using a receiving computing array as the basic unit, plus digital synthesis and radio frequency transmission units, allows for flexible scaling in large-scale, high-bandwidth, fully connected channel simulations while maintaining low processing latency. This application solves the technical problems of existing technologies in flexibly scaling up and handling large latency issues when performing large-scale, high-bandwidth, fully connected channel simulations.

Description

Technical Field

[0001] This application relates to the field of wireless information transmission technology, and more specifically, to a large-scale low-latency, high-bandwidth channel simulation device and method. Background Technology

[0002] With the development of MIMO technology and the increase in the number of communication devices in the system, small-scale channel simulation equipment can no longer meet the needs of field testing, and large-scale channel simulation equipment needs to be built.

[0003] In existing technologies for constructing large-scale, low-latency, high-bandwidth channel simulation equipment, after completing the analog-to-digital conversion of the radio frequency (RF) signal, a method of interconnecting small-scale channel simulation devices is typically used to enable the digital sampled signal to perform digital simulation calculations through the channel simulation devices of each sub-channel. Currently, two main methods are adopted. The first method is to divide the RF signal equally using a power divider and then connect it to each small-scale channel simulator. After down-conversion sampling by the channel simulator, channel simulation calculations are performed, followed by up-conversion from digital to analog to complete the RF output, and then signal synthesis is performed through a power combiner. The second method is to separate the RF and digital processing units of the small-scale channel simulators. The RF units of each small-scale channel simulator are combined into the RF part of the large-scale channel simulation equipment. The RF part performs up-conversion, up-conversion, and analog-to-digital conversion functions. The digital output of the RF part enters the subsequent digital processing unit to complete the channel simulation calculations and then returns to the RF part. However, both methods have certain drawbacks. The first method is simple to implement, but to meet the computational resources required for large-scale channel simulation, the number of RF channels needs to increase exponentially, leading to increased costs and wasted RF resources. The second method, in order to meet the high-speed transmission requirements of large-bandwidth signals, generally uses high-speed serial interfaces for signal connection. However, this method requires multiple serial-to-parallel or parallel-to-serial conversions, introducing significant processing latency. Furthermore, during large-scale channel simulation, the need for multiple data exchanges between basic channel simulation computational units further increases processing latency, making it difficult to meet the low-latency requirements in certain scenarios.

[0004] In related technologies, such as Chinese patent document (CN105337677A), a method and apparatus for simulating high-bandwidth massive MIMO channels are described. This apparatus consists of several basic analog two-input, two-output channel units. The input signal to be simulated can enter the channel fading simulator of this unit for channel simulation, or it can be relayed to other units via cascaded transmit channels for simulation. The simulated output signal can be converted into a simulated baseband signal by a digital-to-analog converter, or it can be cascaded through receive channels for intermediate results to be merged by the next-level unit. This basic unit provides synchronization for the transmission of various data signals through synchronization and timing modules, achieving data alignment at the single-module and system levels. Although it meets the requirements of massive MIMO channel simulation, it still requires data exchange and alignment between basic channel simulation calculations, resulting in significant processing delays.

[0005] There are currently no effective solutions to the problems existing in the relevant technologies. Summary of the Invention

[0006] The main objective of this application is to provide a large-scale, low-latency, high-bandwidth channel simulation device and method to solve the problem that existing technologies are difficult to flexibly expand and handle large latency when performing large-scale, high-bandwidth, fully connected channel simulations.

[0007] To achieve the above objectives, according to one aspect of this application, a large-scale low-latency, high-bandwidth channel simulation apparatus is provided, comprising:

[0008] K receiving and computing arrays, each receiving and computing array containing 1 radio frequency receiving unit, M electro-optical conversion units, M optical splitting units, L photoelectric conversion units and L channel simulation computing units connected in sequence, to complete the reception of M radio frequency signals and the simulation calculation of M×LN logic channels;

[0009] L digital synthesis units, each containing K computational data input ports and 1 computational data output port, are used to synthesize K intermediate computational results;

[0010] L radio frequency (RF) transmission units, each containing one computational data input port and N RF output ports, are used for down-conversion and digital-to-analog conversion of digital signals;

[0011] After the radio frequency input signal is received and sampled by the radio frequency receiving unit, it is converted by an electro-optical conversion unit, then copied by an optical splitter unit and sent to each opto-optical conversion unit. The opto-optical conversion unit converts the signal copied by each optical splitter unit and sends it to the channel simulation calculation unit for calculation. The calculation result is then sent to the digital synthesis unit for synthesis. The synthesis calculation result is finally converted and output by the radio frequency transmitting unit to complete the channel simulation between K×M transmitting antennas and L×N receiving antennas.

[0012] Furthermore, the radio frequency receiving unit includes M radio frequency input ports and M sampling data output ports, which are used to perform down-conversion and analog-to-digital conversion on the radio frequency signals.

[0013] Furthermore, the electro-optic conversion unit includes one sampling data input port and one sampling data optical output port, used to convert the input electrical signal into an optical signal output.

[0014] Furthermore, the optical splitter unit includes one sampling data optical input port and L sampling data optical output ports, used to split one optical signal into L optical signals.

[0015] Furthermore, the photoelectric conversion unit includes M sampling data optical input ports and M sampling data electrical output ports, used to convert optical signals into electrical signals.

[0016] Furthermore, the channel simulation calculation unit includes M sampling data electrical input ports and 1 calculation data output port, used to complete the simulation calculation of M×N channels.

[0017] To achieve the above objectives, according to another aspect of this application, a method for simulating large-scale, low-latency, high-bandwidth channels is provided, comprising:

[0018] S100: A large-scale channel simulation system is constructed using K receiver computing arrays, L digital synthesis units, and L radio frequency transmission units;

[0019] S200: Through the radio frequency receiving unit SR in the kth receiving calculation array k The M connected radio frequency input signals are down-converted and sampled respectively;

[0020] S300: via the j-th electro-optic conversion unit EF in the k-th receiving computing array kj The j-th radio frequency sampling data of the array is converted from an electrical signal to an optical signal through electro-optic conversion.

[0021] S400: via the j-th optical splitter unit FS in the k-th receiving and computing array. kj The j-th optical signal is divided into L identical copies, which are then sent to L photoelectric conversion units respectively.

[0022] S500: via the i-th photoelectric conversion unit FE in the k-th receiving computing array ki The i-th copy of each optical unit is photoelectrically converted to obtain the electrical signal data of all M radio frequency samples of the k-th receiving computing array;

[0023] S600: The i-th channel simulation calculation unit C in the k-th receiving calculation array. ki After receiving M sampled data, channel simulation calculations are performed on M×N logical channels to obtain an intermediate vector calculation result of dimension N, which is then sent to the digital synthesis unit DS. i ;

[0024] S700: Digital Synthesis Unit (DS) i After receiving K intermediate vector calculation results from the 1st to the Kth receiving calculation arrays, an addition operation is performed to obtain the final vector calculation result of dimension N, and this result is sent to the radio frequency transmission unit SS. i ;

[0025] S800: Radio Frequency Transmitter Unit SS i After up-conversion and digital-to-analog conversion of the data in the final vector calculation result, N radio frequency signals are output.

[0026] Furthermore, in step S200, the radio frequency receiving unit SR in the k-th receiving calculation array k The radio frequency inputs are from the (k-1)×M+1th to the k×Mthth.

[0027] Furthermore, step S600 specifically involves M sampled data points, each representing X. (k-1)×M+1 ~X k×M The i-th channel simulation calculation unit C ki The process of performing channel simulation calculations to obtain the intermediate vector calculation results is as follows:

[0028]

[0029] in, y represents the j-th intermediate vector calculation result required to obtain the i-th final vector calculation result. i×N,j h represents the j-th intermediate calculation result required to obtain the i×N-th final calculation result. i×N,k×M This represents the channel impulse response from the k×Mth RF input port to the i×Nth RF output port.

[0030] Furthermore, step S700 specifically involves the digital synthesis unit DS... i The process of adding the results of the K vector calculations to obtain the final vector calculation result is as follows:

[0031]

[0032] in, y represents the result of the i-th final vector calculation. i×N This represents the data input to the i×Nth RF output port.

[0033] Furthermore, step S800 specifically involves the radio frequency output of the radio frequency transmitting unit SSi being the (i-1)×N+1 to the i×Nth output.

[0034] The advantages of this application are: it provides a large-scale, low-latency, high-bandwidth channel simulation device and method. This channel simulation device uses a receiving computing array as the basic unit, plus digital synthesis and radio frequency transmission units, which allows for flexible scaling up when performing large-scale, high-bandwidth, fully connected channel simulations without increasing processing latency. Specifically, for every additional M RF inputs to be simulated, only one additional receiving computing array is needed; for every additional N RF outputs to be simulated, one photoelectric conversion unit and one channel simulation computing unit are added to each receiving computing array, along with one digital synthesis unit and one radio frequency transmission unit, thus achieving flexible scaling up. By using photoelectric conversion units, optical splitting units, and electro-optical conversion units, the signal splitting process is adjusted to the optical domain, reducing the number of parallel-to-serial and serial-to-parallel conversions in the digital switching process, which greatly reduces processing latency compared to electrical domain processing, and does not increase processing latency even when scaling up. Attached Figure Description

[0035] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of this application are used to explain the application and do not constitute an undue limitation of the application. In the drawings:

[0036] Figure 1 This is a schematic diagram of the structure of a large-scale low-latency, high-bandwidth channel simulation device according to an embodiment of this application;

[0037] Figure 2 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application.

[0038] 800. Electronic device; 801. Processing device; 802. ROM; 803. RAM; 804. Bus; 805. I / O interface; 806. Input device; 807. Output device; 808. Storage device; 809. Communication device. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0040] It should be noted that the terms "comprising" and "having" and any variations thereof in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0041] Furthermore, the terms "connection" and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0043] like Figure 1 As shown, the device includes a receiving and computing array for receiving radio frequency signals and performing analog calculations on the logic channel; a digital synthesis unit for synthesizing intermediate calculation results; and a radio frequency transmitting unit for down-converting and digital-to-analog conversion of digital signals to achieve radio frequency output.

[0044] Specifically, a complete large-scale low-latency, high-bandwidth channel simulation device includes K receiver computing arrays, L digital synthesis units, and L radio frequency transmission units, capable of simulating the channel between K×M transmit antennas and L×N receive antennas.

[0045] Each receiving and computing array comprises one RF receiving unit, M electro-optical conversion units, M optical splitting units, L photoelectric conversion units, and L channel analog computing units to receive M RF signals and perform analog calculations on M×LN logic channels. Each digital synthesis unit includes K computational data input ports and one computational data output port to synthesize K intermediate computational results. Each RF transmitting unit includes one computational data input port and N RF output ports for down-conversion and digital-to-analog conversion of digital signals to achieve RF output.

[0046] In a receiving computing array, the radio frequency receiving unit includes M radio frequency input ports and M sampled data output ports for down-conversion and analog-to-digital conversion of radio frequency signals; the electro-optical conversion unit includes one sampled data input port and one sampled data optical output port for converting input electrical signals into optical signals; the optical splitter unit includes one sampled data optical input port and L sampled data optical output ports for splitting one optical signal into L optical signals; each photoelectric conversion unit includes M sampled data optical input ports and M sampled data electrical output ports for converting optical signals into electrical signals; and the channel simulation computing unit includes M sampled data electrical input ports and one calculation data output port for performing simulation calculations on M×N channels.

[0047] According to an embodiment of the present invention, a method for simulating large-scale low-latency, high-bandwidth channels is provided, employing the aforementioned large-scale low-latency, high-bandwidth channel simulation apparatus. The method includes:

[0048] S100: A large-scale channel simulation system is constructed using K receiver computing arrays, L digital synthesis units, and L radio frequency transmission units;

[0049] S200: Through the radio frequency receiving unit SR in the kth receiving calculation array k The M connected radio frequency input signals are down-converted and sampled respectively;

[0050] In this step, the radio frequency input of the radio frequency receiving unit SRk in the k-th receiving calculation array is from the (k-1)×M+1 to the k×Mth.

[0051] S300: via the j-th electro-optic conversion unit EF in the k-th receiving computing array kj The j-th radio frequency sampling data of the array is converted from an electrical signal to an optical signal through electro-optic conversion.

[0052] S400: via the j-th optical splitter unit FS in the k-th receiving and computing array. kj The j-th optical signal is divided into L identical copies, which are then sent to L photoelectric conversion units respectively.

[0053] S500: via the i-th photoelectric conversion unit FE in the k-th receiving computing array ki The i-th copy of each optical unit is photoelectrically converted to obtain the electrical signal data of all M radio frequency samples of the k-th receiving computing array;

[0054] S600: The i-th channel simulation calculation unit C in the k-th receiving calculation array. ki After receiving M sampled data, channel simulation calculations are performed on M×N logical channels to obtain an intermediate vector calculation result of dimension N, which is then sent to the digital synthesis unit DS. i ;

[0055] In this step, the M sampled data are X (k-1)×M+1 ~X k×M The i-th channel simulation calculation unit C ki The process of performing channel simulation calculations to obtain the intermediate vector calculation results is as follows:

[0056]

[0057] in, y represents the j-th intermediate vector calculation result required to obtain the i-th final vector calculation result. i×N,j h represents the j-th intermediate calculation result required to obtain the i×N-th final calculation result. i×N,k×M This represents the channel impulse response from the k×Mth RF input port to the i×Nth RF output port.

[0058] S700: Digital Synthesis Unit (DS) i After receiving K intermediate vector calculation results from the 1st to the Kth receiving calculation arrays, an addition operation is performed to obtain the final vector calculation result of dimension N, and this result is sent to the radio frequency transmission unit SS. i ;

[0059] In this step, the digital synthesis unit DS i The process of adding the results of the K vector calculations to obtain the final vector calculation result is as follows:

[0060]

[0061] in, y represents the result of the i-th final vector calculation. i×N This represents the data input to the i×Nth RF output port.

[0062] S800: Radio Frequency Transmitter Unit SS i After up-conversion and digital-to-analog conversion of the data in the final vector calculation result, N radio frequency signals are output.

[0063] In this step, the radio frequency transmission unit SS i The RF outputs are from the (i-1)×N+1 to the i×Nth.

[0064] In summary, it can be seen that this application achieves the following technical effects:

[0065] (1) For each additional M RF input simulations, only one additional receiving computing array is needed; for each additional N RF output simulations, one photoelectric conversion unit and one channel simulation computing unit are added to each receiving computing array, along with one digital synthesis unit, thus achieving flexible scaling.

[0066] (2) By using photoelectric conversion unit, optical splitting unit and electro-optical conversion unit, the signal splitting process is adjusted to be carried out in the optical domain, which reduces the number of parallel-to-serial and serial-to-parallel conversions in the digital switching process. Compared with electrical domain processing, the processing delay is greatly reduced, and the processing delay will not increase even when the scale is increased.

[0067] It should be noted that the steps shown in the flowchart in the attached figure can be performed in a set of electronic devices, see reference. Figure 2 As shown,

[0068] Electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 801, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 802 or a program loaded from storage device 808 into random access memory (RAM) 803. RAM 803 also stores various programs and data required for the operation of electronic device 800. The processing device 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.

[0069] Typically, the following devices can be connected to I / O interface 805: input devices 806 including, for example, touch screens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 807 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 808 including, for example, magnetic tapes, hard disks, etc.; and communication devices 809. Communication device 809 allows electronic device 800 to communicate wirelessly or wiredly with other devices to exchange data.

[0070] Although Figure 2 An electronic device 800 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0071] Figure 2Each box shown can represent a device or multiple devices as needed.

[0072] In particular, according to some embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, some embodiments of this disclosure include a computer program product comprising a computer program carried on a computer storage medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 809, or installed from a storage device 808, or installed from a ROM 802. When the computer program is executed by the processing device 801, it performs the functions defined above in the methods of some embodiments of this disclosure.

[0073] Obviously, those skilled in the art will understand that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device, or fabricating them separately as individual integrated circuit modules, or fabricating multiple modules or steps as a single integrated circuit module. Thus, the present invention is not limited to any particular hardware and software combination.

[0074] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A large-scale low-latency, high-bandwidth channel simulation device, characterized in that: include: K receiving and computing arrays, each receiving and computing array containing 1 radio frequency receiving unit, M electro-optical conversion units, M optical splitting units, L photoelectric conversion units and L channel simulation computing units connected in sequence, to complete the reception of M radio frequency signals and the simulation calculation of M×LN logic channels; L digital synthesis units, each containing K computational data input ports and 1 computational data output port, are used to synthesize K intermediate computational results; L radio frequency (RF) transmission units, each containing one computational data input port and N RF output ports, are used for down-conversion and digital-to-analog conversion of digital signals; After the radio frequency input signal is received and sampled by the radio frequency receiving unit, it is converted by an electro-optical conversion unit, then copied by an optical splitter unit and sent to each opto-optical conversion unit. The opto-optical conversion unit converts the signal copied by each optical splitter unit and sends it to the channel simulation calculation unit for calculation. The calculation result is then sent to the digital synthesis unit for synthesis. The synthesis calculation result is finally converted and output by the radio frequency transmitting unit to complete the channel simulation between K×M transmitting antennas and L×N receiving antennas.

2. The large-scale low-latency, high-bandwidth channel simulation device according to claim 1, characterized in that: The radio frequency receiving unit includes M radio frequency input ports and M sampling data output ports, which are used to perform down-conversion and analog-to-digital conversion on radio frequency signals.

3. The large-scale low-latency, high-bandwidth channel simulation device according to claim 2, characterized in that: The electro-optic conversion unit includes one sampling data input port and one sampling data optical output port, which are used to convert the input electrical signal into an optical signal output.

4. The large-scale low-latency, high-bandwidth channel simulation device according to claim 3, characterized in that: The optical splitter unit includes one sampling data optical input port and L sampling data optical output ports, which are used to split one optical signal into L optical signals.

5. The large-scale low-latency, high-bandwidth channel simulation device according to claim 4, characterized in that: The photoelectric conversion unit includes M sampling data optical input ports and M sampling data electrical output ports, used to convert optical signals into electrical signals.

6. The large-scale low-latency, high-bandwidth channel simulation device according to claim 5, characterized in that: The channel simulation calculation unit includes M sampling data electrical input ports and 1 calculation data output port, which is used to complete the simulation calculation of M×N channels.

7. A method for simulating large-scale, low-latency, high-bandwidth channels, characterized in that: The large-scale low-latency, high-bandwidth channel simulation apparatus according to any one of claims 1 to 6 includes the following steps: S100: A large-scale channel simulation system is constructed using K receiver computing arrays, L digital synthesis units, and L radio frequency transmission units; S200: Through the radio frequency receiving unit SR in the kth receiving calculation array k The M connected radio frequency input signals are down-converted and sampled respectively; S300: via the j-th electro-optic conversion unit EF in the k-th receiving computing array kj The j-th radio frequency sampling data of the array is converted from an electrical signal to an optical signal through electro-optic conversion. S400: via the j-th optical splitter unit FS in the k-th receiving and computing array. kj The j-th optical signal is divided into L identical copies, which are then sent to L photoelectric conversion units respectively. S500: via the i-th photoelectric conversion unit FE in the k-th receiving computing array ki The i-th copy of each optical unit is photoelectrically converted to obtain the electrical signal data of all M radio frequency samples of the k-th receiving computing array; S600: The i-th channel simulation calculation unit C in the k-th receiving calculation array. ki After receiving M sampled data, channel simulation calculations are performed on M×N logical channels to obtain an intermediate vector calculation result of dimension N, which is then sent to the digital synthesis unit DS. i ; S700: The digital synthesis unit DSi receives the K intermediate vector calculation results from the 1st to the Kth receiver calculation arrays, performs addition operations to obtain the final vector calculation result of dimension N, and sends the result to the radio frequency transmission unit SS. i ; S800: Radio Frequency Transmitter Unit SS i After up-conversion and digital-to-analog conversion of the data in the final vector calculation result, N radio frequency signals are output.

8. The large-scale low-latency, high-bandwidth channel simulation method according to claim 7, characterized in that: In step S200, the radio frequency receiving unit SR in the k-th receiving calculation array k The radio frequency inputs are from the (k-1)×M+1th to the k×Mthth.

9. The large-scale low-latency, high-bandwidth channel simulation method according to claim 8, characterized in that: In step S600, the M sampled data are X (k-1)×M+1 ~X k×M The i-th channel simulation calculation unit C ki The process of performing channel simulation calculations to obtain the intermediate vector calculation results is as follows: in, y represents the j-th intermediate vector calculation result required to obtain the i-th final vector calculation result. i×N,j h represents the j-th intermediate calculation result required to obtain the i×N-th final calculation result. i×N,k×M This represents the channel impulse response from the k×Mth RF input port to the i×Nth RF output port.

10. The large-scale low-latency, high-bandwidth channel simulation method according to claim 9, characterized in that: In step S700, the digital synthesis unit DS i The process of adding the results of the K vector calculations to obtain the final vector calculation result is as follows: in, y represents the result of the i-th final vector calculation. i×N This represents the data input to the i×Nth RF output port.

11. The large-scale low-latency, high-bandwidth channel simulation method according to claim 10, characterized in that: In step S800, the radio frequency transmitting unit SS i The RF outputs are from the (i-1)×N+1 to the i×Nth.

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