Semiconductor element with mask lines to suppress signal cross-talk

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate having a surface, a first signal line disposed on the surface of the substrate, and a second signal line disposed on the surface of the substrate and spaced apart from the first signal line. The semiconductor device also includes a first mask line between the first signal line and the second signal line. A minimum distance between the first signal line and the second signal line is equal to or less than about 90 nanometers (nm).

Description

[0001] Cross-references

[0002] This application claims priority to U.S. Patent Applications Nos. 17 / 679,302 and 17 / 679,482 (i.e., priority date “February 24, 2022”), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device. In particular, it relates to a semiconductor device having mask lines (mask lines) to suppress signal crosstalk. Background Technology

[0004] Typical memory elements (such as dynamic random access memory (DRAM) elements) include signal lines, such as word lines and bit lines that cross word lines.

[0005] As DRAM devices shrink, the size and / or spacing of signal lines become smaller, making capacitive coupling and / or inductive magnetic coupling more significant. Electromagnetic noise or crosstalk between signal lines may also become more severe, thus degrading device performance.

[0006] The description of the "prior art" above is only for background information and does not constitute an admission that the description of the "prior art" above discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the "prior art" above should be considered part of this disclosure. Summary of the Invention

[0007] One aspect of this disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a surface; a first signal line disposed on the surface of the substrate; and a second signal line disposed on the surface of the substrate and spaced apart from the first signal line. The semiconductor device further includes a first mask line between the first signal line and the second signal line. The minimum distance between the first signal line and the second signal line is equal to or less than about 90 nanometers (nm).

[0008] Another aspect of this disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a surface; a first signal line disposed on the surface of the substrate; and a second signal line disposed on the surface of the substrate and spaced apart from the first signal line. The semiconductor device further includes a first mask line between the first signal line and the second signal line. The minimum distance between the first signal line and the first mask line is equal to or less than about 40 nanometers.

[0009] Another aspect of this disclosure provides a method for fabricating a semiconductor device. The method includes: disposing a mandrel layer on a dielectric layer and patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. The minimum distance between the first mandrel and the second mandrel is equal to or less than about 90 nanometers. The method further includes: forming a first spacer adjacent to a first side of the first mandrel, a second spacer adjacent to a second side of the first mandrel, a third spacer adjacent to a first side of the second mandrel, and a fourth spacer adjacent to a second side of the second mandrel. The method further includes: using the first spacer, the second spacer, the third spacer, and the fourth spacer as etching masks to etch the dielectric layer to form a first dielectric element, a second dielectric element, a third dielectric element, and a fourth dielectric element. The method further includes: forming a first mask line between the second dielectric element and the third dielectric element.

[0010] By creating a dummy line between two signal lines (such as an aggressor line and a victim line) and connecting the dummy line to the power supply or ground, electromagnetic noise or crosstalk between signal lines can be reduced or prevented.

[0011] Furthermore, the fabrication techniques for dummy lines and signal lines can include a pitch doubling process, such as a self-aligned pitch doubling technique or a self-aligned double patterning technique. Compared to existing photolithography techniques, the process disclosed herein overcomes scaling-related photolithography problems and creates denser memory arrays. Therefore, device performance can be improved.

[0012] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0013] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0014] Figure 1A This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0015] Figure 1BThis is a top view schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0016] Figure 2 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0017] Figure 3 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0018] Figure 4A These are one or more stages of a method for fabricating a semiconductor element, which exemplifies some embodiments of this disclosure.

[0019] Figure 4B These are one or more stages of a method for fabricating a semiconductor element, which exemplifies some embodiments of this disclosure.

[0020] Figure 4C These are one or more stages of a method for fabricating a semiconductor element, which exemplifies some embodiments of this disclosure.

[0021] Figure 4D These are one or more stages of a method for fabricating a semiconductor element, which exemplifies some embodiments of this disclosure.

[0022] Figure 4E These are one or more stages of a method for fabricating a semiconductor element, which exemplifies some embodiments of this disclosure.

[0023] Figure 4F These are one or more stages of a method for fabricating a semiconductor element, which exemplifies some embodiments of this disclosure.

[0024] Figure 4G These are one or more stages of a method for fabricating a semiconductor element, which exemplifies some embodiments of this disclosure.

[0025] Figure 4H These are one or more stages of a method for fabricating a semiconductor element, which exemplifies some embodiments of this disclosure.

[0026] Figure 4I These are one or more stages of a method for fabricating a semiconductor element, which exemplifies some embodiments of this disclosure.

[0027] Figure 4J These are one or more stages of a method for fabricating a semiconductor element, which exemplifies some embodiments of this disclosure.

[0028] Figure 4K These are one or more stages of a method for fabricating a semiconductor element, which exemplifies some embodiments of this disclosure.

[0029] Figure 5 This is a flowchart illustrating methods for fabricating semiconductor elements according to some embodiments of this disclosure.

[0030] Explanation of reference numerals in the attached figures:

[0031] 1: Semiconductor components

[0032] 2: Semiconductor components

[0033] 3: Semiconductor components

[0034] 10: Base

[0035] 11: Conductive elements

[0036] 12: Signal line

[0037] 13: Dielectric elements

[0038] 13': Dielectric element

[0039] 14: Mask structure

[0040] 14a: Mask line

[0041] 14b: Mask line

[0042] 14c: Mask line

[0043] 15: Signal line

[0044] 16: Dielectric elements

[0045] 16': Dielectric element

[0046] 40: Dielectric layer

[0047] 41: Etching Stop Layer

[0048] 42: Core layer

[0049] 42a: Mandrel

[0050] 42b: Mandrel

[0051] 43: Mask layer

[0052] 43p: Mask pattern

[0053] 44: Conformal interstitial sublayer

[0054] 44a: Spacer

[0055] 44a': Spacer

[0056] 44b: Spacer

[0057] 44b': Spacer

[0058] 50: Preparation method

[0059] 101: Surface

[0060] 121: Side view

[0061] 122: Side view

[0062] 151: Side View

[0063] 152: Side View

[0064] 421: Side view

[0065] 422: Side view

[0066] 423: Side view

[0067] 424: Side View

[0068] S51: Steps

[0069] S52: Steps

[0070] S53: Steps

[0071] S54: Steps

[0072] S55: Steps

[0073] w1: Width

[0074] w2: width

[0075] w3: width

[0076] w4: width

[0077] w5: width Detailed Implementation

[0078] The embodiments or examples of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that this is not intended to limit the scope of the disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as things that would be commonly done by one of ordinary skill in the art to which this disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same reference numerals.

[0079] It should be understood that although the terms first, second, third, etc., can be used to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below can be referred to as the second element, component, region, layer, or part without departing from the teachings of the present invention.

[0080] The terminology used herein is for describing specific embodiments only and is not intended to limit the scope of the invention. As used herein, the singular forms “a,” “an,” and “the” include multiple forms unless the context clearly indicates otherwise. It should be further understood that the terms “comprising” and “including,” when used in this specification, indicate the presence of the stated feature, integer, step, operation, element, or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0081] Figure 1 is a cross-sectional schematic diagram illustrating a semiconductor element 1 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 1 may include a circuit, such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory cell (DRAM cell).

[0082] Furthermore, semiconductor element 1 may be or may include part of an integrated circuit (IC) chip, which includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0083] As shown in FIG1, in some embodiments, semiconductor element 1 may include substrate 10, conductive element 11, signal lines 12, 15, dielectric elements 13, 13', 16, 16', and mask lines 14a, 14b, and 14c.

[0084] In some embodiments, the substrate 10 may include, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials. In other embodiments, the substrate 10 may include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0085] Depending on the IC fabrication stage, the substrate 10 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form an IC feature (e.g., doped region, isolation feature, gate feature, source or drain feature, interconnect feature, other feature, or combination thereof).

[0086] For example, conductive element 11 can be disposed in substrate 10. The fabrication technique of conductive element 11 can be derived from a doped region of a bulk semiconductor substrate or an epitaxial layer. Conductive element 11 can be electrically connected to, for example, the terminals of a MOSFET (such as gate, source, or drain), the terminals of a BJT (such as emitter, collector, or base), or other IC features (such as DRAM cells) in semiconductor element 1.

[0087] The conductive element 11 may be at least partially exposed from the substrate 10. Signal lines 12 and 15 may be electrically connected to one or more conductive elements 11 to control the operation of the semiconductor element 1 (such as a DRAM cell).

[0088] In some embodiments, the operation of semiconductor element 1 may include a state change from binary one to binary zero, or vice versa. For example, a state change may involve the accumulation and / or storage of a charge, or the release of a stored charge.

[0089] In some embodiments, the conductive element 11 may include, for example, polysilicon (poly-Si), metals (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.), or metal alloys. In some embodiments, the conductive element 11 may include, for example, titanium substrates (such as titanium nitride (TiN) or titanium aluminum nitride (TiAlN)), tantalum substrates (such as tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), or tantalum carbide (Ta2C)), or silicides (such as PtSi, TiSi2, CoSi, NiSi, MoSi2, TaSi, WSi2, etc.).

[0090] Although the figure illustrates two conductive elements, it is understood that semiconductor element 1 may include any suitable number of conductive elements.

[0091] Signal line 12 may be disposed on surface 101 of substrate 10. Signal line 12 may be electrically connected to conductive element 11. The width "w2" of signal line 12 is measured in a direction substantially parallel to surface 101 of substrate 10. Width w2 may be equal to or less than about 20 nanometers (nm). In some embodiments, width w2 may be greater than the width "w1" of conductive element 11 measured in a direction substantially parallel to surface 101 of substrate 10. However, in other embodiments, width w2 may be equal to or less than width w1.

[0092] Signal line 15 may be disposed on surface 101 of substrate 10 and spaced apart from signal line 12. Signal line 15 may be electrically connected to conductive elements in substrate 10. Signal line 15 may have a width substantially equal to the width w2 of signal line 12.

[0093] Signal line 12 and signal line 15 can each be part of the word line and bit line of semiconductor element 1, respectively. Signal line 12 and signal line 15 can each be, for example, polysilicon (poly-Si), metal (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.), or metal alloy.

[0094] Although the diagram illustrates two signal lines, it is understood that semiconductor element 1 may include any suitable number of signal lines.

[0095] Signal line 12 may have a side 121 and a side 122 opposite to side 121. Side 121 and side 122 may each be substantially perpendicular to surface 101 of substrate 10. Signal line 15 may have a side 151 and a side 152 opposite to side 151. Side 151 and side 152 may each be substantially perpendicular to surface 101 of substrate 10.

[0096] In some embodiments, the minimum distance “w5” between signal line 12 and signal line 15 is measured in a direction substantially parallel to the surface 101 of substrate 10. For example, the minimum distance w5 can be measured between the side 122 of signal line 12 and the side 151 of signal line 15. The minimum distance w5 can be equal to or less than about 90 nanometers.

[0097] Dielectric element 13 may contact, cover, seal, or encapsulate the side 121 of signal line 12. Dielectric element 13' may contact, cover, seal, or encapsulate the side 122 of signal line 12. Dielectric element 16 may contact, cover, seal, or encapsulate the side 151 of signal line 15. Dielectric element 16' may contact, cover, seal, or encapsulate the side 152 of signal line 15.

[0098] In some embodiments, dielectric element 13, dielectric element 13', dielectric element 16, and dielectric element 16' may each be a spacer. In some embodiments, dielectric element 13, dielectric element 13', dielectric element 16, and dielectric element 16' may each comprise, for example, nitride, oxide, oxynitride amorphous silicon, polycrystalline silicon, or materials suitable for use with materials such as... Figure 4HAnother material required for patterning operations. Exemplary interstitial materials may include, but are not limited to, hafnium silicate (HfSiOx), hafnium oxide (HfO2), zirconium silicate (ZrSiOx), zirconium oxide (ZrO2), silicon nitride (Si3N4), silicon oxynitride (SiON) or silicon oxide (SiO2), tetrachlorosilicic acid (TEOS), carbon-doped silicon, etc.

[0099] In some embodiments, dielectric element 13, dielectric element 13', dielectric element 16 and dielectric element 16' may each be a single-layer structure.

[0100] The width “w3” of each of dielectric elements 13, 13', 16, and 16' is measured in a direction substantially parallel to the surface 101 of the substrate 10. The width w3 may be equal to or less than about 40 nanometers. For example, the width w3 may be between about 10 nanometers and about 40 nanometers. In some embodiments, dielectric elements 13, 13', 16, and 16' may have the same width.

[0101] Mask lines 14a, 14b, and 14c can each be disposed on the surface 101 of the substrate 10. Mask lines 14a, 14b, and 14c can be part of the mask structure 14. Mask lines 14a, 14b, and 14c can be electrically connected to each other. Mask lines 14a, 14b, and 14c can be connected to a power supply or ground.

[0102] Mask lines 14a and 14b can be positioned on opposite sides of signal line 12. Signal line 12 can be positioned between mask lines 14a and 14b. Mask line 14b can be positioned between signal line 12 and signal line 15. Mask lines 14b and 14c can be positioned on opposite sides of signal line 15. Signal line 15 can be positioned between mask lines 14b and 14c.

[0103] Mask lines 14a, 14b and 14c can be referred to as dummy lines.

[0104] Mask lines 14a, 14b, and 14c may not be used to form a conductive interconnect with conductive element 11. In contrast, signal lines 12 and 15 may be disposed on conductive element 11 and may be used to form a conductive interconnect with conductive element 11.

[0105] Mask lines 14a, 14b, and 14c can be configured to provide electromagnetic interference (EMI) mask protection for signal lines 12 and 15. For example, mask lines 14a, 14b, and 14c can be configured to provide an EMI mask to prevent signal line 12 from being interfered with by signal line 15, and vice versa.

[0106] Mask lines 14a, 14b, and 14c may each comprise, for example, polysilicon (poly-Si), a metal (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.), or a metal alloy. Mask lines 14a, 14b, and 14c may be made of the same material. Mask lines 14a, 14b, and 14c may have the same material as signal lines 12 and 15. In some embodiments, mask lines 14a, 14b, and 14c may be formed in the same operation as signal lines 12 and 15.

[0107] The width w3 of dielectric element 13 can be the minimum distance between mask line 14a and signal line 12. The width w3 of dielectric element 13' can be the minimum distance between mask line 14b and signal line 12. The width w3 of dielectric element 16 can be the minimum distance between mask line 14b and signal line 15. The width w3 of dielectric element 16' can be the minimum distance between mask line 14c and signal line 15.

[0108] The width "w4" of each of mask lines 14a, 14b, and 14c is measured in a direction substantially parallel to the surface 101 of the substrate 10. Width w4 may be equal to or less than about 70 nanometers. For example, width w4 may be between about 10 nanometers and 70 nanometers. In some embodiments, width w4 may be the minimum width of each of mask lines 14a, 14b, and 14c. In some embodiments, width w4 may be defined by a pitch multiplication process, such as a self-aligned pitch doubling technique or a self-aligned double patterning technique. In some embodiments, width w4 may be greater than width w3.

[0109] In some embodiments, the minimum distance w5 between signal line 12 and signal line 15 may be the sum of the width w4 of mask line 14b, the width w3 of dielectric element 13', and the width w3 of dielectric element 16.

[0110] As described, the width w3 can be between approximately 10 nanometers and approximately 40 nanometers, and the width w4 can be between approximately 10 nanometers and approximately 70 nanometers. However, the minimum distance w5 between signal line 12 and signal line 15 remains equal to or less than approximately 90 nanometers.

[0111] As DRAM devices (such as semiconductor device 1) shrink, the size and / or spacing of signal lines become smaller, making capacitive coupling and / or inductive magnetic coupling more significant. Electromagnetic noise or crosstalk between signal lines can become severe, thus degrading device performance.

[0112] According to some embodiments of this disclosure, by forming a dummy line between two signal lines (such as an aggressor line and a victim line) and connecting the dummy line to a power supply or ground, electromagnetic noise or crosstalk between signal lines can be reduced or prevented.

[0113] Furthermore, the fabrication techniques for dummy lines and signal lines include a pitch doubling process, such as a self-aligned pitch doubling technique or a self-aligned double patterning technique. Compared to existing photolithography techniques, the process disclosed herein overcomes scaling-related photolithography problems and creates denser memory arrays. Therefore, device performance can be improved.

[0114] Figure 1B This is a top view schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure. In some embodiments, such as Figure 1A The sectional view shown (or as shown) Figure 2 The sectional view shown, or as shown Figure 3 The sectional view shown may be Figure 1B A cross-sectional view of a portion of the semiconductor element shown.

[0115] For example, Figure 1A The semiconductor element 1 shown can be a top view emphasized by a dashed box. For example, Figure 1A The semiconductor element 1 shown can be formed around a periphery of a memory array. In some embodiments, the circuit density of this periphery can be less than the density of the memory array (e.g., densely spaced regions). For example, the minimum distance between signal line 12 and signal line 15 can be greater than the minimum distance between two lines in the memory array.

[0116] In some embodiments, such as Figure 1A The sectional view shown (or as shown) Figure 2 The sectional view shown, or as shown Figure 3The cross-sectional view shown can be in two directions, the "X" direction (corresponding to the direction in which the character line extends) and the "Y" direction (corresponding to the direction in which the bit line extends). In some embodiments, the character line direction may be substantially orthogonal to the bit line direction. In other embodiments, the character line direction may not be orthogonal to the bit line direction.

[0117] In some embodiments, the signal lines (such as signal lines 12 and 15) of the semiconductor element 1 may be parallel. In some embodiments, the mask lines (such as mask lines 14a, 14b, and 14c) of the semiconductor element 1 may be parallel. In some embodiments, the signal lines and mask lines of the semiconductor element 1 may be parallel.

[0118] Figure 2 This is a cross-sectional schematic diagram illustrating a semiconductor element 2 according to some embodiments of the present disclosure. Figure 2 Semiconductor element 2 and Figure 1A The semiconductor element 1 is similar, except for the differences described below.

[0119] exist Figure 2 In this process, the width w3 of each of dielectric element 13, dielectric element 13', dielectric element 16 and dielectric element 16' can be greater than the width w4 of each of mask line 14a, mask line 14b and mask line 14c.

[0120] Figure 3 This is a cross-sectional schematic diagram illustrating a semiconductor element 3 according to some embodiments of the present disclosure. Figure 3 Semiconductor element 3 and Figure 1A The semiconductor element 1 is similar, except for the differences described below.

[0121] exist Figure 3 In this context, the width w3 of each of dielectric element 13, dielectric element 13', dielectric element 16 and dielectric element 16' can be substantially equal to the width w4 of each of mask lines 14a, mask lines 14b and mask lines 14c.

[0122] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J and Figure 4K These figures illustrate stages of methods for fabricating semiconductor devices according to some embodiments of this disclosure. To better understand various aspects of this disclosure, at least some of these figures have been simplified. In some embodiments, Figure 1A Semiconductor components 1, Figure 2 Semiconductor element 2 and Figure 3 Semiconductor element 3 in the middle can be accessed through the following information: Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J and Figure 4K The preparation is done using the following methods.

[0123] Reference Figure 4A A substrate 10 is provided, and one or more conductive elements 11 may be formed in the substrate 10. The conductive elements 11 may be fabricated from a doped region of a block semiconductor substrate or an epitaxial layer. The conductive elements 11 may be at least partially exposed from the substrate 10.

[0124] In some embodiments, the fabrication techniques for the shallow trench isolation (STI) region (not shown in the figure) may include, for example, photolithography, etching, deposition, and chemical mechanical polishing (CMP) processes to form within the substrate 10 to electrically isolate subsequently formed signal lines.

[0125] A dielectric layer 40 may be disposed on the surface 101 of the substrate 10. In some embodiments, the dielectric layer 40 may be disposed on the surface 101 of the substrate 10 in a blanket-like manner. In some embodiments, the fabrication technique of the dielectric layer 40 may include a thermal oxidation operation, a chemical vapor deposition (CVD) operation, a low-pressure chemical vapor deposition (LPCVD) operation, a plasma-enhanced chemical vapor deposition (PECVD) operation, other feasible operations, or combinations thereof. The dielectric layer 40 may include the features listed above for... Figure 1A The materials of dielectric element 13, dielectric element 13', dielectric element 16 and dielectric element 16'.

[0126] The mandrel layer 42 may be disposed on the dielectric layer 40. The mandrel layer 42 may be disposed on the dielectric layer 40 in a blanket-like manner. In some embodiments, the fabrication technique of the mandrel layer 42 may include a thermal oxidation operation, a CVD operation, an LPCVD operation, a PECVD operation, other feasible operations, or combinations thereof. The mandrel layer 42 may include, for example, nitrides, oxides, oxynitride amorphous silicon, polycrystalline silicon, or other materials suitable for use such as... Figure 4C Materials required for patterning operations.

[0127] In some embodiments, an etch stop layer 41 may be formed on the dielectric layer 40 prior to the formation of the mandrel layer 42. In other embodiments, the etch stop layer 41 may be omitted. For the sake of brevity, the case of the etch stop layer 41 is not described in the following operations.

[0128] Reference Figure 4B The mask layer 43 can be disposed on the mandrel layer 42. The mask layer 43 may include, for example, nitrides, oxides, oxynitride amorphous silicon, polycrystalline silicon, or other materials suitable for use with materials such as... Figure 4C The material for the patterning operation shown. In some embodiments, the fabrication technique of the mask layer 43 may include, for example, a CVD operation, an LPCVD operation, a PECVD operation, other feasible operations, or combinations thereof.

[0129] In some embodiments, a photoresist (not shown) and another sacrificial mask material, such as an anti-reflective coating (ARC) material, may be deposited on the mask layer 43.

[0130] Reference Figure 4C The patterning technique for mask layer 43 may include photolithography and etching processes to form mask pattern 43p. The patterning technique for mandrel layer 42 may include using mask pattern 43p as an etching mask. Therefore, mandrels 42a and 42b can be formed.

[0131] In some embodiments, the mask layer 43 and the mandrel layer 42 may be etched anisotropically. In some embodiments, the mask layer 43 and the mandrel layer 42 may be etched in the same operation. In some embodiments, the mask layer 43 and the mandrel layer 42 may be etched in different operations. For example, the etching technique for the mask layer 43 and the mandrel layer 42 may include, for example, using reactive ion etching (RIE) with different chemical substances.

[0132] Mandrels 42a and 42b may have related Figure 1A The width w2 is described. Width w2 can be equal to or less than approximately 20 nanometers. Mandrels 42a and 42b can be spaced apart by a minimum distance w5, such as... Figure 1A The minimum distance w5 can be equal to or less than approximately 90 nanometers.

[0133] The spindle 42a may have a side 421 and a side 422 opposite to the side 421. The spindle 42b may have a side 423 and a side 424 opposite to the side 423.

[0134] Reference Figure 4D The removal technique for removing the mask pattern 43p from the mandrels 42a and 42b may include, for example, an etching process.

[0135] Reference Figure 4EA conformal spacer sublayer 44 may be disposed on the dielectric layer 40 to cover the mandrels 42a and 42b. The fabrication techniques for the conformal spacer sublayer 44 may include silicon nitride, silicon oxide, silicon oxynitride, or any type of organic or inorganic material with etch selectivity relative to the mandrels 42a and 42b. The fabrication techniques for the conformal spacer sublayer 44 may include, for example, atomic layer deposition (ALD), CVD, LPCVD, PECVD, other feasible operations, or combinations thereof.

[0136] Reference Figure 4F The conformal spacer layer 44 may be partially removed to form spacers 44a adjacent to side 421 of mandrel 42a, spacers 44a' adjacent to side 422 of mandrel 42a, spacers 44b adjacent to side 423 of mandrel 42b, and spacers 44b' adjacent to side 424 of mandrel 42b. For example, the etching technique for the conformal spacer layer 44 may include RIE operations based on chemical substances CHF3 or CF4 to etch silicon oxide or silicon oxynitride, or etching silicon nitride based on CHF3 / O2.

[0137] Spacer 44a, spacer 44a', spacer 44b and spacer 44b' are each formed in relation to Figure 1A The width w3 is described. The width w3 can be equal to or less than approximately 40 nanometers. For example, the width w3 can be between approximately 10 nanometers and approximately 40 nanometers.

[0138] Since the minimum distance w5 between signal line 12 and signal line 15 is kept equal to or less than about 90 nanometers, the width w4 can be between about 10 nanometers and about 70 nanometers.

[0139] Reference Figure 4G The spindles 42a and 42b can be removed from the dielectric layer 40, leaving spacers 44a, 44a', 44b, and 44b' on the dielectric layer 40. For example, the etching technique for the spindles 42a and 42b can include a RIE operation.

[0140] Removing mandrels 42a and 42b results in the formation of a gap between spacers 44a and 44a', and a gap between spacers 44b and 44b'. The width w2 of mandrels 42a and 42b can be controlled to determine the width w2 of the gap.

[0141] Reference Figure 4H The patterning technique for dielectric layer 40 may include etching using spacers 44a, 44a', 44b, and 44b' as etching masks. Therefore, dielectric elements 13, 13', 16, and 16' can be formed.

[0142] Dielectric element 13, dielectric element 13', dielectric element 16 and dielectric element 16' each form related to Figure 1A The width w3 is described. The width w3 can be equal to or less than approximately 40 nanometers. For example, the width w3 can be between approximately 10 nanometers and 40 nanometers.

[0143] Reference Figure 4I The removal techniques for spacers 44a, 44a', 44b and 44b' may include, for example, an etching process.

[0144] Reference Figure 4J A conductive layer 45 can be disposed on the substrate 10 to cover dielectric elements 13, 13', 16, and 16'. The conductive layer 45 may include, for example, polysilicon (poly-Si), metals (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.), or metal alloys. The fabrication techniques for the conductive layer 45 may include, for example, an ALD operation, a CVD operation, an LPCVD operation, a PECVD operation, other feasible operations, or combinations thereof.

[0145] Reference Figure 4K The conductive layer 45 can be partially removed to form mask lines 14a, 14b, and 14c. Furthermore, the fabrication of signal lines 12 and 15 can be included in the same operation.

[0146] The width w4 can be defined by a pitch doubling process, such as a self-aligned pitch doubling technique or a self-aligned dual patterning technique. Since the minimum distance w5 between signal line 12 and signal line 15 remains equal to or less than about 90 nanometers, the width w4 can be between about 10 nanometers and about 70 nanometers.

[0147] Figure 5 This is a flowchart illustrating a method 50 for fabricating a semiconductor element according to some embodiments of this disclosure.

[0148] In some embodiments, the fabrication method 50 may include step S51, which involves depositing a mandrel layer on a dielectric layer. For example, such as Figure 4A As shown, the mandrel layer 42 can be disposed on the dielectric layer 40.

[0149] In some embodiments, the fabrication method 50 may include step S52, patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. For example, as Figure 4C As shown, the patterning technique for the mandrel layer 42 may include etching using a mask pattern 43p as an etch. Therefore, mandrels 42a and 42b can be formed. In some embodiments, the minimum distance w5 between mandrels 42a and 42b is equal to or less than about 90 nanometers.

[0150] In some embodiments, the preparation method 50 may include step S53, forming a first spacer adjacent to a first side of the first mandrel, a second spacer adjacent to a second side of the first mandrel, a third spacer adjacent to a first side of the second mandrel, and a fourth spacer adjacent to a second side of the second mandrel. For example, such as Figure 4F As shown, the conformal spacer layer 44 can be partially removed to form spacer 44a adjacent to side 421 of mandrel 42a, spacer 44a' adjacent to side 422 of mandrel 42a, spacer 44b adjacent to side 423 of mandrel 42b, and spacer 44b adjacent to side 424 of mandrel 42b.

[0151] In some embodiments, the fabrication method 50 may include step S54, using the first spacer, the second spacer, the third spacer, and the fourth spacer as etching masks to etch the dielectric layer to form a first dielectric element, a second dielectric element, a third dielectric element, and a fourth dielectric element. For example, such as Figure 4H As shown, the patterning technique for dielectric layer 40 may include etching using spacers 44a, 44a', 44b, and 44b' as etching masks. Therefore, dielectric elements 13, 13', 16, and 16' can be formed.

[0152] In some embodiments, the fabrication method 50 may include step S55, forming a first mask line between the second dielectric element and the third dielectric element. For example, such as Figure 4K As shown, a mask line 14b is formed between dielectric element 13' and dielectric element 16.

[0153] One aspect of this disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a surface; a first signal line disposed on the surface of the substrate; and a second signal line disposed on the surface of the substrate and spaced apart from the first signal line. The semiconductor device further includes a first mask line between the first signal line and the second signal line. The minimum distance between the first signal line and the second signal line is equal to or less than about 90 nanometers (nm).

[0154] Another aspect of this disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a surface; a first signal line disposed on the surface of the substrate; and a second signal line disposed on the surface of the substrate and spaced apart from the first signal line. The semiconductor device further includes a first mask line between the first signal line and the second signal line. The minimum distance between the first signal line and the first mask line is equal to or less than about 40 nanometers.

[0155] Another aspect of this disclosure provides a method for fabricating a semiconductor device. The method includes: disposing a mandrel layer on a dielectric layer and patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. The minimum distance between the first mandrel and the second mandrel is equal to or less than about 90 nanometers. The method further includes: forming a first spacer adjacent to a first side of the first mandrel, a second spacer adjacent to a second side of the first mandrel, a third spacer adjacent to a first side of the second mandrel, and a fourth spacer adjacent to a second side of the second mandrel. The method further includes: using the first spacer, the second spacer, the third spacer, and the fourth spacer as etching masks to etch the dielectric layer to form a first dielectric element, a second dielectric element, a third dielectric element, and a fourth dielectric element. The method further includes: forming a first mask line between the second dielectric element and the third dielectric element.

[0156] By creating a dummy line between two signal lines (such as an aggressor line and a victim line) and connecting the dummy line to the power supply or ground, electromagnetic noise or crosstalk between signal lines can be reduced or prevented.

[0157] Furthermore, the fabrication techniques for dummy lines and signal lines can include a pitch doubling process, such as a self-aligned pitch doubling technique or a self-aligned double patterning technique. Compared to existing photolithography techniques, the process disclosed herein overcomes scaling-related photolithography problems and creates denser memory arrays. Therefore, device performance can be improved.

[0158] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0159] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A substrate having a surface; A first conductive element and a second conductive element are disposed in the substrate, wherein the top surfaces of the first conductive element and the second conductive element are exposed from the surface of the substrate; A first signal line is disposed on the surface of the substrate and the top surface of the first conductive element, wherein the first signal line is electrically connected to the first conductive element, and wherein the width of the first signal line is greater than the width of the first conductive element, such that the first signal line directly contacts the surface of the substrate and the top surface of the first conductive element; A second signal line is disposed on the surface of the substrate and the top surface of the second conductive element, and spaced apart from the first signal line, wherein the second signal line is electrically connected to the second conductive element, and wherein the width of the second signal line is greater than the width of the second conductive element, such that the second signal line directly contacts the surface of the substrate and the top surface of the second conductive element; as well as A first mask line is located between the first signal line and the second signal line, wherein the first mask line is not connected to the first conductive element and the second conductive element; The minimum distance between the first signal line and the second signal line is equal to or less than 90 nanometers.

2. The semiconductor device of claim 1, wherein the first signal line, the second signal line, and the first mask line are substantially parallel.

3. The semiconductor device of claim 1, wherein the minimum width of the first mask line is between about 10 nanometers and about 70 nanometers.

4. The semiconductor device of claim 3, wherein the minimum width of the first mask line is defined by a self-aligned spacing doubling technique.

5. The semiconductor device of claim 1, wherein the minimum distance between the first signal line and the first mask line is between about 10 nanometers and about 40 nanometers.

6. The semiconductor device of claim 5, wherein the minimum distance between the first signal line and the first mask line is less than the minimum width of the first mask line.

7. The semiconductor device of claim 5, wherein the minimum distance between the first signal line and the first mask line is greater than the minimum width of the first mask line.

8. The semiconductor element of claim 5, wherein the minimum distance between the first signal line and the first mask line is substantially equal to the minimum width of the first mask line.

9. The semiconductor device of claim 1, further comprising: A second mask line, wherein the first signal line is disposed between the first mask line and the second mask line, wherein the first mask line and the second mask line are electrically connected.

10. The semiconductor device of claim 9, further comprising: A third mask line, wherein the second signal line is disposed between the first mask line and the third mask line, wherein the first mask line and the third mask line are electrically connected.

11. The semiconductor device of claim 10, wherein the first mask line, the second mask line, and the third mask line are substantially parallel.

12. The semiconductor device of claim 1, further comprising: A first dielectric element is in contact with a first side of the first signal line; as well as A second dielectric element is in contact with a second side of the first signal line, the second side being opposite to the first side.

13. The semiconductor element of claim 12, wherein the minimum width of the first dielectric element is substantially equal to the minimum width of the second dielectric element.

14. The semiconductor element of claim 12, wherein the first side and the second side of the first signal line are substantially perpendicular to the surface of the substrate.

15. A semiconductor element, comprising: A substrate having a surface; A first conductive element and a second conductive element are disposed in the substrate, wherein the top surfaces of the first conductive element and the second conductive element are exposed from the surface of the substrate; A first signal line is disposed on the surface of the substrate to be electrically connected to the first conductive element, wherein the top surface of the first conductive element is completely covered by the first signal line; A second signal line is disposed on the surface of the substrate to be electrically connected to the second conductive element and spaced apart from the first signal line, wherein the top surface of the second conductive element is completely covered by the second signal line; and A first mask line is located between the first signal line and the second signal line, wherein the first mask line is not connected to the first conductive element and the second conductive element; The minimum distance between the first signal line and the first mask line is equal to or less than 40 nanometers.

16. The semiconductor device of claim 15, wherein the first signal line, the second signal line, and the first mask line are substantially parallel.

17. The semiconductor device of claim 15, wherein the minimum width of the first mask line is between about 10 nanometers and about 70 nanometers.

18. The semiconductor device of claim 17, wherein the minimum distance between the first signal line and the first mask line is less than the minimum width of the first mask line.

19. The semiconductor device of claim 17, wherein the minimum distance between the first signal line and the first mask line is greater than the minimum width of the first mask line.

20. The semiconductor device of claim 17, wherein the minimum distance between the first signal line and the first mask line is substantially equal to the minimum width of the first mask line.

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