Stackable timer

Abstract

The plurality of timer circuit blocks (201, 202, 203) includes at least a first timer circuit block (201) and a second timer circuit block (202). Each of the plurality of timer circuit blocks (201, 202, 203) can be selectively coupled through at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix can be configured to couple a second flip-flop input (205) of the first timer circuit block (201) with a first flip-flop output (213) of the second timer circuit block (202).

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