A chip, a consumable cartridge, an image forming apparatus, and a chip verification method

Abstract

Embodiments of the present application provide a chip, a consumable box, an image forming device and a chip verification method. The chip is applied to the consumable box, and the chip comprises a plurality of signal terminals, the plurality of signal terminals comprising a first signal terminal and a second signal terminal, and the chip further comprises a data conversion circuit, which is arranged between the first signal terminal and the second signal terminal; the first signal terminal is used for receiving input data sent by the image forming device; the second signal terminal is used for receiving a verification instruction sent by the image forming device; the data conversion circuit is used for converting the input data into verification data in response to the verification instruction; and the second signal terminal is further used for sending the verification data to the image forming device. Embodiments of the present application avoid the problem that the verification data stored in the chip cannot pass the verification of the image forming device when the image forming device changes the data logic of the verification instruction, thereby ensuring that the chip can be adapted.

Description

[Technical Field]

[0001] The present invention relates to the field of communication technology, and in particular to a chip, a consumable box, an image forming device, and a chip verification method. [Background Technology]

[0002] With the development of imaging technology, image forming devices, such as printers, have been widely used. An image forming device includes a consumable cartridge, which in turn contains a chip. During the imaging process, the image forming device requires imaging assistance information provided by the consumable cartridge to complete the imaging process; the quality of the consumable cartridge directly affects the quality of the image formed. Therefore, image forming devices typically communicate with the chip on the consumable cartridge before use to verify the cartridge's legitimacy.

[0003] The chip has multiple signal terminals for communicating with the image forming apparatus. These signal terminals include clock and data terminals, which work together to enable verification between the chip and the image forming apparatus. The image forming apparatus outputs verification commands to the chip. When the chip reads the verification command from the image forming apparatus, it outputs corresponding verification data to the image forming apparatus, allowing the image forming apparatus to verify the chip based on the verification data.

[0004] The aforementioned chip verification scheme requires a pre-defined verification protocol between the image forming apparatus and the chip, and the chip needs to pre-store verification data. When the image forming apparatus changes the data logic of the verification instructions, the verification data stored in the chip needs to be changed; otherwise, the verification data stored in the chip will fail to pass the verification by the image forming apparatus, resulting in the chip being incompatible. [Summary of the Invention]

[0005] In view of this, embodiments of the present invention provide a chip, a consumable box, an image forming apparatus, and a chip verification method to avoid the problem that verification data stored in the chip cannot be verified by the image forming apparatus, thereby ensuring that the chip can be adapted.

[0006] On one hand, an embodiment of the present invention provides a chip applied to a consumable box. The chip includes multiple signal terminals, including a first signal terminal and a second signal terminal. The chip further includes a data conversion circuit disposed between the first signal terminal and the second signal terminal.

[0007] The first signal terminal is used to receive input data sent by the image forming apparatus;

[0008] The second signal terminal is used to receive a verification command sent by the image forming apparatus;

[0009] The data conversion circuit is used to convert the input data into verification data in response to the verification command;

[0010] The second signal terminal is also used to send the verification data to the image forming apparatus.

[0011] Optionally, the data conversion circuit includes an inverter and a first switch connected in series.

[0012] Optionally, the first signal terminal includes a clock terminal, the second signal terminal includes a data terminal, and the input data includes a clock signal.

[0013] Optionally, the data conversion circuit includes a first conversion sub-circuit and a second conversion sub-circuit connected in parallel;

[0014] The first conversion sub-circuit includes an inverter and a first switch connected in series;

[0015] The second switching sub-circuit includes a second switch.

[0016] Optionally, the first signal terminal includes a voltage terminal, the second signal terminal includes a data terminal, and the input data includes a voltage signal; or,

[0017] The first signal terminal includes a reset terminal, the second signal terminal includes a data terminal, and the input data includes a reset signal.

[0018] On the other hand, embodiments of the present invention provide a consumable box including the above-mentioned chip.

[0019] On the other hand, embodiments of the present invention provide an image forming apparatus, including an image forming device and the aforementioned consumable box, wherein the consumable box is detachably mounted on the image forming device.

[0020] On the other hand, embodiments of the present invention provide a chip verification method, the method comprising:

[0021] The chip receives input data sent by the image forming apparatus;

[0022] The chip receives a verification command sent by the image forming apparatus;

[0023] In response to the verification command, the chip converts the input data into verification data and sends the verification data to the image forming apparatus.

[0024] Optionally, the input data includes level signals at multiple times.

[0025] Optionally, the verification instruction includes at least one specified time.

[0026] The chip, in response to the verification command, converts the input data into verification data and sends the verification data to the image forming apparatus, including:

[0027] The chip performs specified processing on the level signal at a specified time in the input data, generates verification data at the specified time, and sends the verification data at the specified time to the image forming apparatus.

[0028] In the technical solution provided by the embodiments of the present invention, the chip receives input data sent by the image forming apparatus, the chip receives a verification instruction sent by the image forming apparatus, and in response to the verification instruction, converts the input data into verification data and sends the verification data to the image forming apparatus. In the embodiments of the present invention, the verification data is obtained by the chip converting the input data. The verification data used is not stored internally by the chip, which avoids the problem that the verification data stored in the chip cannot be verified by the image forming apparatus when the data logic of the verification instruction is changed, thereby ensuring that the chip can adapt. [Attached Image Description]

[0029] Figure 1 This is a schematic diagram of the structure of an image forming apparatus provided in an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of the structure of a chip provided in an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the structure of a data conversion circuit provided in an embodiment of the present invention;

[0032] Figure 4 for Figure 3 A schematic diagram of an application of a data conversion circuit;

[0033] Figure 5 for Figure 4 Signal diagram of the signal terminals of the chip;

[0034] Figure 6 This is a schematic diagram of another data conversion circuit provided in an embodiment of the present invention;

[0035] Figure 7 for Figure 6 A schematic diagram of an application of a data conversion circuit;

[0036] Figure 8 for Figure 7 Signal diagram of the signal terminals of the chip;

[0037] Figure 9 This is a schematic diagram of another data conversion circuit provided in an embodiment of the present invention;

[0038] Figure 10 for Figure 9 A schematic diagram of an application of a data conversion circuit;

[0039] Figure 11 for Figure 10 Signal diagram of the signal terminals of the chip;

[0040] Figure 12 This is a flowchart of a chip verification method provided in an embodiment of the present invention.

Detailed Implementation Methods

[0041] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0042] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0043] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0044] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0045] Figure 1 This is a schematic diagram of the structure of an image forming apparatus provided in an embodiment of the present invention, such as... Figure 1 As shown, the image forming apparatus includes an image forming device 10 and a consumable cartridge 20, which is detachably mounted on the image forming device 10.

[0046] In the field of printing imaging, examples of image forming apparatus 10 include inkjet printers, laser printers, light-emitting diode (LED) printers, copiers, scanners, or multifunction fax machines, as well as multi-function peripherals (MFPs) that perform the above functions in a single device. Image forming apparatus 10 includes an image forming control unit and an image forming unit. The image forming control unit controls the entire image forming apparatus, and the image forming unit, under the control of the image forming control unit, forms an image on the fed paper based on image forming data and a developer such as toner stored in a consumable cartridge.

[0047] This invention provides a consumable cartridge 20, which may include a chip 200. In the field of printing and imaging, the consumable cartridge 20 is used to contain developer. For example, if the consumable cartridge 20 is an ink cartridge and the developer is ink, then the ink cartridge is used to contain ink; if the consumable cartridge is a toner cartridge and the developer is toner, then the toner cartridge is used to contain toner; if the consumable cartridge is a toner box or toner cartridge and the developer is toner, then the toner box is used to contain toner, and the toner cartridge is used to contain toner.

[0048] This invention provides a chip that is used in a consumable box. Figure 2 This is a schematic diagram of a chip structure provided in an embodiment of the present invention, such as... Figure 2 As shown, the chip 200 includes a plurality of signal terminals 300, including a first signal terminal and a second signal terminal. The chip 200 also includes a data conversion circuit 400, which is disposed between the first signal terminal and the second signal terminal.

[0049] like Figure 2As shown, in one possible implementation, signal terminal 300 may include a data terminal SDA, a clock terminal CLK, a reset terminal RST, a voltage terminal VCC, or a ground terminal GND. If the first signal terminal is one of the multiple signal terminals 300, then the second signal terminal is another of the multiple signal terminals 300. For example, the data conversion circuit 400 may be disposed between the data terminal SDA and other terminals, in which case the first signal terminal includes the clock terminal CLK, and the second signal terminal includes the data terminal; or, the first signal terminal includes the voltage terminal, and the second signal terminal includes the data terminal; or, the first signal terminal includes the reset terminal, and the second signal terminal includes the data terminal. Wherein, the voltage terminal VCC is used to receive a voltage signal sent by the image forming apparatus, the reset terminal RST is used to receive a reset signal sent by the image forming apparatus, the clock terminal CLK is used to receive a clock signal from the image forming apparatus, the data terminal SDA is used to receive a data signal sent by the image forming apparatus or to send a data signal to the image forming apparatus, and the ground terminal GND is used to transmit a ground signal.

[0050] The first signal terminal is used to receive input data sent by the image forming apparatus. The second signal terminal is used to receive a verification command sent by the image forming apparatus. The data conversion circuit is used to convert the input data into verification data in response to the verification command. The second signal terminal is used to send the verification data to the image forming apparatus.

[0051] When a chip verification operation is required, the image forming apparatus sends a verification command to the chip, which instructs the chip to return verification data to the image forming apparatus. After receiving the verification command through the second signal terminal, the chip enters a response period. During the response period, the second signal terminal returns verification data to the image forming apparatus. This verification data is obtained by the data conversion circuit converting the input data received from the other first signal terminals.

[0052] In this embodiment of the invention, the verification data output by the chip to the image forming apparatus is not internally stored data, but rather data obtained by the chip's data conversion circuit from the input data. The chip then returns this verification data to the image forming apparatus. The image forming apparatus verifies the verification data. If the verification data matches preset data, it indicates that the verification data is the data expected by the image forming apparatus, and the chip passes the verification, enabling it to adapt. If the verification data differs from the preset data, it indicates that the verification data is not the data expected by the image forming apparatus, and the chip fails the verification, making it unsuitable for adaptation. The preset data refers to the data expected by the image forming apparatus.

[0053] Figure 3 This is a schematic diagram of a data conversion circuit provided in an embodiment of the present invention. Figure 4 for Figure 3 A schematic diagram of an application of a data conversion circuit, such as... Figure 3 and Figure 4 As shown, the data conversion circuit 400 includes an inverter and a first switch K1 connected in series.

[0054] The inverter is used to invert the input data received from the first signal terminal to generate verification data. The first switch K1, when closed, outputs the verification data to the second signal terminal. The first signal terminal is the clock terminal CLK, and the second signal terminal is the data terminal SDA.

[0055] The data conversion circuit 400 is disposed between the clock terminal CLK and the data terminal SDA. Specifically, the input terminal of the data conversion circuit 400 is electrically connected to the clock terminal CLK, and the output terminal of the data conversion circuit 400 is electrically connected to the data terminal SDA.

[0056] As an alternative, such as Figure 3 As shown, the input of the inverter is electrically connected to the clock terminal CLK, the output of the inverter is electrically connected to one end of the first switch K1, and the other end of the first switch K1 is electrically connected to the data terminal SDA. Alternatively, one end of the first switch K1 is electrically connected to the clock terminal CLK, the other end of the first switch K1 is electrically connected to the input of the inverter, and the output of the inverter is electrically connected to the data terminal SDA; this case is not specifically shown.

[0057] Figure 5 for Figure 4 A schematic diagram of the signal terminals of the chip, as shown below. Figure 3 , Figure 4 and Figure 5 As shown, the image forming apparatus 10 sends input data to the clock terminal CLK. The input data includes a clock signal, and the clock signal received by the clock terminal CLK is a periodic pulse signal. The data terminal SDA receives a verification command sent by the image forming apparatus 10. The verification command includes multiple specified times, such as... Figure 5 As shown, multiple specified times can include time t1, time t2, and time t3. The clock signal at time t1 is a high-level signal, the clock signal at time t2 is a low-level signal, and the clock signal at time t3 is a high-level signal. Figure 3As shown, in response to the verification command, the data conversion circuit 400 converts the clock signal at a specified time from the input data obtained from the clock terminal CLK into verification data at a specified time and outputs the verification data at the specified time to the data terminal SDA. The data terminal SDA sends the verification data at the specified time to the image forming apparatus 10. Specifically, for the clock signal at time t1, the first switch K1 is closed and the inverter inverts the clock signal at time t1 to obtain a low-level signal. The verification data at time t1 is a low-level signal, which is output to the data terminal SDA. The data terminal SDA outputs the low-level signal at time t1 to the image forming apparatus 10. The image forming apparatus 10 reads the verification data of the low-level signal at time t1. Since the preset data at time t1 is a low-level signal, the image forming apparatus 10 verifies that the verification data at time t1 is the same as the preset data, and the verification data at time t1 passes verification. For the clock signal at time t2, the first switch K1 is closed and the inverter inverts the clock signal at time t2 to obtain a high-level signal. The verification data at time t2 is a high-level signal, which is output to the data terminal SDA. The data terminal SDA outputs the high-level signal at time t2 to the data terminal SDA. The image forming apparatus 10 outputs a high-level signal to the image forming apparatus 10. The image forming apparatus 10 reads the verification data of the high-level signal at time t2. Since the preset data at time t2 is a high-level signal, the image forming apparatus 10 verifies that the verification data at time t2 is the same as the preset data, and the verification data at time t2 passes the verification. For the clock signal at time t3, the first switch K1 is closed and the inverter inverts the clock signal at time t3 to obtain a low-level signal. The verification data at time t3 is a low-level signal. This low-level signal at time t3 is output to the data terminal SDA. The data terminal SDA outputs the low-level signal at time t3 to the image forming apparatus 10. The image forming apparatus 10 reads the verification data of the low-level signal at time t3. Since the preset data at time t3 is a low-level signal, the image forming apparatus 10 verifies that the verification data at time t3 is the same as the preset data, and the verification data at time t3 passes the verification. At this point, the image forming apparatus 10 has successfully verified the verification data at multiple specified times, indicating that the chip 200 has passed the verification by the image forming apparatus 10 and is thus compatible. After the verification data has passed, the first switch K1 can be disconnected, and then the chip 200 can output other non-image forming data to the image forming apparatus 10 to enable the image forming apparatus 10 to perform the image forming function. For example, the non-image forming data may include the remaining amount of consumables, the remaining number of pages, etc.

[0058] Figure 6 This is a schematic diagram of another data conversion circuit provided in an embodiment of the present invention. Figure 7 for Figure 6 A schematic diagram of an application of a data conversion circuit, such as... Figure 6 and Figure 7 As shown, the data conversion circuit 400 includes a first conversion sub-circuit and a second conversion sub-circuit connected in parallel. The first conversion sub-circuit includes an inverter and a first switch K1 connected in series, and the second conversion sub-circuit includes a second switch K2.

[0059] The inverter is used to invert the input data received from the first signal terminal to generate verification data. When the first switch K1 is closed and the second switch K2 is open, the verification data is output to the second signal terminal through the first conversion sub-circuit; or, when the first switch K1 is open and the second switch K2 is closed, the input data is directly output to the second signal terminal through the second conversion sub-circuit, in which case the verification data is the input data. The first signal terminal is the voltage terminal VCC, and the second signal terminal is the data terminal SDA.

[0060] The data conversion circuit 400 is disposed between the voltage terminal VCC and the data terminal SDA. Specifically, the input terminal of the data conversion circuit 400 is electrically connected to the voltage terminal VCC, and the output terminal of the data conversion circuit 400 is electrically connected to the data terminal SDA.

[0061] As an alternative, such as Figure 6 As shown, in the first conversion sub-circuit, the input terminal of the inverter is electrically connected to the voltage terminal VCC, the output terminal of the inverter is electrically connected to one end of the first switch K1, and the other end of the first switch K1 is electrically connected to the data terminal SDA. Alternatively, in the first conversion sub-circuit, one end of the first switch K1 is electrically connected to the voltage terminal VCC, the other end of the first switch K1 is electrically connected to the input terminal of the inverter, and the output terminal of the inverter is electrically connected to the data terminal SDA. This case is not specifically shown. Figure 6 As shown, in the second conversion sub-circuit, one end of the second switch K2 is electrically connected to the voltage terminal VCC, and the other end of the second switch K2 is electrically connected to the data terminal SDA.

[0062] Figure 8 for Figure 7 A schematic diagram of the signal terminals of the chip, as shown below. Figure 6 , Figure 7 and Figure 8 As shown, the image forming apparatus 10 sends input data to the voltage terminal VCC. The input data includes a voltage signal, and the voltage signal received by the voltage terminal VCC is a high-level signal (H). The data terminal SDA receives a verification command sent by the image forming apparatus 10. This verification command includes multiple specified times, such as... Figure 8 As shown, multiple specified times can include time t1, time t2, and time t3. The voltage signal at time t1 is a high-level signal, the voltage signal at time t2 is a high-level signal, and the voltage signal at time t3 is a high-level signal. Figure 6 As shown, in response to the verification command, the data conversion circuit 400 converts the voltage signal at a specified time from the input data obtained from the voltage terminal VCC into verification data at a specified time and outputs the verification data at the specified time to the data terminal SDA. The data terminal SDA sends the verification data at the specified time to the image forming apparatus 10. Specifically, for the voltage signal at time t1, the first switch K1 is closed, the second switch K2 is opened, and the inverter inverts the voltage signal at time t1 to obtain a low-level signal. The verification data at time t1 output by the first conversion sub-circuit to the data terminal SDA is a low-level signal. The data terminal SDA outputs the low-level signal at time t1 to the image forming apparatus 10. The image forming apparatus 10 reads the verification data of the low-level signal at time t1. Since the preset data at time t1 is a low-level signal, the image forming apparatus 10 verifies that the verification data at time t1 is the same as the preset data, and the verification data at time t1 is verified successfully. For the voltage signal at time t2, the first switch K1 is opened, and the second switch K2 is closed, so that the second conversion sub-circuit transmits the high-level signal at time t2 output by the voltage terminal VCC to the data terminal SDA. The verification data at time t2 is a high-level signal, and the data terminal SDA outputs the high-level signal at time t2. The image forming apparatus 10 outputs a high-level signal to the image forming apparatus 10. The image forming apparatus 10 reads the verification data of the high-level signal at time t2. Since the preset data at time t2 is a high-level signal, the image forming apparatus 10 verifies that the verification data at time t2 is the same as the preset data, and the verification data at time t2 passes the verification. For the voltage signal at time t3, the first switch K1 is closed, the second switch K2 is opened, and the inverter inverts the voltage signal at time t3 to obtain a low-level signal. The first conversion sub-circuit outputs the verification data at time t3 to the data terminal SDA as a low-level signal. The data terminal SDA outputs the low-level signal at time t3 to the image forming apparatus 10. The image forming apparatus 10 reads the verification data of the low-low-level signal at time t3. Since the preset data at time t3 is a low-level signal, the image forming apparatus 10 verifies that the verification data at time t3 is the same as the preset data, and the verification data at time t3 passes the verification. At this point, the image forming apparatus 10 has successfully verified the verification data at multiple specified times, indicating that the chip 200 has passed the verification by the image forming apparatus 10 and is thus compatible. After the verification data has passed, the first switch K1 and the second switch K2 can be disconnected, and then the chip 200 can output other non-image forming data to the image forming apparatus 10 to enable the image forming apparatus to perform the image forming function. For example, the non-image forming data may include the remaining amount of consumables, the remaining number of pages, etc.

[0063] Figure 9 This is a schematic diagram of another data conversion circuit provided in an embodiment of the present invention. Figure 10 for Figure 9A schematic diagram of an application of a data conversion circuit, such as... Figure 9 and Figure 10 As shown, the data conversion circuit 400 includes a first conversion sub-circuit and a second conversion sub-circuit connected in parallel. The first conversion sub-circuit includes an inverter and a first switch K1 connected in series, and the second conversion sub-circuit includes a second switch K2.

[0064] The inverter is used to invert the input data received from the first signal terminal to generate verification data. When the first switch K1 is closed and the second switch K2 is open, the verification data is output to the second signal terminal through the first conversion sub-circuit; or, when the first switch K1 is open and the second switch K2 is closed, the input data is directly output to the second signal terminal through the second conversion sub-circuit, in which case the verification data is the input data. The first signal terminal is the reset terminal RST, and the second signal terminal is the data terminal SDA.

[0065] The data conversion circuit 400 is disposed between the reset terminal RST and the data terminal SDA. Specifically, the input terminal of the data conversion circuit 400 is electrically connected to the reset terminal RST, and the output terminal of the data conversion circuit 400 is electrically connected to the data terminal SDA.

[0066] As an alternative, such as Figure 9 As shown, in the first conversion sub-circuit, the input terminal of the inverter is electrically connected to the reset terminal RST, the output terminal of the inverter is electrically connected to one end of the first switch K1, and the other end of the first switch K1 is electrically connected to the data terminal SDA. Alternatively, in the first conversion sub-circuit, one end of the first switch K1 is electrically connected to the reset terminal RST, the other end of the first switch K1 is electrically connected to the input terminal of the inverter, and the output terminal of the inverter is electrically connected to the data terminal SDA. This case is not specifically shown. Figure 9 As shown, in the second conversion sub-circuit, one end of the second switch K2 is electrically connected to the reset terminal RST, and the other end of the second switch K2 is electrically connected to the data terminal SDA.

[0067] Figure 11 for Figure 10 A schematic diagram of the signal terminals of the chip, as shown below. Figure 9 , Figure 10 and Figure 11 As shown, the image forming apparatus 10 sends input data to the reset terminal RST. The input data includes a reset signal, and the voltage signal received by the reset terminal RST is a low-level signal (L). The data terminal SDA receives a verification command sent by the image forming apparatus 10. This verification command includes multiple specified times, such as... Figure 11As shown, multiple specified times can include time t1, time t2, and time t3. The voltage signal at time t1 is a low-level signal, the voltage signal at time t2 is a low-level signal, and the voltage signal at time t3 is a low-level signal. Figure 9 As shown, in response to the verification command, the data conversion circuit 400 converts the reset signal at a specified time from the input data obtained from the reset terminal RST into verification data at a specified time and outputs the verification data at the specified time to the data terminal SDA. The data terminal SDA sends the verification data at the specified time to the image forming apparatus 10. Specifically, for the reset signal at time t1, the first switch K1 is opened and the second switch K2 is closed, causing the second conversion sub-circuit to transmit the low-level signal at time t1 output from the reset terminal RST to the data terminal SDA. The verification data at time t1 is a low-level signal. The data terminal SDA outputs the low-level signal at time t1 to the image forming apparatus 10. The image forming apparatus 10 reads the verification data of the low-level signal at time t1. Since the preset data at time t1 is a low-level signal, the image forming apparatus 10 verifies that the verification data at time t1 is the same as the preset data, and the verification data at time t1 is verified successfully. For the voltage signal at time t2, the first switch K1 is closed, the second switch K2 is opened, and the inverter inverts the reset signal at time t2 to obtain a high-level signal. The verification data at time t2 output by the first conversion sub-circuit to the data terminal SDA is a high-level signal. The data terminal SDA outputs the low-level signal at time t2 to the image forming apparatus 10. A high-level signal is output to the image forming apparatus 10. The image forming apparatus 10 reads the verification data of the high-level signal. Since the preset data at time t2 is a high-level signal, the image forming apparatus 10 verifies that the verification data at time t2 is the same as the preset data, and the verification data at time t2 passes verification. For the reset signal at time t3, the first switch K1 is opened and the second switch K2 is closed, so that the second conversion sub-circuit transmits the low-level signal at time t3 output by the reset terminal RST to the data terminal SDA. The verification data at time t3 is a low-level signal. The data terminal SDA outputs the low-level signal at time t3 to the image forming apparatus 10. The image forming apparatus 10 reads the verification data of the low-level signal at time t3. Since the preset data at time t3 is a low-level signal, the image forming apparatus 10 verifies that the verification data at time t3 is the same as the preset data, and the verification data at time t3 passes verification. At this point, the image forming apparatus 10 has successfully verified the verification data at multiple specified times, indicating that the chip 200 has passed the verification by the image forming apparatus 10 and is thus compatible. After the verification data has passed, the first switch K1 and the second switch K2 can be disconnected, and then the chip 200 can output other non-image forming data to the image forming apparatus 10 to enable the image forming apparatus to perform the image forming function. For example, the non-image forming data may include the remaining amount of consumables, the remaining number of pages, etc.

[0068] In this embodiment of the invention, in Figures 6 to 8 In the illustrated scheme, if the voltage signal is a low-level signal, the verification method for the chip is the same as the verification method when the reset signal is a low-level signal, and will not be repeated here; Figures 9 to 11 In the scheme shown, if the reset signal is a high-level signal, the verification method for the chip is the same as the verification method when the voltage signal is a high-level signal, and will not be repeated here.

[0069] In this embodiment of the invention, the chip adopts Figure 6 or Figure 9 The difference in the chip verification method when the input data is a high-level signal versus a low-level signal in the data conversion circuit shown lies in the different selection order of the first switch in the first conversion sub-circuit and the second switch in the second conversion sub-circuit. When the data logic of the input data sent by the image forming apparatus to the chip changes, only the selection order of the first and second conversion sub-circuits needs to be changed to allow the chip to pass the verification by the image forming apparatus.

[0070] In the technical solution of the chip provided in this embodiment of the invention, the chip includes a first signal terminal, a second signal terminal, and a data conversion circuit. The first signal terminal receives input data sent by the image forming apparatus, and the second signal terminal receives a verification command sent by the image forming apparatus. The data conversion circuit converts the input data into verification data in response to the verification command, and the second signal terminal sends the verification data to the image forming apparatus. In this embodiment of the invention, the verification data is obtained by the chip's data conversion circuit converting the input data. The verification data used is not stored internally in the chip, which avoids the problem that the verification data stored in the chip cannot be verified by the image forming apparatus when the data logic of the verification command is changed, thereby ensuring that the chip can adapt.

[0071] This invention also provides a chip verification method, which is implemented based on the above-described image forming apparatus. A description of the image forming apparatus can be found in [link to relevant documentation]. Figure 1 The embodiments shown are not described in detail here.

[0072] Figure 12 A flowchart of a chip verification method provided in an embodiment of the present invention is shown below. Figure 12 As shown, the method includes:

[0073] Step 102: The chip receives input data sent by the image forming apparatus.

[0074] In this embodiment of the invention, the input data may include level signals at multiple times, wherein the level signals at multiple times may all be high level signals; or, the level signals at multiple times may all be low level signals; or, the level signals at multiple times may be a combination of high and low level signals.

[0075] Step 104: The chip receives the verification command sent by the image forming device.

[0076] In this embodiment of the invention, after receiving a verification command, the chip can identify that the verification command is an instruction instructing the chip to return verification data to the image forming apparatus. After receiving the verification command, the chip enters a response period, during which it can return verification data to the image forming apparatus.

[0077] In this embodiment of the invention, the verification instruction includes at least one specified time. When the verification instruction includes one specified time, the image forming apparatus verifies the verification data at only one specified time during one verification of the chip; when the verification instruction includes multiple specified times, the image forming apparatus needs to verify the verification data at multiple specified times during one verification of the chip. For example, the multiple specified times may include time t1, time t2, and time t3.

[0078] Step 106: In response to the verification command, the chip converts the input data into verification data and sends the verification data to the image forming apparatus.

[0079] In this embodiment of the invention, the chip performs specified processing on the level signal at a specified time in the input data to generate verification data at the specified time, and sends the verification data at the specified time to the image forming apparatus. Specifically, the chip can invert the level signal at the specified time to generate the verification data at the specified time and send the verification data at the specified time to the image forming apparatus; alternatively, the chip can use the level signal at the specified time as the verification data at the specified time. In this case, the chip can directly send the level signal at the specified time to the image forming apparatus without processing the level signal at the specified time.

[0080] In this embodiment of the invention, the verification data at a specified moment can be a high-level signal or a low-level signal.

[0081] In this embodiment of the invention, the verification data at multiple specified times can all be high-level signals; or, the verification data at multiple specified times can all be low-level signals; or, the verification data at multiple specified times can be a combination of high and low level signals.

[0082] The image forming apparatus can preset data at specified times. The image forming apparatus verifies whether the verification data at at least one specified time is the same as the preset data at each specified time. If the verification data at at least one specified time is the same as the preset data at each specified time, it indicates that the verification data at the at least one specified time is the data expected by the image forming apparatus, and the chip passes the verification of the image forming apparatus. If the verification data at at least one specified time is different from the preset data at the specified time, it indicates that the verification data at the at least one specified time is not the data expected by the image forming apparatus, and the chip fails the verification of the image forming apparatus.

[0083] In this embodiment of the invention, the chip may execute steps 102 to 106 once, so that the image forming apparatus performs one verification of the chip. In this case, when the image forming apparatus passes the one-time verification of the chip, it indicates that the chip has passed the verification of the image forming apparatus. Alternatively, the chip may repeatedly execute steps 102 to 106 multiple times, so that the image forming apparatus performs multiple verifications of the chip. In this case, when the image forming apparatus passes the multiple verifications of the chip, it indicates that the chip has passed the verification of the image forming apparatus.

[0084] In the technical solution of the chip verification method provided in this embodiment of the invention, the chip receives input data sent by the image forming apparatus, the chip receives verification instructions sent by the image forming apparatus, and in response to the verification instructions, converts the input data into verification data and sends the verification data to the image forming apparatus. In this embodiment of the invention, the verification data is obtained by the chip converting the input data. The verification data used is not stored internally in the chip, which avoids the problem that the verification data stored in the chip cannot be verified by the image forming apparatus when the data logic of the verification instructions is changed, thereby ensuring that the chip can be adapted.

[0085] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip, characterized in that, The chip is applied to a consumable box. The chip includes multiple signal terminals, including a first signal terminal and a second signal terminal. The chip further includes a data conversion circuit disposed between the first signal terminal and the second signal terminal. The first signal terminal is used to receive input data sent by the image forming apparatus; The second signal terminal is used to receive a verification command sent by the image forming apparatus, the verification command including at least one specified time. The data conversion circuit is used to convert the input data into verification data in response to the verification command; The second signal terminal is also used to send the verification data to the image forming apparatus; The data conversion circuit includes an inverter and a first switch connected in series; or... The data conversion circuit includes a first conversion sub-circuit and a second conversion sub-circuit connected in parallel; The first conversion sub-circuit includes an inverter and a first switch connected in series; The second switching sub-circuit includes a second switch; When the first switch is set to be closed according to the specified time, the inverter inverts the input data to obtain the verification data.

2. The chip according to claim 1, characterized in that, The first signal terminal includes a clock terminal, the second signal terminal includes a data terminal, and the input data includes a clock signal.

3. The chip according to claim 1, characterized in that, The first signal terminal includes a voltage terminal, the second signal terminal includes a data terminal, and the input data includes a voltage signal; or, The first signal terminal includes a reset terminal, the second signal terminal includes a data terminal, and the input data includes a reset signal.

4. A consumable box, characterized in that, Includes the chip described in any one of claims 1 to 3.

5. An image forming apparatus, characterized in that, It includes an image forming apparatus and a consumable cartridge as described in claim 4, the consumable cartridge being detachably mounted on the image forming apparatus.

6. A chip verification method, characterized in that, The method includes: The chip receives input data sent by the image forming apparatus; The chip receives a verification command sent by the image forming apparatus, the verification command including at least one specified time. In response to the verification command, the chip converts the input data into verification data and sends the verification data to the image forming apparatus; The chip, in response to the verification command, converts the input data into verification data and sends the verification data to the image forming apparatus, including: The chip inverts the level signal at a specified time in the input data to generate verification data at the specified time, and sends the verification data at the specified time to the image forming apparatus; or, The chip uses the level signal at a specified time in the input data as the verification data at the specified time, and sends the verification data at the specified time to the image forming apparatus.

7. The method according to claim 6, characterized in that, The input data includes level signals at multiple times.

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