Chip testing method, device, equipment, storage medium and program product

Abstract

The application provides a chip testing method, device, equipment, storage medium and program product. The method comprises the following steps: determining pin information of a chip to be tested, wherein the pin information comprises pin identification information, a pin type and a pin voltage of each pin; grouping a plurality of pins according to the pin identification information, the pin voltage and the pin type, to obtain a plurality of pin combinations; and performing electrostatic discharge (ESD) testing on the chip to be tested based on the plurality of pin combinations, to obtain a chip test result of the chip to be tested. The application provides a pin grouping manner for ESD testing, and improves the testing efficiency.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip testing method, apparatus, equipment, storage medium, and program product. Background Technology

[0002] In practical applications, each pin of a chip may be subjected to electrostatic discharge (ESD) attacks. Therefore, before the chips leave the factory, the same batch of chips needs to be sampled for inspection to perform corresponding positive electrostatic stress tests and negative electrostatic stress tests on each pin of the sampled chips.

[0003] In related technologies, conventional human body models (HBM) are typically used for ESD testing. During testing, individual pins can be tested, or the pins of the chip can be combined to achieve combined pin testing.

[0004] Because chips have a large number of pins, such as system-on-chip (SoC) chips which have hundreds or thousands of pins (e.g., 600-1500+), the combination of these pins is random, which makes ESD testing inefficient. Summary of the Invention

[0005] This application provides a chip testing method, apparatus, device, storage medium, and program product to solve the problem of low efficiency in ESD testing due to the randomness of pin combinations in related technologies.

[0006] Firstly, this application provides a chip testing method, including:

[0007] Determine the pin information of the chip to be tested, wherein the pin information includes the pin identifier, pin type and pin voltage of each pin;

[0008] Based on the pin identification information, the pin voltage, and the pin type, multiple pins are grouped to obtain multiple pin combinations;

[0009] Based on the multiple pin combinations, the chip under test is subjected to electrostatic discharge (ESD) testing to obtain the chip test results.

[0010] In one possible implementation, the pin identification information includes a pin number and a pin name, and the pin type includes one or more of the following: power pin type, ground pin type, and input / output (I / O) pin type;

[0011] The multiple pins are grouped according to the pin identification information, the pin voltage, and the pin type to obtain multiple pin combinations, including:

[0012] Based on the pin name and the pin type, the plurality of pins are divided into a plurality of initial combinations. Each initial combination includes a plurality of pin numbers with the same pin name. The plurality of initial combinations include power type combinations, ground type combinations, and input / output I / O type combinations.

[0013] Based on the pin voltage, the power supply type combinations are sorted to obtain the sorted power supply type combinations;

[0014] The plurality of pin combinations are defined as including the sorted power type combinations, the ground type combinations, and the I / O type combinations.

[0015] In one possible implementation, the plurality of pins are divided into a plurality of initial combinations based on the pin name and the pin type, including:

[0016] Based on the pin names, the plurality of pins are divided into a plurality of first groups, and each first group corresponds to a pin name;

[0017] According to the pin type, the plurality of first combinations are divided into the plurality of initial combinations.

[0018] In one possible implementation, based on the multiple pin combinations, an electrostatic discharge (ESD) test is performed on the chip under test to obtain the chip test results, including:

[0019] The first chip is used to perform ESD testing on the sorted power type combinations to obtain the first test result.

[0020] The second chip is used to perform ESD testing on the grounding type combination to obtain the second test result;

[0021] The I / O type combination is subjected to ESD testing using a third chip to obtain a third test result.

[0022] The chip test result is determined based on the first test result, the second test result, and the third test result;

[0023] The chip to be tested includes the first chip, the second chip, and the third chip, and the first chip, the second chip, and the third chip are chips of the same type.

[0024] In one possible implementation, determining the chip test result based on the first test result, the second test result, and the third test result includes:

[0025] If the first test result indicates that the pin ESD test of the power type combination fails, the sorted power type combinations are divided into class i combinations according to the pin voltage;

[0026] The i-type combinations are tested using i chips respectively, resulting in i test results;

[0027] If the i test results indicate that the pin ESD test of the power type combination is successful, then the chip test result is determined based on the i test results, the second test result, and the third test result;

[0028] Wherein, i takes the values ​​2, 3, 4, 5, ... in sequence until the i test results indicate that the pin ESD test of the power type combination is successful, and the chip to be tested includes the i chips.

[0029] In one possible implementation, an ESD test is performed on the sorted power type combinations using a first chip to obtain a first test result, including:

[0030] For any pin in the sorted power type combination, a forward mode electrostatic discharge is performed between the pin and the first pin according to a preset voltage value to determine the forward test result, wherein the first pin is any pin in the ground type combination and the I / O type combination;

[0031] A negative mode electrostatic discharge is performed between the pin and the first pin according to the preset voltage value to determine the negative test result;

[0032] The first test result is determined based on the positive test result and the negative test result.

[0033] Secondly, this application provides a chip testing apparatus, comprising:

[0034] The determination module is used to determine the pin information of the chip under test, wherein the pin information includes the pin identifier information, pin type and pin voltage of each pin;

[0035] The grouping module is used to group multiple pins according to the pin identification information, the pin voltage, and the pin type to obtain multiple pin combinations;

[0036] The testing module is used to perform electrostatic discharge (ESD) testing on the chip under test based on the multiple pin combinations, and obtain the chip test results of the chip under test.

[0037] In one possible implementation, the pin identification information includes a pin number and a pin name, and the pin type includes one or more of the following: power pin type, ground pin type, and input / output (I / O) pin type;

[0038] The grouping module is specifically used for:

[0039] Based on the pin name and the pin type, the plurality of pins are divided into a plurality of initial combinations. Each initial combination includes a plurality of pin numbers with the same pin name. The plurality of initial combinations include power type combinations, ground type combinations, and input / output I / O type combinations.

[0040] Based on the pin voltage, the power supply type combinations are sorted to obtain the sorted power supply type combinations;

[0041] The plurality of pin combinations are defined as including the sorted power type combinations, the ground type combinations, and the I / O type combinations.

[0042] In one possible implementation, the grouping module is specifically used for:

[0043] Based on the pin names, the plurality of pins are divided into a plurality of first groups, and each first group corresponds to a pin name;

[0044] According to the pin type, the plurality of first combinations are divided into the plurality of initial combinations.

[0045] In one possible implementation, the test module is specifically used for:

[0046] The first chip is used to perform ESD testing on the sorted power type combinations to obtain the first test result.

[0047] The second chip is used to perform ESD testing on the grounding type combination to obtain the second test result;

[0048] The I / O type combination is subjected to ESD testing using a third chip to obtain a third test result.

[0049] The chip test result is determined based on the first test result, the second test result, and the third test result;

[0050] The chip to be tested includes the first chip, the second chip, and the third chip, and the first chip, the second chip, and the third chip are chips of the same type.

[0051] In one possible implementation, the test module is specifically used for:

[0052] If the first test result indicates that the pin ESD test of the power type combination fails, the sorted power type combinations are divided into class i combinations according to the pin voltage;

[0053] The i-type combinations are tested using i chips respectively, resulting in i test results;

[0054] If the i test results indicate that the pin ESD test of the power type combination is successful, then the chip test result is determined based on the i test results, the second test result, and the third test result;

[0055] Wherein, i takes the values ​​2, 3, 4, 5, ... in sequence until the i test results indicate that the pin ESD test of the power type combination is successful, and the chip to be tested includes the i chips.

[0056] In one possible implementation, the test module is specifically used for:

[0057] For any pin in the sorted power type combination, a forward mode electrostatic discharge is performed between the pin and the first pin according to a preset voltage value to determine the forward test result, wherein the first pin is any pin in the ground type combination and the I / O type combination;

[0058] A negative mode electrostatic discharge is performed between the pin and the first pin according to the preset voltage value to determine the negative test result;

[0059] The first test result is determined based on the positive test result and the negative test result.

[0060] Thirdly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0061] The memory stores computer-executed instructions;

[0062] The processor executes computer execution instructions stored in the memory to implement the signal processing method as described in the first aspect.

[0063] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a computer, are used to implement the chip testing method as described in the first aspect.

[0064] Fifthly, this application provides a computer program product, including a computer program, which, when executed by a computer, is used to implement the chip testing method described in the first aspect.

[0065] Sixthly, embodiments of this application provide a chip on which a computer program is stored, and when the computer program is executed by the chip, the chip testing method described in the first aspect is executed.

[0066] In one possible implementation, the chip is a chip in a chip module.

[0067] In a seventh aspect, embodiments of this application provide a module device, the module device including a power module, a storage module, and a chip module;

[0068] The power module is used to provide electrical energy to the module device;

[0069] The storage module is used to store data and instructions;

[0070] The chip module is used to perform the chip testing method described in the first aspect.

[0071] This application provides a chip testing method, apparatus, device, storage medium, and program product. By determining the pin information of the chip under test, including pin identification information, pin type, and pin voltage for each pin, multiple pins are grouped according to the pin identification information, pin voltage, and pin type to obtain multiple pin combinations. Based on these multiple pin combinations, electrostatic discharge (ESD) testing is performed on the chip under test to obtain the chip test results. This application provides a pin grouping method for ESD testing, improving testing efficiency. Attached Figure Description

[0072] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0073] Figure 1 A schematic flowchart of a chip testing method provided in an embodiment of this application;

[0074] Figure 2 A schematic flowchart of a chip testing method provided in an embodiment of this application;

[0075] Figure 3 This is a schematic diagram illustrating the ESD test of a chip pin as an example in this application;

[0076] Figure 4 This is a schematic diagram illustrating a power supply type combination grouping as an example of this application;

[0077] Figure 5 This is a schematic diagram of the structure of a chip testing device provided in an embodiment of this application;

[0078] Figure 6This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0079] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0080] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0081] In integrated circuit (IC) design, continuous advancements in manufacturing processes and shrinking process dimensions, coupled with the widespread application of polymer materials, inevitably bring negative impacts. Among these, the design of ESD protection devices has become increasingly difficult, leading to more severe static electricity generation in products and thus posing a greater risk of electrostatic discharge (ESD). This, in turn, necessitates increasingly stringent requirements for ESD testing techniques. ICs are also known as chips.

[0082] HBM is currently the most commonly used model for ESD testing and is a necessary test item in product reliability verification. HBM's ESD refers to the accumulation of static electricity on the human body due to friction or other factors during walking. When this person touches the IC, the static electricity on the human body will enter the IC through the IC's pins and then discharge to ground. The discharge process will generate an instantaneous discharge current of several amperes in a short period of hundreds of nanoseconds (ns). This instantaneous large current is enough to damage the IC.

[0083] In related technologies, when using HBM for ESD testing, individual pins can be tested, or combinations of chip pins can be used for combined pin testing. However, chips have a large number of pins, and the pin combinations are random, resulting in low ESD testing efficiency, a large number of test samples required, and increased testing costs. Moreover, different combinations lead to different test results, resulting in poor consistency of test results.

[0084] Therefore, this application provides a chip testing method that, before chip testing, groups multiple pins of the chip according to pin voltage and pin type to determine multiple pin combinations, and then performs ESD testing based on multiple pin combinations, thereby improving testing efficiency.

[0085] In this embodiment of the application, the chip testing method of this application can be applied to chips in terminal devices, that is, it can perform ESD testing on chips integrated in terminal devices. Terminal devices can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device.

[0086] Currently, examples of such terminals include: mobile phones, tablets, computers with wireless transceiver capabilities (such as laptops and PDAs), mobile internet devices (MIDs), virtual reality (VR) devices, augmented reality (AR) devices, extended reality (XR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical care, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, Session Initiation Protocol (SIP) phones, Wireless Local Loop (WLL) stations, and personal digital assistants (PDAs). Assistant (PDA), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, in-vehicle devices, wearable devices, terminal devices in 5G networks or terminal devices in future evolved Public Land Mobile Networks (PLMNs), etc.

[0087] Furthermore, terminal devices can also be terminal devices in Internet of Things (IoT) systems. IoT is an important component of future information technology development. Its main technical characteristic is connecting objects to networks through communication technologies, thereby realizing an intelligent network that enables human-machine interconnection and machine-to-machine interconnection. IoT technology can achieve massive connectivity, deep coverage, and low power consumption through technologies such as narrowband (NB).

[0088] The technical solutions of this application and how they solve the aforementioned technical problems are described in detail below with specific embodiments. These specific embodiments may exist independently or in combination with each other. Identical or similar concepts or processes may not be repeated in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0089] Figure 1 This is a flowchart illustrating a chip testing method provided in an embodiment of this application. The method can be executed by a testing device or by a chip testing apparatus installed within the testing device. This apparatus can be a chip, a chip module, or an integrated development environment (IDE), etc. (See reference...) Figure 1 The method includes the following steps:

[0090] S101. Determine the pin information of the chip to be tested, wherein the pin information includes the pin identifier, pin type and pin voltage of each pin.

[0091] The measuring equipment can determine the pin information of the chip under test, which includes the pin identification information, pin type and pin voltage of each pin.

[0092] In one possible implementation, the pin information of the chip under test can be information input by the tester to the test equipment, so that the test equipment can obtain the pin information of the pin under test. The input of the pin information can be in the form of a file or other forms, which are not limited in this application.

[0093] For example, pin identification information may include pin number and pin name. Among the multiple pins of the chip under test, there are pins with the same pin name but different pin numbers. For example, Table 1 shows the pin numbers and pin names of multiple pins as an example. Among them, the pins corresponding to the pin name VSSCORE are AA12, AA14 and AA15, and the pins corresponding to the pin name RFCTL

[17] are A11 and A14.

[0094] Table 1

[0095]

[0096]

[0097] For example, pin types include one or more of the following: power supply pins, ground pins, and input / output (O / T) pins. Pin types may also include not-connected (N / C) pins, which are not connected to internal functional circuitry and are limited to the chip's package type. Whether to test N / C pins can be determined based on test requirements; the testing method is similar to that of other pins.

[0098] S102. Based on the pin identification information, pin voltage, and pin type, group multiple pins to obtain multiple pin combinations.

[0099] After determining the pin information of the chip to be tested, the testing equipment can group multiple pins according to the pin identification information, pin voltage, and pin type to obtain multiple pin combinations.

[0100] Since pin voltage has a significant impact on ESD testing, testing equipment can group multiple pins according to their pin voltage. For example, among multiple pins, due to the characteristics of power pins, power pins can be further grouped according to their pin voltage to enable multiple chips to complete the test together, reducing the probability of test failure due to electrostatic accumulation.

[0101] S103. Based on multiple pin combinations, perform electrostatic discharge (ESD) testing on the chip under test to obtain the chip test results.

[0102] After obtaining multiple pins, the testing equipment can perform ESD testing on the chip under test based on the combination of multiple pins, and obtain the chip test results of the chip under test.

[0103] For testing multiple pin combinations, in order to meet the requirements of current testing standards, the testing equipment should test each pin combination through at least three chips to increase the reliability of chip pin testing.

[0104] In this embodiment, the pin information of the chip under test is determined, including pin identification information, pin type, and pin voltage for each pin. Then, based on the pin identification information, pin voltage, and pin type, multiple pins are grouped to obtain multiple pin combinations. Based on these multiple pin combinations, an electrostatic discharge (ESD) test is performed on the chip under test to obtain the chip test results. This application provides a pin grouping method for ESD testing, improving testing efficiency.

[0105] The following describes another chip testing method provided in this application through another embodiment.

[0106] Figure 2 This is a flowchart illustrating a chip testing method provided in an embodiment of this application. The method can be executed by a testing device or by a chip testing apparatus installed within the testing device. This apparatus can be a chip, a chip module, an IDE, etc. (See reference...) Figure 2 The method includes the following steps:

[0107] S201. Determine the pin information of the chip to be tested, wherein the pin information includes the pin identifier, pin type and pin voltage of each pin.

[0108] For a description of the pin information, please refer to the above embodiments, which will not be repeated here.

[0109] S202. Based on the pin name and pin type, divide multiple pins into multiple initial groups, each initial group including multiple pin numbers with the same pin name.

[0110] The testing equipment can divide multiple pins into multiple initial combinations based on pin name and pin type.

[0111] In one possible implementation, the test equipment can divide multiple pins into multiple initial combinations in the following way:

[0112] The testing equipment can divide multiple pins into multiple first groups based on the pin name, with each first group corresponding to a pin name. Then, according to the pin type, the multiple first groups are divided into multiple initial groups.

[0113] For example, taking Table 1 as an example, Table 2 shows the first group after dividing multiple pins according to their pin names. The name of each first group can be a pin name, that is, each first group corresponds to one pin name.

[0114] Table 2

[0115]

[0116]

[0117] For example, for multiple initial combinations obtained by dividing multiple first combinations, the first combinations with the same pin type can be determined as one initial combination. Taking Table 2 as an example, the first combination corresponding to the power pin type (VDDARM1, VDDARM0, AVDD12_AFE1, AVDD_BB) is determined as one initial combination, including pins: AA13, M7, J28, G7. The first combination corresponding to the ground pin type (VSSCORE) is determined as one initial combination, including pins: AA12, AA14, AA15. The first combination corresponding to the I / O pin type (RFCTL

[17] , RFCTL

[12] ) is determined as one initial combination, including pins: A11, A14, A12.

[0118] S203. Sort the power supply type combinations according to the pin voltage to obtain the sorted power supply type combinations.

[0119] After determining multiple initial combinations, the test equipment can sort the power supply type combinations according to the pin voltage. Taking the pins in Table 2 as an example, the sorted power supply type combinations are shown in Table 3.

[0120] Table 3

[0121] VDDARM0(0.9V) M7 AVDD12_AFE1(1.2V) J28 AVDD_BB(1.8V) G7

[0122] S204. Determine multiple pin combinations, including sorted power type combinations, ground type combinations, and I / O type combinations.

[0123] S205. Based on multiple pin combinations, perform ESD testing on the chip under test to obtain the chip test results.

[0124] In one possible implementation, after determining multiple pin combinations, the test equipment can perform ESD testing in the following manner:

[0125] The first chip performs ESD testing on the sorted power type combinations to obtain the first test result. The second chip performs ESD testing on the ground type combinations to obtain the second test result. The third chip performs ESD testing on the I / O type combinations to obtain the third test result. Then, based on the first, second, and third test results, the chip test result is determined.

[0126] The chips to be tested include a first chip, a second chip, and a third chip. The first chip, the second chip, and the third chip are of the same type, meaning that the first chip, the second chip, and the third chip are chips of the same type produced in the same batch.

[0127] The following example illustrates ESD testing using the first chip to perform ESD testing on the sorted power type combinations:

[0128] For any pin in the power type combination, perform a positive mode electrostatic discharge between this pin and the first pin according to a preset voltage value, and perform a negative mode electrostatic discharge between this pin and the first pin according to a preset voltage value to determine the negative test result. Figure 3 For example, Figure 3 This is a schematic diagram illustrating ESD testing of chip pins as an example. Figure 3 For positive-mode electrostatic discharge, the positive terminal of the preset voltage (VESD) is connected to this pin, and the negative terminal is connected to the first pin. The preset voltage value can be, for example, 1500V or 2000V, meaning it can be tested separately with different voltage values. Conversely, for negative-mode electrostatic discharge, the negative terminal of the preset voltage is connected to this pin, and the positive terminal is connected to the first pin.

[0129] It is understood that the first test result includes the positive test result and the negative test result of each power type pin of the first chip. The test result may be whether the pin is damaged under the positive polarity of the preset voltage or whether the pin is damaged under the negative polarity of the preset voltage.

[0130] It is understandable that the second test result is obtained by performing ESD testing on the grounding type combination using the second chip, and the third test result is obtained by performing ESD testing on the I / O type combination using the third chip. The test methods are similar and will not be described in detail here.

[0131] Because power type combinations are highly prone to ESD testing failures, such as short test intervals (e.g., 300ms) due to electrostatic accumulation, it is necessary to regroup the power type combinations. To improve the success rate and efficiency of power type combination pin testing, the pins of the power type combinations can be further grouped using the following method, allowing multiple chips to test the pins of the further grouped combinations separately.

[0132] In one possible implementation, if the first test result indicates that the ESD test of the pin of the power type combination failed, it means that the pin of the power type combination needs to be tested again. The test equipment can divide the sorted power type combinations into i types based on the pin voltage, and test i types of combinations through i chips to obtain i test results. If the i test results indicate that the ESD test of the pin of the power type combination was successful, the chip test result is determined based on the i test results, the second test result, and the third test result.

[0133] Where i takes the values ​​2, 3, 4, 5, ..., until i test results indicate that the pin ESD test of the power type combination is successful. The chip to be tested includes i chips, that is, i chips are the chips in the chip to be tested.

[0134] For example, if the 0.9V power pin test in Table 3 fails, initially, since the characteristics of the 0.9V and 1.2V power pins are quite similar, the test equipment can sort the pins according to the power type combination, grouping the 0.9V and 1.2V into one category and the 1.8V power pin into another category, i.e., two categories of combinations. Then, two chips are used to test the pins of these two categories respectively. For example, if these two chips are #1 and #2, it can be understood that the power pins of the 0.9V and 1.2V combination of chip #1 are tested, and the power pins of the 1.8V combination of chip #2 are tested.

[0135] It is understandable that if the power supply pins of the 0.9V and 1.2V combination of chip #1 are tested and the test fails, then the 0.9V and 1.2V combination can be further divided into a combination corresponding to 0.9V and a combination corresponding to 1.2V. Then, the pins of these three combinations (0.9V, 1.2V and 1.8V) can be tested separately through three chips.

[0136] For example, Figure 4 This is a schematic diagram illustrating a power supply type combination grouping as an example of this application.

[0137] Of course, if the test fails when testing the power supply pins of the 1.8V type combination of chip #2, the 1.8V type combination can be grouped into two groups according to a preset grouping method. For example, the preset grouping method can be to divide them equally according to the quantity, or, for the pins of the 1.8V type combination, the test equipment can sort them according to the pin name or number, so that the test equipment can identify the pins that failed the test and group the pins that failed the test with the pins within a preset range in the sorting (for example, the first 20 and the last 20 of the pins). Other methods can also be used, and this application does not limit this.

[0138] As one possible implementation, taking the ESD test of the ground type combination through the second chip as an example, if one or more pins of the ground type combination fail to be tested, the pins of the ground type combination can also be grouped so that the pins of this type combination can be tested by multiple chips. For example, the pins of the 1.8V type combination can be grouped in the same way as described above, which will not be elaborated here.

[0139] In this embodiment, the pin information of the chip under test is determined, including the pin identifier, pin type, and pin voltage for each pin. Then, based on the pin name and pin type, multiple pins are divided into multiple initial combinations. The power type combinations are then sorted according to the pin voltage to obtain sorted power type combinations. Multiple pin combinations are determined, including sorted power type combinations, ground type combinations, and I / O type combinations. Based on these multiple pin combinations, an electrostatic discharge (ESD) test is performed on the chip under test to obtain the chip test results. This application provides a pin grouping method for ESD testing, improving testing efficiency. Furthermore, by clarifying the pin grouping method, the problem of a high number of test sample chips caused by disorganized grouping can be further solved, saving testing costs.

[0140] Figure 5 This is a schematic diagram of a chip testing device provided in an embodiment of this application. (Reference) Figure 5 The device 50 includes: a determination module 501, a grouping module 502, and a test module 503.

[0141] The determination module 501 is used to determine the pin information of the chip under test, wherein the pin information includes the pin identification information, pin type and pin voltage of each pin.

[0142] Grouping module 502 is used to group multiple pins according to pin identification information, pin voltage and pin type to obtain multiple pin combinations.

[0143] Test module 503 is used to perform electrostatic discharge (ESD) tests on the chip under test based on multiple pin combinations, and obtain the chip test results of the chip under test.

[0144] In one possible implementation, the pin identification information includes the pin number and pin name, and the pin type includes one or more of the following: power pin type, ground pin type, and input / output (I / O) pin type.

[0145] Grouping module 502 is specifically used for:

[0146] Based on the pin name and pin type, multiple pins are divided into multiple initial combinations. Each initial combination includes multiple pin numbers with the same pin name. The multiple initial combinations include power type combinations, ground type combinations, and input / output I / O type combinations.

[0147] Based on the pin voltage, the power supply type combinations are sorted to obtain the sorted power supply type combinations.

[0148] Determine multiple pin combinations, including sorted power type combinations, ground type combinations, and I / O type combinations.

[0149] In one possible implementation, the grouping module 502 is specifically used for:

[0150] Based on the pin name, multiple pins are divided into multiple first groups, and each first group corresponds to a pin name.

[0151] Based on pin type, multiple first combinations are divided into multiple initial combinations.

[0152] In one possible implementation, test module 503 is specifically used for:

[0153] The first chip performs ESD testing on the sorted power type combinations to obtain the first test result.

[0154] The second chip is used to perform ESD testing on the grounding type combination to obtain the second test result.

[0155] The third test result is obtained by performing ESD testing on the I / O type combination using a third chip.

[0156] The chip test results are determined based on the first test result, the second test result, and the third test result.

[0157] The chips to be tested include a first chip, a second chip, and a third chip, all of which are of the same type.

[0158] In one possible implementation, test module 503 is specifically used for:

[0159] If the first test result indicates that the pin ESD test of the power type combination failed, the sorted power type combinations are divided into class i based on the pin voltage.

[0160] i types of combinations are tested using i chips respectively, and i test results are obtained.

[0161] If the i test results indicate that the ESD test of the pin for the power type combination is successful, then the chip test result is determined based on the i test results, the second test result, and the third test result.

[0162] Where i takes the values ​​2, 3, 4, 5, ..., until i test results indicate that the pin ESD test of the power type combination is successful, and the chips to be tested include i chips.

[0163] In one possible implementation, test module 503 is specifically used for:

[0164] For any pin in the sorted power type combination, perform a forward mode electrostatic discharge between the pin and the first pin according to a preset voltage value to determine the forward test result. The first pin is any pin in the ground type combination and the I / O type combination.

[0165] A negative mode electrostatic discharge is performed between the pin and the first pin according to a preset voltage value to determine the negative test result.

[0166] The first test result is determined based on the positive and negative test results.

[0167] The apparatus in this embodiment can be used to execute the technical solutions of the above method embodiments. The specific implementation methods and technical effects are similar, and will not be described again here.

[0168] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 6 As shown, the electronic device 60 may include at least one processor 601 and a memory 602.

[0169] The memory 602 is used to store programs. Specifically, the program may include program code, which includes computer-executable instructions.

[0170] The memory 602 may include random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device.

[0171] The processor 601 is used to execute computer execution instructions stored in the memory 602 to implement the method described in the foregoing method embodiments. The processor 601 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0172] Optionally, the electronic device 60 may also include a communication interface 603. In specific implementations, if the communication interface 603, memory 602, and processor 601 are implemented independently, they can be interconnected via a bus to complete communication. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc., but this does not imply that there is only one bus or one type of bus.

[0173] Optionally, in a specific implementation, if the communication interface 603, memory 602, and processor 601 are integrated on a single chip, then the communication interface 603, memory 602, and processor 601 can communicate through an internal interface.

[0174] Electronic equipment 60 can be testing equipment, chips, chip modules, etc.

[0175] The electronic device in this embodiment can be used to execute the technical solutions of the above method embodiments. The specific implementation methods and technical effects are similar, and will not be repeated here.

[0176] This application provides a computer-readable storage medium, which may include various media capable of storing computer-executable instructions, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), RAM, a disk, or an optical disk. Specifically, the computer-readable storage medium stores computer-executable instructions, which, when executed by a computer, cause the technical solution shown in the above method embodiment to be executed. The specific implementation and technical effects are similar and will not be repeated here.

[0177] This application provides a computer program product, including a computer program. When the computer program is executed by a computer, the technical solution shown in the above method embodiment is executed. The specific implementation method and technical effect are similar, and will not be repeated here.

[0178] This application provides a chip that stores a computer program. When the computer program is executed by the chip, the technical solution shown in the above method embodiment is executed.

[0179] In one possible implementation, the chip can also be a chip module.

[0180] The chip in this embodiment can be used to execute the technical solution shown in the above method embodiment. The specific implementation method and technical effect are similar, and will not be described again here.

[0181] This application provides a module device, which includes a power module, a storage module, and a chip module.

[0182] The power module is used to provide power to the module devices.

[0183] Storage modules are used to store data and instructions.

[0184] The chip module in this embodiment can be used to execute the technical solution shown in the above method embodiment. The specific implementation method and technical effect are similar, and will not be repeated here.

[0185] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0186] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0187] In this application, "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document indicates that the preceding and following related objects have an "or" relationship.

[0188] "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where each of a, b, and c can be an element itself or a set containing one or more elements.

[0189] In this application, "at least one" means one or more. "More than one" means two or more. The descriptions of "first," "second," etc., appearing in the embodiments of this application are only for illustration and to distinguish the described objects, and have no order, nor do they indicate a special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application. For example, "first threshold" and "second threshold" are only used to distinguish different thresholds, and do not indicate that the size, priority, or importance of these two thresholds are different.

[0190] In this application, terms such as "exemplary," "in some embodiments," and "in other embodiments" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the term "exemplary" is used to present the concept in a specific manner.

[0191] In this application, the terms "of," "corresponding (relevant)," "corresponding," and "related" may sometimes be used interchangeably. It should be noted that, unless a distinction is emphasized, their intended meanings are consistent. Similarly, in the embodiments of this application, "communication" and "transmission" may sometimes be used interchangeably. It should be noted that, unless a distinction is emphasized, their intended meanings are consistent. For example, transmission can include sending and / or receiving, and can be a noun or a verb.

Claims

1. A chip testing method, characterized in that, include: Determine the pin information of the chip to be tested, wherein the pin information includes the pin identifier, pin type and pin voltage of each pin; Based on the pin identification information, the pin voltage, and the pin type, multiple pins are grouped to obtain multiple pin combinations; Based on the multiple pin combinations, the chip under test is subjected to electrostatic discharge (ESD) testing to obtain the chip test results. The pin identification information includes the pin number and the pin name, and the pin type includes one or more of the following: power pin type, ground pin type, and input / output (I / O) pin type; The multiple pins are grouped according to the pin identification information, the pin voltage, and the pin type to obtain multiple pin combinations, including: Based on the pin name and the pin type, the plurality of pins are divided into a plurality of initial combinations. Each initial combination includes a plurality of pin numbers with the same pin name. The plurality of initial combinations include power type combinations, ground type combinations, and input / output I / O type combinations. Based on the pin voltage, the power supply type combinations are sorted to obtain the sorted power supply type combinations; The plurality of pin combinations are defined as including the sorted power type combinations, the ground type combinations, and the I / O type combinations; Based on the aforementioned pin combinations, an electrostatic discharge (ESD) test is performed on the chip under test to obtain the chip test results, including: The first chip is used to perform ESD testing on the sorted power type combinations to obtain the first test result. The second chip is used to perform ESD testing on the grounding type combination to obtain the second test result; The I / O type combination is subjected to ESD testing using a third chip to obtain a third test result. If the first test result indicates that the pin ESD test of the power type combination fails, the sorted power type combinations are divided into class i combinations according to the pin voltage; The i-type combinations are tested using i chips respectively, resulting in i test results; If the i test results indicate that the pin ESD test of the power type combination is successful, then the chip test result is determined based on the i test results, the second test result, and the third test result; Wherein, i takes the values ​​2, 3, 4, 5, ... in sequence until the i test results indicate that the pin ESD test of the power type combination is successful, and the chip to be tested includes the i chips; The chip to be tested includes the first chip, the second chip, and the third chip, and the first chip, the second chip, and the third chip are chips of the same type.

2. The method according to claim 1, characterized in that, Based on the pin name and the pin type, the plurality of pins are divided into multiple initial combinations, including: Based on the pin names, the plurality of pins are divided into a plurality of first groups, and each first group corresponds to a pin name; According to the pin type, the plurality of first combinations are divided into the plurality of initial combinations.

3. The method according to claim 1, characterized in that, The first chip performs ESD testing on the sorted power type combinations to obtain a first test result, including: For any pin in the sorted power type combination, a forward mode electrostatic discharge is performed between the pin and the first pin according to a preset voltage value to determine the forward test result, wherein the first pin is any pin in the ground type combination and the I / O type combination; A negative mode electrostatic discharge is performed between the pin and the first pin according to the preset voltage value to determine the negative test result; The first test result is determined based on the positive test result and the negative test result.

4. A chip testing device, characterized in that, include: The determination module is used to determine the pin information of the chip under test, wherein the pin information includes the pin identifier information, pin type and pin voltage of each pin; The grouping module is used to group multiple pins according to the pin identification information, the pin voltage, and the pin type to obtain multiple pin combinations; The testing module is used to perform electrostatic discharge (ESD) testing on the chip under test based on the multiple pin combinations, and obtain the chip test results of the chip under test. The pin identification information includes the pin number and the pin name, and the pin type includes one or more of the following: power pin type, ground pin type, and input / output (I / O) pin type; The grouping module is specifically used for: Based on the pin name and the pin type, the plurality of pins are divided into a plurality of initial combinations. Each initial combination includes a plurality of pin numbers with the same pin name. The plurality of initial combinations include power type combinations, ground type combinations, and input / output I / O type combinations. Based on the pin voltage, the power supply type combinations are sorted to obtain the sorted power supply type combinations; The plurality of pin combinations are defined as including the sorted power type combinations, the ground type combinations, and the I / O type combinations; The test module is specifically used for: The first chip is used to perform ESD testing on the sorted power type combinations to obtain the first test result. The second chip is used to perform ESD testing on the grounding type combination to obtain the second test result; The I / O type combination is subjected to ESD testing using a third chip to obtain a third test result. If the first test result indicates that the pin ESD test of the power type combination fails, the sorted power type combinations are divided into class i combinations according to the pin voltage; The i-type combinations are tested using i chips respectively, resulting in i test results; If the i test results indicate that the pin ESD test of the power type combination is successful, then the chip test result is determined based on the i test results, the second test result, and the third test result; Wherein, i takes the values ​​2, 3, 4, 5, ... in sequence until the i test results indicate that the pin ESD test of the power type combination is successful, and the chip to be tested includes the i chips; The chip to be tested includes the first chip, the second chip, and the third chip, and the first chip, the second chip, and the third chip are chips of the same type.

5. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the chip testing method as described in any one of claims 1-3.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the chip testing method as described in any one of claims 1-3.

7. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the chip testing method according to any one of claims 1-3.

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