Full adder, chip and computing device

Abstract

The application relates to the field of integrated circuits, and provides a full adder, a chip and a computing device, wherein the full adder comprises: an inverter used for generating an inverted signal of a first addend signal input at a first addend end and providing the inverted signal to a first node; an exclusive OR circuit used for performing exclusive OR calculation on the first addend signal and a second addend signal input at a second addend end based on the inverted signal to obtain a carry propagation signal and provide the carry propagation signal to a second node; and an exclusive NOR circuit used for, in the case that the first addend signal is at a high level and the second addend signal is at a low level, pulling up a sum bit output signal by using a power supply signal under the control of an exclusive OR signal and a carry input signal if the carry input signal is at a low level, and taking the exclusive OR signal as the sum bit output signal if the carry input signal is at a high level. The problem that the output performance of the sum bit output signal is reduced due to pull-up delay at the second node when the first addend signal is at a high level and the second addend signal is at a low level can be avoided, and the performance of the full adder is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a full adder, a chip, and a computing device. Background Technology

[0002] A full adder is a fundamental computing unit in digital circuits, primarily used for addition and multiplication calculations. It is a crucial component of computing circuits, and reducing power consumption and improving performance are key design challenges for full adders. Therefore, improving the performance of full adders is a critical issue that the industry urgently needs to address. Summary of the Invention

[0003] This invention provides a full adder, a chip, and a computing device to solve the problem of how to improve the performance of a full adder in the prior art, thereby achieving an improvement in the performance of the full adder.

[0004] This invention provides a full adder, comprising:

[0005] An inverter, connected to the first addend terminal and the first node respectively, is used to generate an inverted signal from the first addend signal input to the first addend terminal and provide it to the first node;

[0006] An XOR circuit, connected to the first addend terminal, the second addend terminal, the first node, and the second node respectively, is used to perform an XOR calculation on the first addend signal and the second addend signal input at the second addend terminal based on the inverted signal to obtain a carry propagation signal and provide it to the second node;

[0007] An XOR circuit is connected to the first addend terminal, the second addend terminal, the first node, and the third node, respectively, and is used to perform XOR calculation on the first addend signal and the second addend signal based on the inverted signal to obtain an XOR signal and provide it to the third node;

[0008] The summation circuit is connected to the second node, the third node, the carry input terminal, the power supply terminal, and the sum output terminal, respectively. It is used to generate the sum output signal of the sum output terminal based on the carry propagation signal, the carry input signal provided by the carry input terminal, the XOR signal, and the power supply signal provided by the power supply terminal. Specifically, when the first addend signal is high and the second addend signal is low, if the carry input signal is low, the sum output signal is pulled up by the power supply signal under the control of the XOR signal and the carry input signal. If the carry input signal is high, the XOR signal is used as the sum output signal.

[0009] According to a full adder provided by the present invention, the XOR circuit includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, and a fifth switching transistor; the first switching transistor and the second switching transistor are P-type switching transistors; the third switching transistor, the fourth switching transistor, and the fifth switching transistor are N-type switching transistors.

[0010] The gate of the first switching transistor, the first source / drain of the second switching transistor, and the gate of the fifth switching transistor are respectively connected to the first addend terminal;

[0011] The gate of the second switching transistor, the first source / drain of the first switching transistor, the first source / drain of the third switching transistor, and the gate of the fourth switching transistor are respectively connected to the second addend terminal;

[0012] The second source / drain of the first switching transistor, the second source / drain of the second switching transistor, the second source / drain of the third switching transistor, and the first source / drain of the fourth switching transistor are respectively connected to the second node;

[0013] The second source / drain of the fourth switching transistor is connected to the first source / drain of the fifth switching transistor;

[0014] The second source / drain of the fifth switching transistor is connected to the ground terminal;

[0015] The gate of the third switching transistor is connected to the first node.

[0016] According to a full adder provided by the present invention, the summing circuit includes: a first transmission gate, a sixth switching transistor, a seventh switching transistor, and an eighth switching transistor; wherein the sixth and seventh switching transistors are P-type switching transistors; and the eighth switching transistor is an N-type switching transistor.

[0017] The gate of the sixth switching transistor, the input terminal of the first transmission gate, and the gate of the eighth switching transistor are respectively connected to the carry input terminal.

[0018] The first source / drain of the sixth switching transistor is connected to the power supply terminal, and the second source / drain of the sixth switching transistor is connected to the first source / drain of the seventh switching transistor;

[0019] The second source / drain of the seventh switching transistor, the output terminal of the first transmission gate, and the first source / drain of the eighth switching transistor are respectively connected to the sum-bit output terminal;

[0020] The first control terminal of the first transmission gate is connected to the second node;

[0021] The second control terminal of the first transmission gate, the gate of the seventh switching transistor, and the second source / drain of the eighth switching transistor are respectively connected to the third node;

[0022] When the first addend signal is high and the second addend signal is low, if the carry input signal is low, under the control of the XOR signal and the carry input signal, the sixth switch transistor and the seventh switch transistor turn on the power supply terminal and the sum output terminal, so as to pull up the sum output signal using the power supply signal;

[0023] When the first addend signal is high and the second addend signal is low, if the carry input signal is high, the eighth switching transistor is turned on under the control of the carry input signal to use the XOR signal as the sum output signal.

[0024] According to a full adder provided by the present invention, the XOR circuit includes: a ninth switching transistor, a tenth switching transistor, an eleventh switching transistor, a twelfth switching transistor, and a thirteenth switching transistor; wherein the ninth, tenth, and eleventh switching transistors are P-type switching transistors; and the twelfth and thirteenth switching transistors are N-type switching transistors.

[0025] The first source / drain of the ninth switching transistor, the gate of the tenth switching transistor, the first source / drain of the twelfth switching transistor, and the gate of the thirteenth switching transistor are respectively connected to the second addend terminal;

[0026] The gate of the eleventh switching transistor, the gate of the twelfth switching transistor, and the first source / drain of the thirteenth switching transistor are respectively connected to the first addend terminal.

[0027] The second source / drain of the ninth switching transistor, the first source / drain of the tenth switching transistor, the second source / drain of the twelfth switching transistor, and the second source / drain of the thirteenth switching transistor are respectively connected to the third node;

[0028] The gate of the ninth switching transistor is connected to the first node;

[0029] The second source / drain of the tenth switching transistor is connected to the first source / drain of the eleventh switching transistor;

[0030] The second source / drain of the eleventh switching transistor is connected to the power supply terminal.

[0031] According to a full adder provided by the present invention, the inverter includes: a fourteenth switching transistor and a fifteenth switching transistor; wherein, the fourteenth switching transistor is a P-type switching transistor; and the fifteenth switching transistor is an N-type switching transistor;

[0032] The gates of the fourteenth switching transistor and the fifteenth switching transistor are respectively connected to the first addend terminal;

[0033] The first source / drain of the fourteenth switching transistor is connected to the power supply terminal;

[0034] The second source / drain of the fourteenth switching transistor and the first source / drain of the fifteenth switching transistor are respectively connected to the first node;

[0035] The second source / drain of the fifteenth switching transistor is connected to the ground terminal.

[0036] A full adder provided by the present invention further includes: a carry circuit;

[0037] The carry circuit is connected to the second node, the third node, the carry input terminal, the second addend terminal, and the carry output terminal, respectively, and is used to generate the carry output signal of the carry output terminal based on the carry propagation signal, the XOR signal, the second addend signal, and the carry input signal.

[0038] According to a full adder provided by the present invention, the carry circuit includes: a second transmission gate and a third transmission gate;

[0039] The first control terminal of the second transmission gate and the second control terminal of the third transmission gate are respectively connected to the second node;

[0040] The second control terminal of the second transmission gate and the first control terminal of the third transmission gate are respectively connected to the third node;

[0041] The input terminal of the second transmission gate is connected to the second adder terminal;

[0042] The input terminal of the third transmission gate is connected to the carry input terminal;

[0043] The output terminals of the second transmission gate and the third transmission gate are respectively connected to the carry output terminal.

[0044] According to a full adder provided by the present invention, the P-type switching transistor is a PMOS; and the N-type switching transistor is an NMOS.

[0045] The present invention also provides a chip comprising a full adder as described in any of the above embodiments.

[0046] The present invention also provides a computing device comprising a chip as described in any of the above embodiments.

[0047] The full adder provided by this invention uses an inverter to generate an inverted signal from the first addend signal and provides it to the first node. An XOR circuit performs an XOR operation on the first and second addend signals based on the inverted signal to obtain a carry propagation signal and provides it to the second node. An XNOR circuit performs an XNOR operation on the first and second addend signals based on the inverted signal to obtain an XNOR signal and provides it to the third node. When the first addend signal is high and the second addend signal is low, if the carry input signal is low, the summing circuit can use a power supply signal to pull up the sum output signal under the control of the XNOR signal and the carry input signal. If the carry input signal is high, the summing circuit uses the XNOR signal as the sum output signal. This avoids the problem of reduced output performance of the sum output signal due to the pull-up delay at the second node when the first addend signal is high and the second addend signal is low, thus greatly improving the performance of the full adder. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0049] Figure 1 This is one of the structural schematic diagrams of the full adder provided by the present invention;

[0050] Figure 2 This is the second schematic diagram of the full adder provided by the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0052] The logical expression for a full adder is as follows:

[0053]

[0054] p'=p=A⊙B (2)

[0055]

[0056] Cout= p'·B+ p·Cin (4)

[0057] in, ⊙ represents XOR calculation, ⊙ represents XNOR calculation, A and B represent the two input addend signals, Cin represents the carry input signal, p represents the result of XOR calculation, p' represents the result of XNOR calculation, Sum represents the sum output signal, and Cout represents the carry output signal.

[0058] Full adders based on transistor logic offer advantages in area and power consumption, thus dominating the low-power full adder market. However, many full adder designs still suffer from issues such as non-full-swing output at internal nodes, low noise margin, poor stability, and excessive delay under minimum power conditions. Static inverters are typically added to full adder designs to optimize the non-full-swing problem at internal nodes; however, the introduction of inverters leads to excessive internal node delay. Among many low-power full adders, 16-transistor (T) and 20-transistor (20T) full adders have relatively low power consumption. However, in 16T full adder designs, the output nodes of the XOR and XNOR calculations exhibit threshold losses in certain states, significantly degrading the full adder's performance and preventing normal operation at low voltages. In 20T full adder designs, the threshold loss problem is compensated by an NMOS / PMOS transistor controlled by an inverter (A), but a race condition exists when A=1, B=0, and Cin=0, also resulting in a relatively high delay for the 20T full adder. Therefore, the performance of the full adder needs to be improved.

[0059] The following is combined Figures 1 to 2 A full adder according to the present invention is described.

[0060] This embodiment provides a full adder, such as Figure 1 As shown, it includes:

[0061] Inverter 110 is connected to the first addend terminal and the first node respectively, and is used to generate an inverted signal from the first addend signal input to the first addend terminal and provide it to the first node;

[0062] The XOR circuit 120 is connected to the first addend terminal, the second addend terminal, the first node, and the second node, respectively. It is used to perform XOR calculation on the first addend signal and the second addend signal input at the second addend terminal based on the inverted signal to obtain a carry propagation signal and provide it to the second node.

[0063] The XOR circuit 130 is connected to the first addend terminal, the second addend terminal, the first node, and the third node, respectively, and is used to perform XOR calculation on the first addend signal and the second addend signal based on the inverted signal to obtain an XOR signal and provide it to the third node;

[0064] The summation circuit 140 is connected to the second node, the third node, the carry input terminal, the power supply terminal, and the sum output terminal, respectively. It is used to generate the sum output signal of the sum output terminal based on the carry propagation signal, the carry input signal provided by the carry input terminal, the XOR signal, and the power supply signal provided by the power supply terminal. Specifically, when the first addend signal is high and the second addend signal is low, if the carry input signal is low, the sum output signal is pulled up by the power supply signal under the control of the XOR signal and the carry input signal. If the carry input signal is high, the XOR signal is used as the sum output signal.

[0065] A full adder requires two addend signals as input: a first addend signal A and a second addend signal B. The first addend terminal is used to input the first addend signal A, and the second addend terminal is used to input the second addend signal B.

[0066] Inverter 110 generates an inverted signal F of the first addend signal A and provides it to the first node. XOR circuit 120 performs an XOR operation on the first addend signal A and the second addend signal B based on the inverted signal F to obtain the XOR result p, which serves as the carry propagation signal. Therefore, p also represents the carry propagation signal, and the carry propagation signal p is provided to the second node. XNOR circuit 130 performs an XNOR operation on the first addend signal A and the second addend signal B based on the inverted signal F to obtain the XNOR result p', which serves as the XNOR signal. Therefore, p' also represents the XNOR signal, and the XNOR signal p' is provided to the third node. Summation circuit 140 generates a sum output signal Sun at the sum output terminal based on the carry propagation signal p, the carry input signal Cin provided by the carry input terminal, the XNOR signal p', and the power supply signal Vdd provided by the power supply terminal.

[0067] The first addend signal can be either high or low, where high level is 1 and low level is 0, i.e., A = 0 or A = 1. The second addend signal can also be high, i.e., B = 1, or low, i.e., B = 0. Therefore, the first and second addend signals input to the full adder can include the following cases:

[0068] A = 1, B = 1;

[0069] A = 1, B = 0;

[0070] A = 0, B = 1;

[0071] A = 0, B = 0.

[0072] Accordingly, the carry propagation signal p of the XOR circuit 120 includes:

[0073] When A = 1 and B = 1, p = 0;

[0074] When A = 1 and B = 0, p = 1;

[0075] When A = 0 and B = 1, p = 1;

[0076] When A=0 and B=0, p=0.

[0077] The XOR signal of the XOR circuit 130 includes:

[0078] When A = 1 and B = 1, p' = 1;

[0079] When A = 1 and B = 0, p' = 0;

[0080] When A = 0 and B = 1, p' = 0;

[0081] When A = 0 and B = 0, p' = 1.

[0082] When the first addend signal is high and the second addend signal is low (i.e., A = 1, B = 0), the pull-up of the second node is delayed, resulting in a decrease in the output performance of the sum output signal of the summing circuit 140. To solve this problem, in this embodiment, when A = 1, B = 0, and Cin = 0, the sum output signal of the full adder is not output using the carry propagation signal p at the second node, but rather using the XOR signal p' and the carry input signal Cin. Under the control of the XOR signal p' and the carry input signal Cin, the sum output signal Sum is pulled up using the power supply signal Vdd, thereby making the sum output signal Sum high (i.e., Sum = 1). When A=1, B=0, and Cin=1, the carry propagation signal p at the second node is not used to output the sum output signal Sum of the full adder. Instead, the XOR signal p' is used to output the sum output signal Sum, and the XOR signal p' is used as the sum output signal Sum. In this way, the problem of reduced output performance of the sum output signal caused by the pull-up delay at the second node can be avoided.

[0083] Based on this, the sum output signal Sum of the summing circuit 140 includes:

[0084] When p = 1 (p' = 0) and Cin = 1, Sum = 0;

[0085] When p = 1 (p' = 0) and Cin = 0, Sum = 1;

[0086] When p = 0 (p' = 1) and Cin = 1, Sum = 1;

[0087] When p = 0 (p' = 1) and Cin = 0, Sum = 0.

[0088] In this embodiment, inverter 110 generates an inverted signal for the first addend signal and provides it to the first node. XOR circuit 120 performs XOR calculation on the first and second addend signals based on the inverted signal to obtain a carry propagation signal and provides it to the second node. XOR circuit 130 performs XOR calculation on the first and second addend signals based on the inverted signal to obtain an XOR signal and provides it to the third node. When the first addend signal is high and the second addend signal is low, if the carry input signal is low, summing circuit 140 can use the power supply signal to pull up the sum output signal under the control of the XOR signal and the carry input signal. If the carry input signal is high, summing circuit 140 uses the XOR signal as the sum output signal. This avoids the problem of reduced output performance of the sum output signal due to the pull-up delay at the second node when the first addend signal is high and the second addend signal is low, thereby greatly improving the performance of the full adder.

[0089] Furthermore, such as Figure 1 As shown, the full adder may also include: a carry circuit 150;

[0090] The carry circuit 150 is connected to the second node, the third node, the carry input terminal, the second addend terminal, and the carry output terminal, respectively, and is used to generate the carry output signal of the carry output terminal based on the carry propagation signal, the XOR signal, the second addend signal, and the carry input signal.

[0091] The carry output signal Cout of the carry circuit 150 includes:

[0092] When p = 1 (p' = 0) and Cin = 1, Cout = 1;

[0093] When p = 1 (p' = 0) and Cin = 0, Cout = 0;

[0094] When p = 0 (p' = 1) and B = 1, Cout = 1;

[0095] When p = 0 (p' = 1) and B = 0, Cout = 0.

[0096] In this embodiment, the carry circuit 150 is not affected by the delay problem and can directly use the carry propagation signal p, the XOR signal p', the second addend signal B, and the carry input signal Cin to obtain the carry output signal.

[0097] In an exemplary embodiment, such as Figure 2 As shown, the carry circuit 150 includes: a second transmission gate T2 and a third transmission gate T3;

[0098] The first control terminal of the second transmission gate T2 and the second control terminal of the third transmission gate T3 are respectively connected to the second node;

[0099] The second control terminal of the second transmission gate T2 and the first control terminal of the third transmission gate T3 are respectively connected to the third node;

[0100] The input terminal of the second transmission gate T2 is connected to the second adder terminal;

[0101] The input terminal of the third transmission gate T3 is connected to the carry input terminal;

[0102] The output terminals of the second transmission gate T2 and the third transmission gate T3 are respectively connected to the carry output terminal.

[0103] In this embodiment, a selector controlled by a carry propagation signal p or an XOR signal p' is constructed using a second transmission gate T2 and a third transmission gate T3 to select whether to output the second addend signal B or the carry input signal Cin, thereby realizing the output of the carry output signal Cout.

[0104] in:

[0105] When p = 1 (p' = 0) and Cin = 1, the third transmission gate T3 is turned on to connect to the carry input terminal, thereby selecting the output carry input signal Cin, Cout = 1;

[0106] When p = 1 (p' = 0) and Cin = 0, the third transmission gate T3 is turned on to connect to the carry input terminal, thereby selecting the output carry input signal Cin, Cout = 0;

[0107] When p = 0 (p' = 1) and B = 1, the second transmission gate T2 is turned on and connected to the second adder terminal, thereby selecting the output of the second adder signal B, and Cout = 1;

[0108] When p = 0 (p' = 1) and B = 0, the second transmission gate T2 is turned on to the second addend terminal, thereby selecting the output of the second addend signal B, and Cout = 0.

[0109] In an exemplary embodiment, such as Figure 2As shown, the XOR circuit 120 includes: a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, a fourth switching transistor M4, and a fifth switching transistor M5; the first switching transistor M1 and the second switching transistor M2 are P-type switching transistors; the third switching transistor M3, the fourth switching transistor M4, and the fifth switching transistor M5 are N-type switching transistors.

[0110] The gate of the first switching transistor M1, the first source / drain of the second switching transistor M2, and the gate of the fifth switching transistor M5 are respectively connected to the first addend terminal;

[0111] The gate of the second switching transistor M2, the first source / drain of the first switching transistor M1, the first source / drain of the third switching transistor M3, and the gate of the fourth switching transistor M4 are respectively connected to the second addend terminal.

[0112] The second source / drain of the first switching transistor M1, the second source / drain of the second switching transistor M2, the second source / drain of the third switching transistor M3, and the first source / drain of the fourth switching transistor M4 are respectively connected to the second node;

[0113] The second source / drain of the fourth switching transistor M4 is connected to the first source / drain of the fifth switching transistor M5;

[0114] The second source / drain of the fifth switching transistor M5 is connected to the ground terminal GND;

[0115] The gate of the third switching transistor M3 is connected to the first node.

[0116] The P-type switching transistor in this invention can be a PMOS; the N-type switching transistor can be an NMOS. The switching transistor includes a gate, a first source / drain, a second source / drain, and a substrate. The substrate of a PMOS is connected to a power supply terminal, while the substrate of an NMOS is connected to a ground terminal. One of the first and second source / drain terminals is the source, and the other is the drain. In a PMOS, the terminal with the higher voltage is the source, and in an NMOS, the terminal with the lower voltage is the source.

[0117] In this embodiment, the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, the fourth switching transistor M4, and the fifth switching transistor M5 form a full-swing output XOR logic gate to perform the XOR operation between the first addend signal A and the second addend signal B, generating a carry propagation signal p. The working process is as follows:

[0118] The first addend signal A generates an inverted signal F under the action of inverter 110. Based on this:

[0119] When A=1 and B=1, the fourth switching transistor M4 and the fifth switching transistor M5 are connected to GND, and p=0;

[0120] When A=1 and B=0, the second switching transistor M2 is turned on and connected to the first adder terminal, p=1;

[0121] When A=0 and B=1, the third switching transistor M3 is turned on and connected to the second addend terminal, the first switching transistor M1 is turned on and connected to the second addend terminal, and p=1;

[0122] When A=0 and B=0, the third switching transistor M3 is connected to the second addend terminal, the first switching transistor M1 is connected to the second addend terminal, the second switching transistor M2 is connected to the first addend terminal, and p=0.

[0123] exist Figure 2 In the full adder shown, when A=1 and B=0, the third switching transistor M3 is delayed in turning off, which hinders the second switching transistor M2 from pulling up the second node, thus causing a delay. This solution improves the output logic of the sum bit output signal Sum in the critical state. When A=1, B=0, and Cin=0, the sum bit output signal Sum is pulled up by the XOR signal p' and the carry input signal Cin. When A=1, B=0, and Cin=1, the XOR signal p' is output by the carry input signal Cin. The full adder and bit output logic are realized without the carry propagation signal p, avoiding the impact of delay on the performance of the full adder.

[0124] In an exemplary embodiment, such as Figure 2 As shown, the summing circuit 140 includes: a first transmission gate T1, a sixth switching transistor M6, a seventh switching transistor M7, and an eighth switching transistor M8; wherein, the sixth switching transistor M6 and the seventh switching transistor M7 are P-type switching transistors; and the eighth switching transistor M8 is an N-type switching transistor.

[0125] The gate of the sixth switching transistor M6, the input terminal of the first transmission gate T1, and the gate of the eighth switching transistor M8 are respectively connected to the carry input terminal.

[0126] The first source / drain of the sixth switching transistor M6 is connected to the power supply terminal, and the second source / drain of the sixth switching transistor M6 is connected to the first source / drain of the seventh switching transistor M7.

[0127] The second source / drain of the seventh switching transistor M7, the output terminal of the first transmission gate T1, and the first source / drain of the eighth switching transistor M8 are respectively connected to the sum-bit output terminal;

[0128] The first control terminal of the first transmission gate T1 is connected to the second node;

[0129] The second control terminal of the first transmission gate T1, the gate of the seventh switching transistor M7, and the second source / drain of the eighth switching transistor M8 are respectively connected to the third node;

[0130] When the first addend signal is high and the second addend signal is low, if the carry input signal is low, under the control of the XOR signal and the carry input signal, the sixth switching transistor M6 and the seventh switching transistor M7 turn on the power supply terminal and the sum output terminal, so as to pull up the sum output signal using the power supply signal;

[0131] When the first addend signal is high and the second addend signal is low, if the carry input signal is high, the eighth switching transistor M8 is turned on under the control of the carry input signal to use the XOR signal p' as the sum output signal.

[0132] In this configuration, the first transmission gate T1, the sixth switching transistor M6, the seventh switching transistor M7, and the eighth switching transistor M8 form an XNOR gate (XNOR) between the carry input signal Cin and the carry propagation signal p, yielding the final sum output signal Sum.

[0133] When p = 1 (p' = 0) and Cin = 1, the eighth switching transistor M8 is turned on and connected to the third node, and Sum = 0;

[0134] When p = 1 (p' = 0) and Cin = 0, the sixth switching transistor M6 and the seventh switching transistor M7 are connected to the power supply terminal, and Sum = 1;

[0135] When p = 0 (p' = 1) and Cin = 1, the first transmission gate T1 is turned on to connect to the carry input terminal, and Sum = 1;

[0136] When p = 0 (p' = 1) and Cin = 0, the first transmission gate T1 is turned on to connect to the carry input terminal, and Sum = 0.

[0137] When A=1 and B=0, the turn-off of the third switching transistor M3 is delayed, hindering the second switching transistor M2 from pulling up the XOR signal p at the second node. This results in a slower turn-off of the first transmission gate T1 or a higher node delay in other full adders where the XOR signal p at the second node is directly pulled up, further reducing the output performance of the sum bit output signal Sum of the full adder. In this embodiment, the output logic of the sum bit output signal Sum in this critical state is improved. When A=1, B=0, and Cin=0, the XOR signal p' and the carry input signal Cin are used to pull up the sum bit output signal Sum through the sixth switching transistor M6 and the seventh switching transistor M7. When A=1, B=0, and Cin=1, the XOR signal p' is output by the carry input signal Cin. This allows the output logic of the full adder and the bit output signal Sum to be realized without the carry propagation signal p, thus optimizing the critical path.

[0138] In an exemplary embodiment, such as Figure 2 As shown, the inverter 110 includes a fourteenth switching transistor M14 and a fifteenth switching transistor M15; wherein, the fourteenth switching transistor M14 is a P-type switching transistor; and the fifteenth switching transistor M15 is an N-type switching transistor.

[0139] The gate of the fourteenth switching transistor M14 and the gate of the fifteenth switching transistor M15 are respectively connected to the first addend terminal.

[0140] The first source / drain of the fourteenth switching transistor M14 is connected to the power supply terminal;

[0141] The second source / drain of the fourteenth switching transistor M14 and the first source / drain of the fifteenth switching transistor M15 are respectively connected to the first node;

[0142] The second source / drain of the fifteenth switching transistor M15 is connected to the ground terminal GND.

[0143] As mentioned above, the P-type switching transistor can be a PMOS; the N-type switching transistor can be an NMOS.

[0144] In this embodiment, the problem of non-full swing of the internal nodes is optimized by adding a static inverter 110 to the design of the full adder. The full swing output of the internal nodes is suitable for operation at low voltage, making the full adder suitable for low-voltage scenarios.

[0145] In an exemplary embodiment, such as Figure 2As shown, the XOR circuit 130 includes: a ninth switching transistor M9, a tenth switching transistor M10, an eleventh switching transistor M11, a twelfth switching transistor M12, and a thirteenth switching transistor M13; wherein, the ninth switching transistor M9, the tenth switching transistor M10, and the eleventh switching transistor M11 are P-type switching transistors; and the twelfth switching transistor M12 and the thirteenth switching transistor M13 are N-type switching transistors.

[0146] The first source / drain of the ninth switching transistor M9, the gate of the tenth switching transistor M10, the first source / drain of the twelfth switching transistor M12, and the gate of the thirteenth switching transistor M13 are respectively connected to the second addend terminal.

[0147] The gate of the eleventh switching transistor M11, the gate of the twelfth switching transistor M12, and the first source / drain of the thirteenth switching transistor M13 are respectively connected to the first addend terminal.

[0148] The second source / drain of the ninth switching transistor M9, the first source / drain of the tenth switching transistor M10, the second source / drain of the twelfth switching transistor M12, and the second source / drain of the thirteenth switching transistor M13 are respectively connected to the third node;

[0149] The gate of the ninth switching transistor M9 is connected to the first node;

[0150] The second source / drain of the tenth switching transistor M10 is connected to the first source / drain of the eleventh switching transistor M11;

[0151] The second source / drain of the eleventh switching transistor M11 is connected to the power supply terminal.

[0152] Among them, the ninth switching transistor M9, the tenth switching transistor M10, the eleventh switching transistor M11, the twelfth switching transistor M12, and the thirteenth switching transistor M13 form a full-swing output XOR logic gate to realize the XOR of the first addend signal A and the second addend signal B, generating an XOR signal p', where:

[0153] The first addend signal A generates an inverted signal F under the action of inverter 110. Based on this:

[0154] When A=1 and B=1, the ninth switch transistor M9 is turned on and connected to the second addend terminal, the twelfth switch transistor M12 is turned on and connected to the second addend terminal, and the thirteenth switch transistor M13 is turned on and connected to the first addend terminal, and p'=1;

[0155] When A=1 and B=0, the ninth switching transistor M9 is turned on and connected to the second addend terminal, the twelfth switching transistor M12 is turned on and connected to the second addend terminal, and p'=0;

[0156] When A=0 and B=1, the thirteenth switching transistor M13 is turned on and connected to the first adder terminal, and p'=0;

[0157] When A=0 and B=0, the tenth switching transistor M10 and the eleventh switching transistor M11 are connected to the power supply terminal, and p'=1.

[0158] The XOR circuit 130 in this embodiment can perform XOR calculations for full-amplitude output.

[0159] Each of the three transmission gates—the first transmission gate T1, the second transmission gate T2, and the third transmission gate T3—is composed of a PMOS and an NMOS transistor connected in parallel. Therefore, Figure 2 The full adder shown includes 21 switching transistors, i.e., a 21T full adder. The full adder provided in this embodiment can operate stably and rapidly at low voltage. Although power consumption deteriorates slightly, latency is significantly improved, and the overall power-delay product (PDP) is superior to other full adders. Compared to typical low-power full adders like the CMOS 28T and advanced low-power full adders 16T, 20T, one 22T, and another 22T, at 200MHz, 1.2V, room temperature, and TT process, the power consumption of a single full adder in this invention deteriorates by 8.7%, 2.1%, 10.8%, -3%, and -1.3%, respectively; latency is optimized by 39.7%, 46.6%, 47%, 11.7%, and 11.2%, respectively; and the overall PDP is optimized by 34.4%, 45.5%, 40%, 14.4%, and 12.4%, respectively. Compared to CMOS 28T, 20T, and a 22T (16T cannot operate normally at 0.8V) under 0.8V, room temperature, and TT process conditions, the power consumption of a single full adder in this invention is reduced by 10.9%, 1.8%, and -2.3%, respectively; the delay is optimized by 34.3%, 37.1%, and 17.2%, respectively; and the overall PDP is optimized by 27.2%, 36%, and 16.2%, respectively. TT is an abbreviation for Typical-Typical, indicating that both NMOS and PMOS are typical processes.

[0160] The present invention also provides a chip, including the full adder provided in any of the above embodiments. Specific implementations of the chip can be found in the embodiments of the full adder described above, and will not be repeated here.

[0161] This embodiment also provides a computing device, including the chip provided in any of the above embodiments. Specific implementations of the computing device can be found in the embodiments of the chips described above, and will not be repeated here.

[0162] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A full adder, characterized in that, include: An inverter, connected to the first addend terminal and the first node respectively, is used to generate an inverted signal from the first addend signal input to the first addend terminal and provide it to the first node; An XOR circuit, connected to the first addend terminal, the second addend terminal, the first node, and the second node respectively, is used to perform an XOR calculation on the first addend signal and the second addend signal input at the second addend terminal based on the inverted signal to obtain a carry propagation signal and provide it to the second node; An XOR circuit is connected to the first addend terminal, the second addend terminal, the first node, and the third node, respectively, and is used to perform XOR calculation on the first addend signal and the second addend signal based on the inverted signal to obtain an XOR signal and provide it to the third node; The summation circuit is connected to the second node, the third node, the carry input terminal, the power supply terminal, and the sum output terminal, respectively. It is used to generate the sum output signal of the sum output terminal based on the carry propagation signal, the carry input signal provided by the carry input terminal, the XOR signal, and the power supply signal provided by the power supply terminal. Specifically, when the first addend signal is high and the second addend signal is low, if the carry input signal is low, the sum output signal is pulled up by the power supply signal under the control of the XOR signal and the carry input signal. If the carry input signal is high, the XOR signal is used as the sum output signal.

2. The full adder according to claim 1, characterized in that, The XOR circuit includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, and a fifth switching transistor; the first switching transistor and the second switching transistor are P-type switching transistors; the third switching transistor, the fourth switching transistor, and the fifth switching transistor are N-type switching transistors. The gate of the first switching transistor, the first source / drain of the second switching transistor, and the gate of the fifth switching transistor are respectively connected to the first addend terminal; The gate of the second switching transistor, the first source / drain of the first switching transistor, the first source / drain of the third switching transistor, and the gate of the fourth switching transistor are respectively connected to the second addend terminal; The second source / drain of the first switching transistor, the second source / drain of the second switching transistor, the second source / drain of the third switching transistor, and the first source / drain of the fourth switching transistor are respectively connected to the second node; The second source / drain of the fourth switching transistor is connected to the first source / drain of the fifth switching transistor; The second source / drain of the fifth switching transistor is connected to the ground terminal; The gate of the third switching transistor is connected to the first node.

3. The full adder according to claim 2, characterized in that, The summing circuit includes: a first transmission gate, a sixth switching transistor, a seventh switching transistor, and an eighth switching transistor; wherein the sixth and seventh switching transistors are P-type switching transistors; and the eighth switching transistor is an N-type switching transistor. The gate of the sixth switching transistor, the input terminal of the first transmission gate, and the gate of the eighth switching transistor are respectively connected to the carry input terminal. The first source / drain of the sixth switching transistor is connected to the power supply terminal, and the second source / drain of the sixth switching transistor is connected to the first source / drain of the seventh switching transistor; The second source / drain of the seventh switching transistor, the output terminal of the first transmission gate, and the first source / drain of the eighth switching transistor are respectively connected to the sum-bit output terminal; The first control terminal of the first transmission gate is connected to the second node; The second control terminal of the first transmission gate, the gate of the seventh switching transistor, and the second source / drain of the eighth switching transistor are respectively connected to the third node; When the first addend signal is high and the second addend signal is low, if the carry input signal is low, under the control of the XOR signal and the carry input signal, the sixth switch transistor and the seventh switch transistor turn on the power supply terminal and the sum output terminal, so as to pull up the sum output signal using the power supply signal; When the first addend signal is high and the second addend signal is low, if the carry input signal is high, the eighth switching transistor is turned on under the control of the carry input signal to use the XOR signal as the sum output signal.

4. The full adder according to claim 1, characterized in that, The XOR circuit includes: a ninth switching transistor, a tenth switching transistor, an eleventh switching transistor, a twelfth switching transistor, and a thirteenth switching transistor; wherein the ninth, tenth, and eleventh switching transistors are P-type switching transistors; and the twelfth and thirteenth switching transistors are N-type switching transistors. The first source / drain of the ninth switching transistor, the gate of the tenth switching transistor, the first source / drain of the twelfth switching transistor, and the gate of the thirteenth switching transistor are respectively connected to the second addend terminal; The gate of the eleventh switching transistor, the gate of the twelfth switching transistor, and the first source / drain of the thirteenth switching transistor are respectively connected to the first addend terminal. The second source / drain of the ninth switching transistor, the first source / drain of the tenth switching transistor, the second source / drain of the twelfth switching transistor, and the second source / drain of the thirteenth switching transistor are respectively connected to the third node; The gate of the ninth switching transistor is connected to the first node; The second source / drain of the tenth switching transistor is connected to the first source / drain of the eleventh switching transistor; The second source / drain of the eleventh switching transistor is connected to the power supply terminal.

5. The full adder according to claim 1, characterized in that, The inverter includes a fourteenth switching transistor and a fifteenth switching transistor; wherein the fourteenth switching transistor is a P-type switching transistor; and the fifteenth switching transistor is an N-type switching transistor. The gates of the fourteenth switching transistor and the fifteenth switching transistor are respectively connected to the first addend terminal; The first source / drain of the fourteenth switching transistor is connected to the power supply terminal; The second source / drain of the fourteenth switching transistor and the first source / drain of the fifteenth switching transistor are respectively connected to the first node; The second source / drain of the fifteenth switching transistor is connected to the ground terminal.

6. The full adder according to any one of claims 1 to 5, characterized in that, Also includes: Carry circuit; The carry circuit is connected to the second node, the third node, the carry input terminal, the second addend terminal, and the carry output terminal, respectively, and is used to generate the carry output signal of the carry output terminal based on the carry propagation signal, the XOR signal, the second addend signal, and the carry input signal.

7. The full adder according to claim 6, characterized in that, The carry circuit includes: a second transmission gate and a third transmission gate; The first control terminal of the second transmission gate and the second control terminal of the third transmission gate are respectively connected to the second node; The second control terminal of the second transmission gate and the first control terminal of the third transmission gate are respectively connected to the third node; The input terminal of the second transmission gate is connected to the second adder terminal; The input terminal of the third transmission gate is connected to the carry input terminal; The output terminals of the second transmission gate and the third transmission gate are respectively connected to the carry output terminal.

8. The full adder according to claim 2, characterized in that, The P-type switching transistor is a PMOS; the N-type switching transistor is an NMOS.

9. A chip, characterized in that, Includes the full adder as described in any one of claims 1 to 8.

10. A computing device, characterized in that, Includes the chip as described in claim 9.

Images