一种支持多种精度的乘法器及微处理器
By designing a multiplier that supports multiple precisions, and employing a parallel structure and resource reuse approach, the problem of high hardware overhead in existing technologies is solved, achieving low-overhead multiplication operations with multiple precisions, suitable for general-purpose processors and hardware accelerators.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAT UNIV OF DEFENSE TECH
- Filing Date
- 2023-05-25
- Publication Date
- 2026-07-17
AI Technical Summary
In existing technologies, multipliers and microprocessors that support multiple precisions have significant area and power consumption overhead issues, especially in machine learning applications, making it difficult to meet the computational requirements of the five data types: FP32, FP8-E5M2, FP8-E4M3, INT8, and UINT8.
Design a multiplier that supports multiple precisions, including an FP8 data path, a FIX8 data path, and an integrated data path. Through parallel structure and resource reuse, achieve parallel processing of FP8 and FIX8 multiplication operations, and integrate the results into 16-bit or 32-bit floating-point multiplication results to reduce hardware overhead.
It implements multiplication operations for five data types: FP32, FP8-E5M2, FP8-E4M3, INT8, and UINT8, reducing hardware area and power consumption overhead. It is suitable for various general-purpose processors and hardware accelerators, and provides greater computing power.
Smart Images
Figure CN116661733B_ABST