Apparatus and control method with dynamic pipelined error correction

Abstract

The application discloses a device and a control method with a dynamic pipeline error correction function, which comprises a function logic processing module and a data error detection and correction module that are executed in parallel, a group of pipeline registers and a bypass control module. The pipeline registers are used to store corrected data output by the data error detection and correction module, and the bypass control module is used to control the selection of one of the uncorrected data and the corrected data output from the pipeline registers. When the data error detection and correction module finds correctable errors, the control invalidates the current error transaction and controls the selection of the output of the corrected data in the pipeline registers, so that the function logic processing module uses the corrected data for processing. The application has the advantages of simple structure, high execution efficiency and reliability, low latency and strong flexibility.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit chip technology, and in particular to a device and control method with dynamic pipeline error correction function. Background Technology

[0002] Error correction is an essential technique when using large-scale memory in integrated circuits, playing a crucial role in ensuring chip functionality and improving yield. Error correction is a functional part of circuit design, implemented using an encoder and decoder to execute a specific error correction coding algorithm. The encoder obtains encoded data with redundant codes, which is then stored in memory. When data is needed, the read encoded data is sent to the decoder to obtain the decoded information. The meaning of this information varies depending on the encoding algorithm. For example, the commonly used ECC elliptic curve encryption algorithm outputs an error status, whether it is error-correctable, and the corrected data.

[0003] Error-correcting coding aims to improve system reliability. However, in high-performance applications such as processors, pipeline circuits are designed with high clock frequencies and have strict requirements for transaction response latency. This necessitates the following approach when using error-correcting coding algorithms: after reading data from the data body into the pipeline station, data error detection and correction are performed, and the status information is passed to the next pipeline station or the corrected data is used directly at the current station. This approach serializes decoding with subsequent functional logic, which can consume a clock cycle or disrupt the timing of other functional logic. Since data errors are generally considered low-probability events, the actual execution efficiency of this approach is low. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a device and control method with dynamic pipeline error correction function that is simple in structure, efficient in execution, highly reliable, low in latency and highly flexible, in response to the technical problems existing in the prior art.

[0005] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows:

[0006] An apparatus with dynamic pipelined error correction functionality includes a parallel-execution functional logic processing module and a data error detection and correction module. The functional logic processing module performs functional logic processing on transactions, while the data error detection and correction module detects and corrects data, outputting corrected data when a correctable error is detected. The apparatus also includes a set of pipeline registers and a bypass control module. The pipeline registers are located at the output of the data error detection and correction module to store the corrected data output by the module. The bypass control module controls the selection of one data path for output between uncorrected data and the corrected data output from the pipeline registers. When the data error detection and correction module detects a correctable error, it controls the invalidation of the current erroneous transaction and selects to output the corrected data from the pipeline registers, enabling the functional logic processing module to use the corrected data for processing.

[0007] Furthermore, the bypass control module includes a selection circuit and a control circuit connected to each other. The selection circuit receives uncorrected data and corrected data output from the pipeline register, respectively. The control circuit generates a control signal based on the inspection result of the data error detection and correction module to control the selection circuit to select and output one data path.

[0008] Furthermore, the selection circuit is a 2-to-1 selector, with its two input terminals connected to the input terminal of the data error detection and correction module and the output terminal of the pipeline register, respectively, and its control terminal connected to the output terminal of the control circuit.

[0009] Furthermore, in the normal state, the functional logic processing module processes the data before correction, and the control circuit generates a first control signal to control the selection circuit to select and output uncorrected data. When the data error detection and correction module finds a correctable error, it generates a second control signal to control the selection and output of the data in the pipeline register to the functional logic processing module for processing.

[0010] Furthermore, the bypass control module is also used to control the output of uncorrected data when the pipeline has an idle cycle, so that the pipeline register enters the bypass state and the pipeline resumes normal operation, so that the functional logic processing module can use the uncorrected data for processing.

[0011] The control method using the aforementioned device with dynamic pipeline error correction function includes the following steps:

[0012] S01. The pipeline register is initially in a bypass state, the pipeline is working in a normal state, the functional logic processing module and the data error detection and correction module are executed in parallel, and the functional logic processing module uses uncorrected data that has not been processed by the data error detection and correction module for processing;

[0013] S02. When the data error detection and correction module detects a correctable error, it controls the current erroneous transaction to fail and enables the pipeline register to output corrected data. The functional logic processing module uses the corrected data for processing, and the pipeline enters the error correction state.

[0014] Furthermore, after the pipeline enters the error correction state in step S02, all data is first checked and corrected by the data error detection and correction module, and the next cycle functional logic processing module uses the corrected data in the pipeline register for processing.

[0015] Furthermore, after step S02, a correction mode exit control step S03 is also included. Step S03 includes: when the pipeline has an idle cycle, the control selects to output uncorrected data, so that the pipeline register enters the bypass state, and the pipeline resumes normal operation, so that the functional logic processing module can use the uncorrected data for processing.

[0016] Compared with the prior art, the advantages of the present invention are as follows:

[0017] 1. The present invention provides a device and control method with dynamic pipeline error correction function. When a series of transactions enter the pipeline process, and a transaction in the pipeline encounters a correctable error, the pipeline structure can be dynamically adjusted during data error correction by combining the simple control logic of the bypass control module. This extends the pipeline without interruption, allowing the functional logic to execute transactions using the corrected data, thus realizing the dynamic pipeline error correction function. While ensuring that error detection and correction are executed in parallel with the functional logic, it also enables the correctable transactions to be completed normally. This avoids the constant delay of serial execution and eliminates the need to resend transactions to complete error correction, thereby improving the efficiency and reliability of error correction execution while reducing implementation complexity. It effectively balances the system's reliability, efficiency, and complexity.

[0018] 2. The device and control method of the present invention with dynamic pipeline error correction function make the pipeline delay adjustable through the bypass structure and make its output data determined by the post-station control logic. It can also achieve the purpose of separating the combined logic delay of the two stations before and after the bypass, and ensure the low delay of the pipeline without reducing the system reliability.

[0019] 3. The device and control method of the present invention with dynamic pipeline error correction function can realize the extension of pipeline structure to adapt to data error correction, identify idle periods and automatically complete the exit of the error correction state. When the system is under high load and fully pipelined, the system is not sensitive to latency, and the impact of the increased cost due to error correction and serial execution of processing is very small. When not under full load, the pipeline can quickly switch to the low-latency normal state using idle periods, so that the switching can be transparent and seamless under any load condition without the need for global detection and clearing of the pipeline. At the same time, by monitoring the status of the pipeline, the pipeline switching logic can realize the characteristic of not interfering with transactions when extending the pipeline and shrinking the pipeline during idle periods, thus realizing the automatic scaling of the pipeline in a dynamic adaptive manner. Attached Figure Description

[0020] Figure 1 This is a schematic diagram illustrating the structural principle of implementing the pipeline register bypass function in this embodiment.

[0021] Figure 2 This is a schematic diagram of the device with dynamic pipeline error correction function in this embodiment. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.

[0023] As disclosed in this invention, unless the context clearly indicates otherwise, words such as "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. The terms "first," "second," and similar terms used in this invention disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, words such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Words such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0024] like Figure 1 , 2As shown, the device with dynamic pipeline error correction function in this embodiment includes a parallel-execution functional logic processing module and a data error detection and correction module. The functional logic processing module is used to perform functional logic processing on transactions, and the data error detection and correction module is used to detect and correct data, and output corrected data when a correctable error is found. It also includes a set of pipeline registers and a bypass control module. The pipeline registers are set at the output end of the data error detection and correction module to store the corrected data output by the data error detection and correction module. The bypass control module is used to control the selection of one of the uncorrected data and the corrected data output by the pipeline registers to output data, so as to realize the bypass function. When the data error detection and correction module finds a correctable error, it controls the invalidation of the current erroneous transaction and selects to output the corrected data in the pipeline register, so that the functional logic processing module can use the corrected data for processing.

[0025] In this embodiment, through the above structure, when a series of transactions enter the pipeline and a transaction in the pipeline encounters a correctable error, the pipeline structure can be dynamically adjusted during data error correction by combining the simple control logic of the bypass control module. This allows the pipeline to be extended without interruption so that the functional logic can use the corrected data to execute transactions, thus realizing the dynamic pipeline error correction function. This can improve the efficiency and reliability of error correction execution while reducing implementation complexity, effectively balancing system reliability, efficiency, and complexity. Furthermore, the bypass structure makes the pipeline delay adjustable and the output data determined by the post-station control logic. It can also achieve the purpose of separating the combined logic delay of the two stations before and after the bypass, ensuring low pipeline latency without reducing system reliability.

[0026] In this embodiment, the bypass control module includes a selection circuit and a control circuit that are interconnected. The selection circuit receives uncorrected data and corrected data output from the pipeline register, respectively. The control circuit generates a control signal based on the inspection results of the data error detection and correction module to control the selection circuit to select and output one data path.

[0027] like Figure 1 , 2As shown, the pipeline register is constructed using a set of registers Reg. The selection circuit specifically employs a multiplexer (MUX) to implement bypass functionality. The two inputs of the multiplexer are connected to the input of the data error detection and correction module and the output of the pipeline register, respectively, to receive data before the error detection and correction module (uncorrected data) and data stored in register Reg after the error detection and correction module (corrected data). The control terminal is connected to the output of the control circuit to achieve a two-to-one output control function based on the control signal generated by the control circuit. The corrected data is input to the pipeline register, and the register's output, along with the uncorrected data, serves as the data input source for the multiplexer. The control signal output from the register selects which data to output. The multiplexer's output, after functional logic processing, becomes the final output result sent to the next stage.

[0028] In this embodiment, under normal conditions, the functional logic processing module processes data using the uncorrected data, and the control circuit generates a first control signal to control the selection circuit to select uncorrected data for output; that is, functional logic processing and data error correction are executed in parallel. When the data error detection and correction module detects a correctable error, it generates a second control signal to control the selection of data in the output pipeline register for processing by the functional logic processing module; that is, functional logic processing and data error correction are executed serially, and the functional logic uses corrected data for processing. Specifically, the control signal of the control circuit is based on the output control of the data error correction logic before the extended pipeline register (pipeline register Reg) after it has been stored in the register. Specifically, if the corrected data stored in the pipeline register Reg is invalid, the control generates a first control signal to maintain the use of the uncorrected data for functional processing; if the corrected data stored in the pipeline register Reg is valid, the control generates a second control signal to enable the pipeline register Reg to output data for functional logic processing.

[0029] In this embodiment, the bypass control module is also used to control the output of uncorrected data when the pipeline has an idle cycle, causing the pipeline register to enter a bypass state and the pipeline to resume normal operation, so that the functional logic processing module can use the uncorrected data for processing. Through the above control functions of the bypass control module, the pipeline can automatically recover to the normal state when it has an idle cycle, improving the overall processing efficiency of the system.

[0030] This embodiment, through the above structure, can extend the pipeline structure to adapt to data error correction and automatically exit the error correction state by recognizing idle periods. When the system is under high load and fully pipelined, since the system is not sensitive to latency, the impact of the increased cost due to error correction and serial execution of processing is very small. When not under full load, the pipeline can quickly switch to a low-latency normal state using idle periods, so that the switching can be transparent and seamless under any load condition without the need for global detection and clearing of the pipeline. At the same time, by monitoring the status of the pipeline, the pipeline switching logic can utilize the characteristic of not interfering with transactions when extending the pipeline and shrinking the pipeline during idle periods to achieve dynamic adaptive automatic scaling of the pipeline.

[0031] In this embodiment, the device with dynamic pipeline error correction function may be in two types of states during the lifecycle of pipeline processing transactions:

[0032] Normal state: Decoding and functional logic are processed in parallel; the decoder result is discarded, and the processing result is output.

[0033] Error correction state: Decoding and functional logic are processed sequentially. Within two cycles, the decoding result is first entered into the pipeline, and then the functional logic processes the error-corrected data and outputs the processing result.

[0034] The process of transitioning between the two states mentioned above during transaction processing is as follows:

[0035] 1. The process of entering error correction mode includes the following steps:

[0036] 1) After data is read from the storage unit, it enters the data storage station where decoding and functional logic processing are performed simultaneously;

[0037] 2) When a correctable error occurs, the transaction on this site is invalidated, and the corrected data is sent to the error correction result storage station;

[0038] 3) When the error correction result storage station is valid, the functional logic switches to selecting the data from the error correction result storage station for processing;

[0039] 2. The process of exiting error correction mode includes the following steps:

[0040] 1) When the decoding pipeline is idle, prepare the failure correction result storage station;

[0041] 2) After one clock cycle, the error correction result register becomes invalid, and the functional logic switches to select the data register for processing.

[0042] In this embodiment, the control logic of the bypass control module is as follows:

[0043] When in normal condition, if an error is detected during the error detection and correction cycle, the error detection logic will disable the output of the functional logic and enable the pipeline register of the error correction data input, generating a selector control signal to select the error-corrected data. After the cycle ends, the multiplexer outputs the error-corrected data to the functional logic for processing, and outputs the correct result to the next station.

[0044] When in error correction mode, the device structure (such as...) Figure 2 In reality, there are two stations. Within one clock cycle, if the current station is in an idle state with no transactions, the multiplexer control signal output to the register switches to select uncorrected data. After the cycle ends, the transaction processing results of the previous station reach the next stage, and the idle transactions of the previous station are compressed and discarded. The two stations become one station, and the new transactions enter the pipeline in normal state.

[0045] The detailed steps of the control method using the device with dynamic pipeline error correction function described above in this embodiment include:

[0046] S01. The pipeline register is initially in bypass state, the pipeline is working in normal state, the functional logic processing module and the data error detection and correction module are executed in parallel, and the functional logic processing module uses the uncorrected data that has not been processed by the data error detection and correction module for processing;

[0047] S02. When the data error detection and correction module detects a correctable error, it controls the current erroneous transaction to fail and enables the pipeline register to output corrected data. The functional logic processing module uses the corrected data for processing, and the pipeline enters the error correction state.

[0048] In step S02 of this embodiment, after the pipeline enters the error correction state, all data is first checked and corrected by the data error detection and correction module. The next cycle functional logic processing module uses the corrected data in the pipeline register for processing.

[0049] This embodiment also includes a correction mode exit control step S03 after step S02. Step S03 includes: when the pipeline has an idle cycle, the control selects to output uncorrected data, so that the pipeline register enters the bypass state, and the pipeline resumes normal operation, so that the functional logic processing module can use the uncorrected data for processing.

[0050] In a specific application embodiment, the pipeline switching logic process includes the following steps:

[0051] 1) The pipeline register is initially set to bypass mode by default, and the pipeline operates in normal mode;

[0052] 2) Under normal circumstances, data error detection and correction and functional logic are executed in parallel at the same station;

[0053] 3) When data error detection finds a correctable error, the current erroneous transaction is marked as invalid, the bypassed pipeline register is enabled, and in the next cycle, the multiplexer selects the data of the extended pipeline register Reg (i.e., the register after data error detection and correction).

[0054] 4) After one cycle of error detection, the functional logic processes the corrected data, and the transaction is completed normally;

[0055] 5) After this cycle, the pipeline registers are not bypassed, and the pipeline is in error correction mode;

[0056] 6) In error correction mode, the data is first checked and corrected. The next cycle of the extended pipeline register uses the corrected data for processing (regardless of whether an error can be corrected).

[0057] 7) When the pipeline has an idle cycle, the control logic causes the multiplexer to select the uncorrected data output in the next cycle, and the transactions after the pipeline register are processed normally.

[0058] 8) After this cycle ends, the pipeline register is in bypass mode, and the pipeline resumes normal operation.

[0059] This invention adjusts the pipeline structure by distinguishing between normal and error-correction states, which can effectively achieve a balance between system reliability and efficiency. While ensuring that error detection and correction and functional logic are executed in parallel, it enables error-correctable transactions to be completed normally, avoiding the constant delay of serial execution and eliminating the need to use transaction retransmission to complete error correction.

[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.

Claims

1. A device with dynamic pipeline error correction function, comprising a parallel-executed functional logic processing module and a data error detection and correction module, wherein the functional logic processing module is used to perform functional logic processing on transactions, and the data error detection and correction module is used to detect and correct data, and output corrected data when a correctable error is detected, characterized in that, It also includes a set of pipeline registers and a bypass control module. The pipeline registers are located at the output of the data error detection and correction module to store the corrected data output by the data error detection and correction module. The bypass control module is used to control the selection of one of the uncorrected data and the corrected data output by the pipeline registers for output. When the data error detection and correction module detects a correctable error, it controls the current error transaction to be invalidated and selects to output the corrected data in the pipeline register so that the functional logic processing module can use the corrected data for processing. The bypass control module is also used to control the output of uncorrected data when the pipeline has an idle cycle, so that the pipeline register enters the bypass state and the pipeline resumes normal operation, so that the functional logic processing module can use the uncorrected data for processing.

2. The device with dynamic pipeline error correction function according to claim 1, characterized in that, The bypass control module includes a selection circuit and a control circuit that are interconnected. The selection circuit receives uncorrected data and corrected data output from the pipeline register. The control circuit generates a control signal based on the inspection results of the data error detection and correction module to control the selection circuit to select and output one data path.

3. The device with dynamic pipeline error correction function according to claim 2, characterized in that, The selection circuit is a 2-to-1 selector. The two input terminals of the selector are connected to the input terminal of the data error detection and correction module and the output terminal of the pipeline register, respectively, and the control terminal is connected to the output terminal of the control circuit.

4. The device with dynamic pipeline error correction function according to claim 2, characterized in that, In normal operation, the functional logic processing module processes the data before correction. The control circuit generates a first control signal to control the selection circuit to select and output uncorrected data. When the data error detection and correction module detects a correctable error, it generates a second control signal to control the selection and output of the data in the pipeline register to the functional logic processing module for processing.

5. A control method using the device with dynamic pipeline error correction function according to any one of claims 1 to 4, characterized in that the step include: S01. The pipeline register is initially in a bypass state, the pipeline is working in a normal state, the functional logic processing module and the data error detection and correction module are executed in parallel, and the functional logic processing module uses uncorrected data that has not been processed by the data error detection and correction module for processing; S02. When the data error detection and correction module detects a correctable error, it controls the current erroneous transaction to fail and enables the pipeline register to output corrected data. The functional logic processing module uses the corrected data for processing, and the pipeline enters the error correction state.

6. The control method of the device with dynamic pipeline error correction function according to claim 5, characterized in that, In step S02, after the pipeline enters the error correction state, all data is first checked and corrected by the data error detection and correction module. The next cycle functional logic processing module uses the corrected data in the pipeline register for processing.

7. The control method of the device with dynamic pipeline error correction function according to claim 5 or 6, characterized in that, The step S02 is followed by a correction mode exit control step S03, which includes: when the pipeline has an idle cycle, the control selects to output uncorrected data, so that the pipeline register enters the bypass state, and the pipeline resumes normal operation, so that the functional logic processing module can use the uncorrected data for processing.

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