A failure analysis method and device based on chip pin testing

Abstract

The application discloses a kind of based on chip pin test failure analysis method and device.The method comprises the following steps of: obtaining chip pin test data in wafer test stage, determining the failure number of each bump in chip from pin test data;According to the failure number, select risk bump from the bump in chip, and count the coordinate position of risk bump, determine the risk area of chip according to the coordinate position;Import the failure log of failed chip, obtain the original failure path set by parsing failure log, and filter the failure data points corresponding to risk area from original failure path set;Failure analysis and verification are carried out on failure data points by using electrical failure analysis tool.The technical scheme of the application defines and evaluates risk area using chip pin test data, feeds back risk area information to electrical failure analysis tool, reduces the range of failure data analysis and verification, speeds up the analysis speed, and improves accuracy.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a failure analysis method and apparatus based on chip pin testing. Background Technology

[0002] During chip manufacturing, various factors such as manufacturing process fluctuations, transportation disruptions, and other external forces can easily lead to numerous cracks and damage within the chip. This physical failure can cause irreversible failures in subsequent testing, even causing the chip to fail during DC testing, rendering subsequent functional testing impossible. For these chips, it is often necessary to combine on-site test data with various failure analysis methods to quickly identify the cause of failure and pinpoint the problem, thereby minimizing chip yield losses. However, when chip test data is scarce, analyzing the cause and location of chip failures becomes increasingly difficult.

[0003] like Figure 1 As shown, in traditional solutions, when chips encounter problems such as breakage and cracks, the approach typically involves directly using physical failure methods to perform hotspot analysis and physical cross-section observation of the failed chip. In addition, non-destructive failure analysis methods such as Electrical Failure Analysis (EFA) can be used, along with location support, to collect data from the SCAN diagnostic tool on the test equipment. This data is then analyzed using specialized tools to help find the cause and location of the failure. However, the above solutions do not pre-identify the problem area before directly inputting it into the EFA tool, affecting the accuracy of the search. Indiscriminately loading SCAN logs into the analysis will increase EFA time; for example, SCAN analysis may also capture other problems, resulting in significant noise. Furthermore, directly using destructive failure analysis methods such as chip-level Physical Failure Analysis (PFA) to perform physical and material analysis on hotspots or cross-sections of the die (DIE) region will increase the analysis difficulty and cost. Summary of the Invention

[0004] In view of this, the present invention provides a failure analysis method and apparatus based on chip pin testing, aiming to solve the problems of high difficulty, high cost and insufficient data accuracy in failure analysis.

[0005] The present invention provides a failure analysis method based on chip pin testing in a first aspect, comprising:

[0006] Obtain chip pin test data during the wafer testing phase, and determine the number of failures for each bump in the chip from the pin test data;

[0007] Based on the number of failures, risky bumps are selected from the bumps in the chip, and the coordinate positions of the risky bumps are counted. The risk area of ​​the chip is determined based on the coordinate positions.

[0008] Import the failure logs of the failed chip, parse the failure logs to obtain the original failure path set, and filter out the failure data points corresponding to the risk area from the original failure path set;

[0009] The failure data points were analyzed and verified using electrical failure analysis tools.

[0010] Preferably, determining the number of failures for each bump in the chip from the pin test data further includes:

[0011] Statistical analysis of failed bumps is performed on wafer pin testing items to obtain electrical test data of the bumps. By observing failed bumps in DC pin-related tests, the number of failures for each bump is obtained.

[0012] Preferably, the step of selecting risky bumps from the bumps in the chip based on the number of failures and statistically analyzing the coordinate positions of the risky bumps further includes:

[0013] By using chip-level physical mapping, the set of bumps with the highest number of failures among the failed bumps is obtained as a set of risk bumps and added to the risk bump list.

[0014] Based on the location of all risk bumps in the chip layout, coordinate queries and markings are performed to obtain the set of center coordinates of all risk bumps.

[0015] Preferably, determining the risk area of ​​the chip based on coordinate location further includes:

[0016] For the coordinate set of n risk convex points, perform separate statistics on the X-coordinate set and the Y-coordinate set:

[0017] X_list = {x1,x2,x3,...,xn};

[0018] Y_list = {y1, y2, y3, ..., yn}.

[0019] Where xn and yn represent the x-coordinate and y-coordinate of the nth risk convex point, respectively;

[0020] Obtain the maximum and minimum values ​​of the x-coordinate and the maximum and minimum values ​​of the y-coordinate of the risk convex point, that is:

[0021] Xmin=minimum(x1,x2,x3,x4,...,xn);

[0022] Xmax=maximum(x1,x2,x3,x4,...,xn);

[0023] Ymin=minimum(y1,y2,y3,y4,...,yn);

[0024] Ymax=maximum(y1,y2,y3,y4,...,yn);

[0025] Where minimum and maximum are functions for finding the minimum and maximum values, respectively;

[0026] The risk area can be defined as the following constraint box:

[0027] Bounding box={Xmin,Ymin,Xmax,Ymax};

[0028] Expand the x and y coordinates of the constraint box outwards to obtain a coordinate filtering window:

[0029] C-Filter Box =

[0030] {Xmin-offset,Ymin-offset,Xmax+offset,Ymax+offset}.

[0031] Where offset is the outward offset of the horizontal and vertical coordinates of the constraint box.

[0032] Preferably, the step of filtering the failure data points corresponding to the risk area from the original failure path set further includes:

[0033] Extract the coordinates of the center points of the original set of failure paths to form a set of failure path center coordinate data.

[0034] The coordinate filtering window is used to filter the set of center coordinates of the failure path, and only failure data points whose coordinates are located within the coordinate filtering window are retained.

[0035] In a second aspect, the present invention provides a failure analysis apparatus based on chip pin testing, comprising:

[0036] The test data acquisition module is used to acquire chip pin test data during the wafer testing stage, and determine the number of failures of each bump in the chip from the pin test data;

[0037] The risk area determination module is used to select risk bumps from the bumps in the chip according to the number of failures, count the coordinate positions of the risk bumps, and determine the risk area of ​​the chip according to the coordinate positions.

[0038] The failure data filtering module is used to import the failure logs of the failed chip, parse the failure logs to obtain the original failure path set, and filter out the failure data points corresponding to the risk area from the original failure path set.

[0039] The failure analysis module is used to perform failure analysis and verification on the failure data points using electrical failure analysis tools.

[0040] Preferably, the test data acquisition module is further configured as follows:

[0041] Statistical analysis of failed bumps is performed on wafer pin testing items to obtain electrical test data of the bumps. By observing failed bumps in DC pin-related tests, the number of failures for each bump is obtained.

[0042] Preferably, the risk area determination module is further configured as follows:

[0043] By using chip-level physical mapping, the set of bumps with the highest number of failures among the failed bumps is obtained as a set of risk bumps and added to the risk bump list.

[0044] Based on the location of all risk bumps in the chip layout, coordinate queries and markings are performed to obtain the set of center coordinates of all risk bumps.

[0045] Preferably, the risk area determination module is further configured as follows:

[0046] For the coordinate set of n risk convex points, perform separate statistics on the X-coordinate set and the Y-coordinate set:

[0047] X_list = {x1,x2,x3,...,xn};

[0048] Y_list = {y1, y2, y3, ..., yn}.

[0049] Where xn and yn represent the x-coordinate and y-coordinate of the nth risk convex point, respectively;

[0050] Obtain the maximum and minimum values ​​of the x-coordinate and the maximum and minimum values ​​of the y-coordinate of the risk convex point, that is:

[0051] Xmin=minimum(x1,x2,x3,x4,...,xn);

[0052] Xmax=maximum(x1,x2,x3,x4,...,xn);

[0053] Ymin=minimum(y1,y2,y3,y4,...,yn);

[0054] Ymax=maximum(y1,y2,y3,y4,...,yn);

[0055] Where minimum and maximum are functions for finding the minimum and maximum values, respectively;

[0056] The risk area can be defined as the following constraint box:

[0057] Bounding box={Xmin,Ymin,Xmax,Ymax};

[0058] Expand the x and y coordinates of the constraint box outwards to obtain a coordinate filtering window:

[0059] C-Filter Box =

[0060] {Xmin-offset,Ymin-offset,Xmax+offset,Ymax+offset}.

[0061] Where offset is the outward offset of the horizontal and vertical coordinates of the constraint box. Preferably, the failure data filtering module is further configured as follows:

[0062] Extract the coordinates of the center points of the original set of failure paths to form a set of failure path center coordinate data.

[0063] The coordinate filtering window is used to filter the set of center coordinates of the failure path, and only failure data points whose coordinates are located within the coordinate filtering window are retained.

[0064] As can be seen, the failure analysis method and apparatus based on chip pin testing provided by this invention uses chip pin test data to define and evaluate risk areas, and further feeds the risk area information obtained from chip testing back to the EFA analysis tool, thereby narrowing the scope of failure data analysis and verification, accelerating the analysis speed, and improving the test accuracy. Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 The flowchart illustrates a process for performing hotspot analysis and physical slicing analysis on a failed chip using physical failure methods based on existing technologies.

[0067] Figure 2 A flowchart of the failure analysis method based on chip pin testing described in this invention is shown.

[0068] Figure 3 A flowchart of the failure chip analysis described in this invention is shown.

[0069] Figure 4 A schematic diagram of the failure bump count table generated from pin test data according to the present invention is shown.

[0070] Figure 5 A schematic diagram illustrating the determination of risk areas based on the location of failure protrusions according to the present invention is shown.

[0071] Figure 6 This diagram illustrates the calculation of the risk area range based on a risk bump list according to the present invention.

[0072] Figure 7 A block diagram of the failure analysis device based on chip pin testing according to the present invention is shown. Detailed Implementation

[0073] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0074] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. To more clearly illustrate the present invention, numerous technical details are described in the following specific embodiments. Those skilled in the art should understand that the present invention can be implemented even without some of these details. Furthermore, to highlight the inventive spirit of the present invention, some methods, means, components, and applications well-known to those skilled in the art are not described in detail; however, this does not affect the implementation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0075] Given the difficulty, high cost, and insufficient data accuracy of traditional solutions for failure analysis and processing such as cracks and fragments, this invention combines pin testing with pin test data from the wafer testing phase to perform extensive statistical analysis of bumps across the entire chip, locate the physical coordinates of failed bumps, identify areas prone to failure, and determine high-risk areas. Then, it combines EFA analysis tools such as SCAN to optimize the failure path database and perform preliminary data screening to improve the accuracy of failure analysis, increase PFA success rate, and reduce analysis costs.

[0076] Example 1

[0077] One aspect of this invention provides a failure analysis method based on chip pin testing. See also... Figure 2 The flowchart shown includes the following steps:

[0078] Step S101: Obtain chip pin test data during the wafer testing phase, and determine the number of failures of each bump in the chip from the pin test data.

[0079] Figure 3 A flowchart illustrating the improved failure chip analysis process of this invention is shown. Figure 3 As shown, firstly, a statistical analysis of failed bumps is performed on the wafer pin open (WS PIN Opens) test items to obtain the electrical test data of the bumps. After obtaining the electrical test data, the chip data at these specific locations is compiled into a dataset to form its test data results. This includes statistically organizing the test data of these failed chips, obtaining relevant data results on the number of failed bumps by observing the failed bumps in DC pin-related tests, and evaluating potentially high-risk, easily failed bumps in subsequent steps. Based on this, a list of severely and significantly failed bumps is formed. A bump with a high number of failures can be defined as a bump that has failed a large number of times in a large number of chip tests. Figure 4 This diagram illustrates a table of failed bump counts generated from pin test data. The horizontal axis represents the name of each bump, and the vertical axis represents the number of failures for that corresponding bump.

[0080] Step S102: Select risk bumps from the bumps in the chip according to the number of failures, and count the coordinate positions of the risk bumps. Determine the risk area of ​​the chip according to the coordinate positions.

[0081] In a specific embodiment of the present invention, after determining the number of failures for each bump, severely failed bumps are obtained through chip-level physical mapping, forming a risk bump list. Chip-level layout location confirmation is then performed to determine the risk area. For example, a set of bumps with the highest number of failures (by a preset percentage) can be obtained as risk bumps, representing a set of bumps with relatively severe failures. In a preferred embodiment, bumps can be sorted in descending order of failure count, and the top 30% of bumps can be selected as risk bumps. Bumps within this range are then added to the risk bump list.

[0082] After obtaining the above list of risk bumps, coordinate queries and markings are performed according to the positions of all risk bumps in the chip layout to obtain the set of center coordinates of all risk bumps. Figure 5 An example of determining the risk area based on the location of the failure bump is shown.

[0083] In one embodiment, assuming a set of coordinates for n risk convex points is obtained, the X-coordinate set and the Y-coordinate set can be statistically analyzed separately. The format is as follows:

[0084] X_list = {x1,x2,x3,...,xn};

[0085] Y_list = {y1, y2, y3, ..., yn}.

[0086] Where xn and yn represent the x-coordinate and y-coordinate of the nth risk convex point, respectively, and so on.

[0087] This set provides the maximum and minimum values ​​of the x-coordinate and y-coordinate of the risk convex point, i.e., four coordinate parameters:

[0088] Xmin=minimum(x1,x2,x3,x4,...,xn);

[0089] Xmax=maximum(x1,x2,x3,x4,...,xn);

[0090] Ymin=minimum(y1,y2,y3,y4,...,yn);

[0091] Ymax=maximum(y1,y2,y3,y4,...,yn);

[0092] Where minimum and maximum are functions for finding the minimum and maximum values, respectively.

[0093] Therefore, the initial risk area can be defined as a constraint box:

[0094] Boundingbox={Xmin,Ymin,Xmax,Ymax}

[0095] See Figure 6 The diagram illustrates the calculation of the risk region based on the risk bump list. In a further embodiment, considering the influence of the bump size and layout, the constraint box can be further expanded outwards in both length and width directions to increase the area of ​​the risk region. The offset of the expansion of the constraint box's horizontal and vertical coordinates can be defined as offset, ultimately obtaining the complete coordinate filtering window C-Filter, represented as:

[0096] C-FilterBox =

[0097] {Xmin-offset,Ymin-offset,Xmax+offset,Ymax+offset}.

[0098] In a specific embodiment, according to the definition of checkwindow size in the Design for Manufacturing (DFM) provided by the wafer manufacturer, the value of the offset can be between 50μm and 100μm.

[0099] Steps S101 and S102 described above can be used as preprocessing steps, corresponding to Figure 3 The process ①.

[0100] Step S103: Import the failure log of the failed chip, parse the failure log to obtain the original failure path set, and filter out the failure data points corresponding to the risk area from the original failure path set.

[0101] Specifically, the existing SCAN EFA diagnostic tool is first used to collect the machine failure log data of these failed chips, and then this data is imported into the existing test software tool.

[0102] To reduce database noise and improve analysis accuracy, these failure logs need to be filtered. The machine failure log data for failed chips can physically be represented as a set of physical failure paths (such as Netpath 1, Netpath 2, etc.). We can first extract the coordinates of the center points of these failure paths to form a Netpath Coordinate List of failure path center coordinates.

[0103] Then, the set of center coordinate data of the original failure path is filtered. The filtering condition is the coordinate filtering window C-Filter based on pin testing obtained in step S102. Only data points whose coordinates are within the constraint box of C-Filter are retained, thereby achieving the initial screening of failure data.

[0104] The above step S103 corresponds to Figure 3 The process ②.

[0105] Step S104: Use the EFA analysis tool to perform failure analysis and verification on the failure data points.

[0106] Next, the selected failure data points are input into the EFA analysis tool and the software execution process is initiated to obtain a more accurate PFA risk point path. After obtaining the above PFA risk point path, PFA hotspot, slice, and physical analyses corresponding to each failure data point are performed to verify and confirm the final failure analysis results.

[0107] As an example, the following is a portion of the pseudocode for risk point area delineation in the EFA SCAN tool:

[0108] #scan_xy is the coordinate of the center point of the SCAN path.

[0109] center_x = int(scan_xy[0])

[0110] center_y = int(scan_xy[1])

[0111] ifcenter_y>90000:

[0112] y_flag = 1

[0113] if 14600 > bit_center_ x > 0:

[0114]

[0115] elif 87400>center_x>41600:

[0116]

[0117] elif 133600>center_x>87400:

[0118]

[0119] else:

[0120] x_flag = 3

[0121] else:

[0122] y_flag=0

[0123] if 41600 > center_x > 0:

[0124]

[0125] elif 87400>center_x>41600

[0126]

[0127] elif 133600>center_x>87400

[0128]

[0129] else:

[0130] x_flag = 3

[0131] block_definition=str(x_flag)+":"+str(y_flag).

[0132] Those skilled in the art will understand that this document uses SCAN as an example for description. In addition to SCAN, other failure analysis tools such as bitmaps may also be used in EFA failure analysis.

[0133] Example 2

[0134] See Figure 7 Another aspect of the present invention includes a functional module architecture that is completely consistent with the aforementioned failure analysis method based on chip pin testing. That is, the embodiments of the present invention also provide a failure analysis apparatus based on chip pin testing, comprising:

[0135] The test data acquisition module 201 is used to acquire chip pin test data during the wafer testing stage and determine the number of failures of each bump in the chip from the pin test data;

[0136] The risk area determination module 202 is used to select risk bumps from the bumps in the chip according to the number of failures, count the coordinate positions of the risk bumps, and determine the risk area of ​​the chip according to the coordinate positions.

[0137] The failure data filtering module 203 is used to import the failure logs of the failed chip, parse the failure logs to obtain the original failure path set, and filter out the failure data points corresponding to the risk area from the original failure path set.

[0138] The failure analysis module 204 is used to perform failure analysis and verification on the failure data points using EFA analysis tools.

[0139] The apparatus in this regard can be implemented using the failure analysis method based on chip pin testing provided in Embodiment 1 above. The specific functions implemented by each module can be found in the description in Embodiment 1, and will not be repeated here.

[0140] As can be seen, compared with the prior art, the failure analysis method and apparatus based on chip pin testing provided by the present invention uses chip pin test data to define and evaluate risk areas, and further feeds the risk area information obtained from chip testing back to the EFA analysis tool, thereby narrowing the scope of failure data analysis and verification, accelerating the analysis speed, and improving the test accuracy.

[0141] Those skilled in the art will understand that the implementation details of each step or module of the failure analysis method and apparatus based on chip pin testing described above do not constitute a limitation on the overall solution of the present invention. Those skilled in the art can make readily conceivable adjustments to the sequence, parameters, or formulas involved in the above method and apparatus based on the actual size of the chip or its failure state.

[0142] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0143] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A failure analysis method based on chip pin testing, characterized in that, include: Obtain chip pin test data during the wafer testing phase, and determine the number of failures for each bump in the chip from the pin test data; Based on the number of failures, risky bumps are selected from the bumps in the chip, and the coordinate positions of the risky bumps are counted. The risk area of ​​the chip is determined based on the coordinate positions. Import the failure logs of the failed chip, parse the failure logs to obtain the original failure path set, and filter out the failure data points corresponding to the risk area from the original failure path set; Failure analysis and verification of the aforementioned failure data points were performed using electrical failure analysis tools; The step of selecting risky bumps from the bumps in the chip based on the number of failures, and calculating the coordinate positions of the risky bumps, further includes: By using chip-level physical mapping, the set of bumps with the highest number of failures among the failed bumps is obtained as a risk bump and added to the risk bump list. Based on the position of all risk bumps in the chip layout, coordinate query and marking are performed to obtain the center coordinate set of all risk bumps, and a coordinate filtering window is obtained through the coordinate set; The step of filtering the failure data points corresponding to the risk area from the original failure path set further includes: Extract the coordinates of the center points of the original set of failure paths to form a set of failure path center coordinate data. The coordinate filtering window is used to filter the set of center coordinates of the failure path, and only failure data points whose coordinates are located within the coordinate filtering window are retained.

2. The failure analysis method based on chip pin testing according to claim 1, characterized in that, Determining the number of failures for each bump in the chip from the pin test data further includes: Statistical analysis of failed bumps is performed on wafer pin testing items to obtain electrical test data of the bumps. By observing failed bumps in DC pin-related tests, the number of failures for each bump is obtained.

3. The failure analysis method based on chip pin testing according to claim 2, characterized in that, The step of determining the risk area of ​​the chip based on the coordinate position further includes: For the coordinate set of n risk convex points, perform separate statistics on the X-coordinate set and the Y-coordinate set: X_list={x1, x2, x3, ... , xn}; Y_list={y1, y2, y3, ... , yn}; Where xn and yn represent the x-coordinate and y-coordinate of the nth risk convex point, respectively; Obtain the maximum and minimum values ​​of the x-coordinate and the maximum and minimum values ​​of the y-coordinate of the risk convex point, that is: Xmin=minimum (x1, x2, x3, x4, ... ,xn); Xmax=maximum (x1, x2, x3, x4, ... ,xn); Ymin=minimum (y1, y2, y3, y4, ... ,yn); Ymax=maximum (y1, y2, y3, y4, ... ,yn); Where minimum and maximum are functions for finding the minimum and maximum values, respectively; The risk area is defined by the following constraint box: Bounding box={Xmin, Ymin, Xmax, Ymax}; Expand the x and y coordinates of the constraint box outwards to obtain a coordinate filtering window: C-Filter Box={Xmin-offset, Ymin-offset, Xmax+offset, Ymax+offset}; Where offset is the outward offset of the horizontal and vertical coordinates of the constraint box.

4. A failure analysis device based on chip pin testing, characterized in that, include: The test data acquisition module is used to acquire chip pin test data during the wafer testing stage, and determine the number of failures of each bump in the chip from the pin test data; The risk area determination module is used to select risk bumps from the bumps in the chip according to the number of failures, count the coordinate positions of the risk bumps, and determine the risk area of ​​the chip according to the coordinate positions. The failure data filtering module is used to import the failure logs of the failed chip, parse the failure logs to obtain the original failure path set, and filter out the failure data points corresponding to the risk area from the original failure path set. The failure analysis module is used to perform failure analysis and verification on the failure data points using electrical failure analysis tools; The risk area determination module is further configured as follows: By using chip-level physical mapping, the set of bumps with the highest number of failures among the failed bumps is obtained as a risk bump and added to the risk bump list. Based on the position of all risk bumps in the chip layout, coordinate query and marking are performed to obtain the center coordinate set of all risk bumps, and a coordinate filtering window is obtained through the coordinate set; The failure data filtering module is further configured as follows: Extract the coordinates of the center points of the original set of failure paths to form a set of failure path center coordinate data. The coordinate filtering window is used to filter the set of center coordinates of the failure path, and only failure data points whose coordinates are located within the coordinate filtering window are retained.

5. The failure analysis device based on chip pin testing according to claim 4, characterized in that, The test data acquisition module is further configured as follows: Statistical analysis of failed bumps is performed on wafer pin testing items to obtain electrical test data of the bumps. By observing failed bumps in DC pin-related tests, the number of failures for each bump is obtained.

6. The failure analysis device based on chip pin testing according to claim 5, characterized in that, The risk area determination module is further configured as follows: For the coordinate set of n risk convex points, perform separate statistics on the X-coordinate set and the Y-coordinate set: X_list={x1, x2, x3, ... , xn}; Y_list={y1, y2, y3, ... , yn}; Where xn and yn represent the x-coordinate and y-coordinate of the nth risk convex point, respectively; Obtain the maximum and minimum values ​​of the x-coordinate and the maximum and minimum values ​​of the y-coordinate of the risk convex point, that is: Xmin=minimum (x1, x2, x3, x4, ... ,xn); Xmax=maximum (x1, x2, x3, x4, ... ,xn); Ymin=minimum (y1, y2, y3, y4, ... ,yn); Ymax=maximum (y1, y2, y3, y4, ... ,yn); Where minimum and maximum are functions for finding the minimum and maximum values, respectively; The risk area is defined by the following constraint box: Bounding box={Xmin, Ymin, Xmax, Ymax}; Expand the x and y coordinates of the constraint box outwards to obtain a coordinate filtering window: C-Filter Box={Xmin-offset, Ymin-offset, Xmax+offset, Ymax+offset}; Where offset is the outward offset of the horizontal and vertical coordinates of the constraint box.

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