Circuit implementing physically unclonable function and operating method thereof, electronic device

Abstract

A circuit for implementing a physically unclonable function, an operating method thereof, and an electronic device. The circuit includes a random number generation circuit, an address encoding circuit, a fingerprint data generation circuit, and an iteration control circuit. The fingerprint data generation circuit includes a first memristor array, the random number generation circuit includes a second memristor array and a third memristor array, and the address encoding circuit includes a first address encoding unit and a second address encoding unit. The random number generation circuit generates an intermediate random number through the second memristor array and the third memristor array. The iteration control circuit provides the intermediate random number to the second address encoding unit or provides the intermediate random number to the first address encoding unit. The first address encoding unit encodes the intermediate random number to obtain first address information. The fingerprint data generation circuit selects a plurality of first memristors from the first memristor array according to the first address information to generate fingerprint data. The circuit has a small area and low cost, and overcomes the data correlation problem.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a circuit for implementing a physically unclonable function (PUF), a method of operating the same, an integrated circuit chip, and an electronic device. Background Technology

[0002] With the rapid development of information technology, the application of hardware such as smart cards and radio frequency identification (RFID) is becoming increasingly widespread, and hardware security faces multifaceted threats. Hardware security is crucial for hardware circuits, chips, and IoT devices.

[0003] Hardware security circuits typically include authentication circuits, encryption circuits, true random number generator circuits, and fingerprint circuits. The fingerprint circuit generates the fingerprint data necessary for authentication and encryption, ensuring that each chip's fingerprint is unique. This is a key security technology for preventing circuit cloning, chip counterfeiting, and secure communication. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a circuit for implementing a physically unclonable function. The circuit includes a random number generation circuit, an address encoding circuit, a fingerprint data generation circuit, and an iteration control circuit. The fingerprint data generation circuit includes a first memristor array, the random number generation circuit includes a second memristor array and a third memristor array, and the address encoding circuit includes a first address encoding unit connected to the first memristor array and a second address encoding unit connected to the random number generation circuit. The random number generation circuit is configured to generate intermediate random numbers using the second memristor array and the third memristor array based on intermediate address information obtained by encoding input data using the second address encoding unit. The iteration control circuit is configured to provide the intermediate random numbers as input data to the second address encoding unit in response to satisfying an iteration condition, and to provide the intermediate random numbers to the first address encoding unit in response to not satisfying the iteration condition. The first address encoding unit is configured to encode the intermediate random numbers received from the iteration control circuit to obtain first address information. The fingerprint data generation circuit is configured to select multiple first memristors from the first memristor array based on the first address information to generate fingerprint data.

[0005] For example, in the circuit provided in at least one embodiment of this disclosure, the second address encoding unit includes a second address encoding subunit connected to the second memristor array and a third address encoding subunit connected to the third memristor array. The second address encoding subunit encodes the input data input in the positive direction to obtain second address information, and the third address encoding subunit encodes the input data input in the negative direction to obtain third address information. The intermediate address information includes the second address information and the third address information.

[0006] For example, in the circuit provided in at least one embodiment of this disclosure, the intermediate random number includes a first intermediate result generated by the second memristor array based on the second address information and a second intermediate result generated by the third memristor array based on the third address information.

[0007] For example, in the circuit provided in at least one embodiment of this disclosure, the random number generation circuit further includes a fourth memristor array, and the second address encoding unit further includes a fourth address encoding subunit connected to the fourth memristor array. The fourth address encoding subunit encodes the input data input in a forward or reverse direction to obtain fourth address information, and the intermediate address information includes the second address information, the third address information, and the fourth address information.

[0008] For example, in the circuit provided in at least one embodiment of this disclosure, the intermediate random number includes a first intermediate result generated by the second memristor array based on the second address information, a second intermediate result generated by the third memristor array based on the third address information, and a third intermediate result generated by the fourth memristor array based on the fourth address information.

[0009] For example, in the circuit provided in at least one embodiment of this disclosure, a plurality of memristors in the first memristor array, the second memristor array, or the third memristor array store a plurality of randomly distributed data.

[0010] For example, in the circuit provided in at least one embodiment of this disclosure, the intermediate address information includes an intermediate start address bit, an input data address bit, and an intermediate addressing rule, wherein the first address information includes a first start address bit, a random number data address bit, and a first addressing rule.

[0011] For example, in the circuit provided in at least one embodiment of this disclosure, the intermediate address information or the first address information further includes a region slice select bit, which is used to select a target region from the partitions of the first memristor array, the second memristor array, or the third memristor array.

[0012] For example, in the circuit provided in at least one embodiment of this disclosure, the intermediate addressing rule may be the same as or different from the first addressing rule.

[0013] For example, in the circuit provided in at least one embodiment of this disclosure, the fingerprint data generation circuit is further configured to read multiple resistance values ​​of the plurality of first memristors and output multiple data corresponding to the plurality of resistance values ​​as the fingerprint data.

[0014] For example, in at least one embodiment of the circuit provided in this disclosure, the address encoding circuit includes an XOR tree circuit.

[0015] At least one embodiment of this disclosure also provides an operation method for a circuit that implements a physically unclonable function. The circuit that implements the physically unclonable function includes a random number generation circuit, an address encoding circuit, a fingerprint data generation circuit, and an iterative control circuit. The fingerprint data generation circuit includes a first memristor array, the random number generation circuit includes a second memristor array and a third memristor array, and the address encoding circuit includes a first address encoding unit connected to the first memristor array and a second address encoding unit connected to the random number generation circuit.

[0016] The operation method includes: generating intermediate random numbers using the second memristor array and the third memristor array of the random number generation circuit, based on intermediate address information obtained by encoding input data using the second address encoding unit; providing the intermediate random numbers as input data to the second address encoding unit via the iteration control circuit in response to satisfying the iteration condition; providing the intermediate random numbers to the first address encoding unit via the iteration control circuit in response to not satisfying the iteration condition; encoding the intermediate random numbers received from the iteration control circuit using the first address encoding unit to obtain first address information; and generating fingerprint data by selecting multiple first memristors from the first memristor array using the fingerprint data generation circuit based on the first address information.

[0017] For example, in the operation method provided in at least one embodiment of this disclosure, the step of selecting a plurality of first memristors from the first memristor array to generate fingerprint data by the fingerprint data generation circuit according to the first address information includes: reading a first starting address bit, a random number data address bit, and a first addressing rule in the first address information; determining a starting memristor in the first memristor array according to the first starting address bit; selecting the plurality of first memristors starting from the starting memristor according to the random number data address bit and the first addressing rule; and outputting the plurality of data stored in the plurality of first memristors as the fingerprint data.

[0018] At least one embodiment of this disclosure also provides an integrated circuit chip, including the circuit that implements a physically unclonable function as described in any embodiment of this disclosure.

[0019] At least one embodiment of this disclosure also provides an electronic device, including the integrated circuit chip described in any embodiment of this disclosure. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0021] Figure 1 This is a schematic diagram of a circuit that implements a physically unclonable function based on an arbitrator;

[0022] Figure 2 This is a schematic diagram of a circuit that implements a physically unclonable function based on a memristor array;

[0023] Figure 3 A schematic diagram of the circuit structure for implementing a physically unclonable function provided in at least one embodiment of this disclosure;

[0024] Figure 4 This is a schematic diagram of an exemplary memristor array;

[0025] Figure 5 This is a schematic diagram of an XOR tree circuit.

[0026] Figure 6 A schematic diagram of an exemplary address encoding circuit provided in at least one embodiment of this disclosure;

[0027] Figure 7 A schematic diagram of the structure of an exemplary circuit for implementing a physically unclonable function, provided for at least one embodiment of this disclosure;

[0028] Figure 8 A schematic diagram of the structure of another exemplary circuit for implementing a physically unclonable function, provided for at least one embodiment of this disclosure;

[0029] Figure 9 A flowchart illustrating an operation method provided in at least one embodiment of this disclosure;

[0030] Figure 10 A schematic diagram illustrating the fingerprint data generation process provided in at least one embodiment of this disclosure;

[0031] Figure 11 A probability distribution map of fingerprint data generated by a circuit implementing a physically unclonable function, provided in at least one embodiment of this disclosure; and

[0032] Figure 12 Hamming distance distribution map of fingerprint data generated by a circuit implementing a physically unclonable function, provided in at least one embodiment of this disclosure. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0035] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, that component is represented by the same or similar reference numerals in each drawing.

[0036] One approach to fingerprint circuitry involves generating fingerprint data externally to the chip and then writing it into the chip's on-chip non-volatile memory. However, this method generates a limited number of fingerprint sets, resulting in high chip testing costs and security vulnerabilities during data writing. Another approach utilizes an on-chip implementation of a physically unclonable function (PUF) to spontaneously generate fingerprint data during chip manufacturing. For example, it generates N sets of fingerprint data (N greater than or equal to 2, e.g., greater than 10), and randomly selects one set for each encryption or authentication operation. PUFs are considered a viable hardware security solution due to their advantages such as randomness, reproducibility, and compatibility with micro / nano fabrication processes.

[0037] Circuits implementing physically unclonable functions (PUFs) can be categorized into weak PUF circuits and strong PUF circuits. Both offer strong security and relatively low chip costs. Strong PUF circuits generate more fingerprint data than weak PUF circuits, thus providing higher security. This is because authentication and encryption are frequently performed when using chips or IoT devices. Repeated use of the same fingerprint data reduces its security; therefore, the more fingerprint data a fingerprint circuit can generate, the fewer times the same fingerprint data is used, resulting in stronger overall chip security. Therefore, designing strong PUF circuits that meet hardware security requirements has become a current research hotspot.

[0038] Physically unclonable functions can be implemented using CMOS-based arbiter circuits. Figure 1 A schematic diagram of a circuit for implementing physically unclonable functions based on an arbitrator is shown. Figure 1 As shown in (a), the CMOS arbiter circuit includes a delay path consisting of K (e.g., K = 64) cascaded switching circuits and an arbiter circuit located at the end of the delay path. Figure 1 As shown in (b), each switching circuit has two input signals, two output signals, and one control signal. The control signal controls the data path within the switching circuit, thus causing the input signals to propagate along different paths within the circuit. For example, when the control signal bi is 0, the input signals pass through the switching circuit in parallel; when bi is 1, the input signals pass through the switching circuit in a crisscross pattern. For instance, two step signals In1 and In2 are input to the first-stage switching circuit of a CMOS arbiter circuit. K control signals b1, b2…bk are input to the K switching circuits respectively. The K control signals control the propagation paths of the two step signals In1 and In2 within the K switching circuits. After a period of time, the two step signals In1 and In2 reach the outputs YK1 and YK2 of the Kth-stage switching circuit, respectively. Figure 1 As shown in (c) and (d), due to different propagation paths, the delay times for the input signals to propagate to YK1 and YK2 are also different. The arbitrator circuit outputs 1 or 0 based on the order in which the input signals arrive. For example, the output of a CMOS arbitrator circuit is determined by K control signals and has 2 K With two inputs and their corresponding outputs, theoretically, the number of fingerprint data sets that can be generated by a CMOS arbiter circuit is 2. K .

[0039] However, CMOS arbiter circuits have two problems. First, there's the issue of randomness; the circuit cannot guarantee the output's 2... K First, the fingerprint data sets are independent of each other, making them easy to crack by neural network algorithms and unable to resist attacks from neural network algorithms. Second, there is the issue of stability. The delays of the two propagation paths may be very close, so even with the same control signal configuration, the output of the CMOS arbitrator circuit may err due to environmental factors such as thermal noise.

[0040] For example, physically non-clonable functions can also be implemented using two memristor arrays. Figure 2 This is a schematic diagram of a circuit that implements physically non-clonable functions based on a memristor array. For example, firstly using... Figure 2 The memristor array on the left implements a weak PUF (Power-On-Flight) and then uses the output of the weak PUF as the address input. Figure 2 In the memristor array on the right, for example, by setting or resetting the memristor devices in the left memristor array to change their resistance values, the resistance values ​​of the memristor devices are mapped to the row and column addresses of the right memristor array. Finally, the right memristor array stores the randomly generated data and outputs the final fingerprint data. Although this method overcomes the stability problem, it has a data correlation problem, that is, when only one bit of the input address data changes, only one bit of the output fingerprint data also changes.

[0041] However, in order to increase the complexity of the data and enhance the security of hardware authentication, it is desirable that when the input data changes, for example, when only one bit of the input data changes, the output fingerprint data should change significantly, such as when about half of the output fingerprint data changes.

[0042] One solution is to first implement a weak fingerprint fingerprint (PUF) using a memristor array, and then input the output data of the weak PUF into a hash circuit (e.g., a hash circuit based on the SHA256 algorithm). The hash circuit then outputs the final fingerprint data, thus achieving a strong PUF. While this solution overcomes the randomness and stability problems using the memristor array and the data correlation problem using the hash circuit, the hash circuit leads to serious area and cost issues.

[0043] This disclosure provides at least one embodiment of a circuit for implementing a Physically Unclonable Function (PUF) and its operation method, an integrated circuit chip, and an electronic device. The circuit structure for implementing the PUF is simple, lightweight, and low-cost. It can generate a large amount of fingerprint data, achieving a strong PUF. Utilizing the strong intrinsic randomness and data retention capabilities of memristor arrays, it overcomes data randomness and stability problems. The correlation between multiple memristor arrays and iterative control circuits solves the data correlation problem, enabling the output fingerprint data to change significantly with small changes in the input data, effectively increasing data complexity and improving hardware security.

[0044] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0045] Some embodiments of this disclosure provide a circuit for implementing physically unclonable functions. Figure 3 This is a schematic diagram of the circuit structure for implementing a physically unclonable function, provided in at least one embodiment of this disclosure. Figure 3 As shown, the circuit 10 that implements PUF includes a random number generation circuit 100, an address encoding circuit 200, an iteration control circuit 300, and a fingerprint data generation circuit 400.

[0046] For example, the fingerprint data generation circuit 400 includes a first memristor array 401, and the random number generation circuit 100 includes a second memristor array 101 and a third memristor array 102.

[0047] The following is combined Figure 4 The structure of a memristor array is described, but this description is exemplary and not limiting.

[0048] For example, Figure 4 This is a schematic diagram of an exemplary memristor array. Figure 4 As shown, the memristor array includes memristor cells arranged in an array of M rows and N columns, M word lines (WL1 to WLM), M source lines (SL1 to SLM), and N bit lines (BL1 to BLN). M and N are both integers greater than or equal to 1, for example, both M and N are integers greater than or equal to 10, or both are integers greater than or equal to 100. The embodiments of this disclosure are not limited in this respect.

[0049] For example, each memristor cell may include a switching element (e.g., a transistor T) and a memristor R. Figure 4A memristor cell with a 1T1R structure (one transistor T and one memristor R) is shown, but embodiments of this disclosure are not limited thereto. For example, the structure of the memristor cell in a memristor array can be 1T1R, 2T2R (two transistors T and two memristors R), or other possible structures (e.g., including but not limited to 2T1R (two transistors T and one memristor R)).

[0050] For example, WL1, WL2...WLM represent the word lines of the first, second...Mth rows, respectively. The control electrode (e.g., the gate of transistor T) of the switching element in each row's memristor cell is connected to the corresponding word line of that row. BL1, BL2...BLN represent the bit lines of the first, second...Nth columns, respectively. The memristor R in each column's memristor cell is connected to the corresponding bit line of that column. SL1, SL2...SLM represent the source lines of the first, second...Mth rows, respectively. The source of transistor T in each row's memristor cell is connected to the corresponding source line of that row. For example, in this case, the word lines and source lines are parallel.

[0051] For example, the memristor array can adopt a structure in which word lines and source lines are parallel, or it can adopt other arrangement structures, such as a structure in which bit lines and source lines are parallel. The embodiments of this disclosure do not limit the arrangement of the memristor array.

[0052] It should be noted that the transistors used in some embodiments of this disclosure can be thin-film transistors (TFTs), field-effect transistors (e.g., MOS TFTs), or other switching devices with the same characteristics. Thin-film transistors can include oxide TFTs, amorphous silicon TFTs, or polycrystalline silicon TFTs, etc. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, in order to distinguish the two poles of the transistor other than the gate (source and drain), one of the poles is directly described as the first pole, and the other as the second pole.

[0053] For example, transistor T can be an N-type transistor, with its gate connected to the word line. For example, transistor T conducts when the word line input is high. The first terminal of transistor T can be the source and configured to be connected to the source line, so that transistor T can receive a reset voltage through the source line. The second terminal of transistor T can be the drain and configured to be connected to the second terminal (e.g., the negative terminal) of memristor R. The first terminal (e.g., the positive terminal) of memristor R is connected to the bit line, so that memristor R can receive a set voltage through the bit line. Alternatively, transistor T can be a P-type transistor, with its gate connected to the word line. For example, transistor T conducts when the word line input is low. The first terminal of transistor T can be the drain and configured to be connected to the source line, so that transistor T can receive a reset voltage through the source line. The second terminal of transistor T can be the source and configured to be connected to the second terminal (e.g., the negative terminal) of memristor R. The first terminal (e.g., the positive terminal) of memristor R is connected to the bit line, so that memristor R can receive a set voltage through the bit line.

[0054] It should be noted that, in addition to the exemplary structure described above, the structure of the memristor unit can also be implemented in other ways, such as a structure in which the second terminal of the memristor R is connected to the source line terminal. The embodiments disclosed herein do not limit this.

[0055] For example, the word line terminal applies a corresponding voltage to the gate of transistor T, thereby controlling transistor T to turn on or off. When operating memristor R, such as performing a set or reset operation, transistor T must first be turned on; that is, a turn-on voltage must be applied to the gate of transistor T through the word line terminal. After transistor T is turned on, for example, voltages can be applied to memristor R through the source line and bit line terminals to change the resistance state of memristor R. For example, a set voltage can be applied to the bit line terminal to put memristor R in a low-resistance state; or a reset voltage can be applied to the source line terminal to put memristor R in a high-resistance state. For example, the resistance value in the high-resistance state is more than 100 times, or even more than 1000 times, the resistance value in the low-resistance state.

[0056] For example, in at least one embodiment of this disclosure, by simultaneously applying voltage to the word line and bit line, the resistance value of the memristor R can be made smaller and smaller, that is, the memristor R changes from a high resistance state to a low resistance state. The operation of changing the memristor R from a high resistance state to a low resistance state is called a set operation. By simultaneously applying voltage to the word line and source line, the resistance value of the memristor R can be made larger and larger, that is, the memristor R changes from a low resistance state to a high resistance state. The operation of changing the memristor R from a low resistance state to a high resistance state is called a reset operation. For example, the memristor R has a threshold voltage. Inputting a voltage greater than the threshold voltage can change the resistance value (or conductance value) of the memristor R, while inputting a voltage less than the threshold voltage does not change the resistance value (or conductance value) of the memristor R.

[0057] For example, in at least one embodiment of this disclosure, after a set or reset operation is performed on the memristor, the resistance (or conductance) value of the memristor remains unchanged, thus the memristor can be used to store data. For example, in one example of this disclosure, the low resistance state of the memristor corresponds to storing data 1, that is, a set operation on the memristor can make the corresponding data value of the memristor 1, and the high resistance state of the memristor corresponds to storing data 0, that is, a reset operation on the memristor can make the corresponding data value of the memristor 0. For example, by applying a read voltage (e.g., less than a threshold voltage) to the memristor, the resistance (or conductance) value of the memristor can be read, thereby obtaining the data stored in the memristor.

[0058] For example, in at least one embodiment of this disclosure, a preset reference resistance value can be used to distinguish between the low-resistance state and the high-resistance state of the memristor. For instance, if the preset reference resistance value is 100kΩ, then the binary data value corresponding to a memristor with a resistance value less than 100kΩ is 1, and the binary data value corresponding to a memristor with a resistance value greater than 100kΩ is 0. The preset reference resistance value can be set according to the actual characteristics of the memristor. For example, the reference resistance value can be the median of the resistance values ​​of all memristors, or it can be the middle value of a preset resistance range. The embodiments of this disclosure do not limit this.

[0059] It should be noted that memristors with different structures and characteristics can store different types of data, such as binary data, quaternary data, or decimal data. The embodiments of this disclosure do not impose any limitations on this. The array structure, array size, structure and type of memristor cells, and material composition of the first memristor array 401, the second memristor array 101, and the third memristor array 102 can be the same or different. The embodiments of this disclosure do not impose any limitations on this. For example, in one example, the array structures of the first memristor array 401, the second memristor array 101, and the third memristor array 102 are all the same. For example, in another example, the array structures of the second memristor array 101 and the third memristor array 102 are the same, but their array structures differ from those of the first memristor array 401.

[0060] For example, in at least one embodiment of this disclosure, during operation, multiple memristors in the first memristor array 401, the second memristor array 101, or the third memristor array 102 store multiple randomly distributed data. That is, the resistance values ​​(or conductance values) of the multiple memristors in the first memristor array 401, the second memristor array 101, or the third memristor array 102 are randomly distributed.

[0061] For example, in one example, the intrinsic randomness of the memristor array can be used to make multiple memristors in the memristor array randomly store data (e.g., binary data 0 or 1). For example, after the memristor array is fabricated, the resistance values ​​(or conductance values) of multiple memristors are usually randomly distributed. The memristor array can be used directly in the PUF circuit without any operation, thereby saving the early debugging cost.

[0062] For example, in another example, the resistance (or conductance) values ​​of multiple memristors in a memristor array can be randomly distributed through set or reset operations. For instance, after multiple authentications and encryptions, a memristor in the same location may be used multiple times. By changing the resistance value of the memristor through set and reset operations, the memristor array can store updated randomly distributed data, which can further increase data complexity, improve hardware security, and reduce the possibility of being cracked by neural network algorithms.

[0063] For example, such as Figure 3 As shown, the address encoding circuit 200 is configured to encode input data to generate address information. For example, this address information is provided to the memristor array of the random number generation circuit 100 or the fingerprint data generation circuit 400 to select a target memristor from the memristor array, thereby obtaining the data stored in the target memristor.

[0064] For example, in at least one example of the embodiments of this disclosure, an exemplary address encoding circuit includes an XOR tree circuit.

[0065] Figure 5 This is a schematic diagram of an XOR tree circuit. Figure 6 This is a schematic diagram of an exemplary address encoding circuit provided for at least one embodiment of the present disclosure. For example, in the figure, black circles represent XOR tree circuits, and cross circles represent XOR gates.

[0066] For example, such as Figure 5 As shown, the XOR tree circuit includes multiple XOR gates. For example, the length of the input data X to the multiple XOR gates is 2. l The input data is XORed pairwise. The result of multiple XOR gates in the first group (e.g., the first row in the figure) is used as the input data for multiple XOR gates in the second group (e.g., the second row in the figure), and so on. The final output data Y has a length of 1 bit.

[0067] For example, such as Figure 6As shown, the address encoding circuit includes multiple XOR tree circuits and multiple XOR gate circuits. The address encoding circuit encodes the input data C using these circuits to generate address information, including the address of the target memristor. For example, in one example, the address encoding circuit generates multiple address bits used to select multiple target memristors from the target region of the memristor array. In another example, the address encoding circuit generates at least one chip select bit and one start address bit. The at least one chip select bit is used to select a target region from multiple subarrays or partitions of the memristor array, and the start address bit is used to select a starting memristor from the target region of the memristor array as the first target memristor in the address chain. Then, multiple memristors are selected based on the first target memristor to generate multiple data.

[0068] For example, such as Figure 6 As shown, the address encoding circuit includes K+2 XOR tree circuits (e.g., the first row in the figure) and K XOR gate circuits (e.g., the second row in the figure) for generating the starting address bits, and 2 XOR tree circuits for generating the chip select bits (e.g., the third row in the figure). It should be noted that the address encoding circuit can also use other logic gate structures. Figure 6 The circuit structures shown are merely exemplary and are not intended to limit the embodiments of this disclosure.

[0069] For example, in at least one embodiment of this disclosure, the address encoding circuit 200 includes a first address encoding unit 210 connected to the fingerprint data generation circuit 400 and a second address encoding unit 220 connected to the random number generation circuit 100.

[0070] For example, in at least one embodiment of this disclosure, the second address encoding unit 220 is configured to encode input data to obtain intermediate address information. For example, the input data may be binary data initially provided to the circuit 10 implementing the PUF, or it may be an intermediate random number provided to the second address encoding unit 220 by the iteration control circuit 300 during the iteration process.

[0071] For example, in at least one embodiment of this disclosure, the random number generation circuit 100 is configured to generate intermediate random numbers through the second memristor array 101 and the third memristor array 102 based on the intermediate address information obtained by encoding the input data by the second address encoding unit 220.

[0072] For example, the second memristor array 101 and the third memristor array 102 address according to the intermediate address information, and read and output the data stored in the selected memristors in the second memristor array 101 and the third memristor array 102.

[0073] For example, in at least one embodiment of this disclosure, the random data output by the second memristor array 101 and the third memristor array 102 can be arranged or spliced ​​according to a preset rule to form an intermediate random number. For example, the preset rule specifies how to select the valid part of the random data output by the two memristor arrays, or specifies the arrangement order, splicing method, etc. of the random data of the two memristor arrays. The embodiments of this disclosure do not limit the preset rule.

[0074] For example, in one example, a preset rule specifies that the random data output by the second memristor array 101 and the third memristor array 102 are sequentially concatenated. For instance, the set of n random data output by the second memristor array 101 is Ma = {a1, a2, ..., a...} n The set of n random data output by the third memristor array 102 is Mb = {b1, b2, ..., b}. n}, concatenate sets Ma and Mb in a sequential manner to form an intermediate random number Mc, where Mc = {a1, a2, ..., a n b1, b2, ..., b n}

[0075] For example, in another example, a preset rule specifies that the first half of the data (considered as the valid part) from the multiple random data output by the second memristor array 101 and the second half of the data (considered as the valid part) from the multiple random data output by the third memristor array 102 are sequentially concatenated. For example, the set of 2n random data output by the second memristor array 101 is Md = {d1, d2, ..., dn}. 2n The set of 2n random data output by the third memristor array 102 is Me = {e1, e2, ..., e...} 2n}, concatenate the valid parts of sets Md and Me in a sequential manner to form an intermediate random number Mf, Mf = {d1, d2, ..., dm}. n ,e n+1 ,e n+2 ,……,e 2n}

[0076] In the above embodiments of this disclosure, the random number generation circuit 100 can effectively improve the data complexity of intermediate random numbers, increase the complexity of address encoding, reduce data correlation, and further improve hardware security by splicing multiple random data output from the second memristor array 101 and the third memristor array 102.

[0077] For example, in at least one embodiment of this disclosure, the iteration control circuit 300 is configured to provide an intermediate random number as input data to the second address encoding unit 220 in response to the fulfillment of the iteration condition, and to provide an intermediate random number to the first address encoding unit 210 in response to the non-fulfillment of the iteration condition.

[0078] For example, the iteration conditions can be a preset number of iterations set manually, or conditions such as the number of iterations and iteration time generated based on index parameters used to evaluate the data correlation between fingerprint data and input data. The embodiments of this disclosure do not limit the setting of iteration conditions.

[0079] For example, the iteration control circuit 300 is connected to the random number generation circuit 100 and the address encoding circuit 200. For example, when the number of iterations is less than the preset number of iterations r, the iteration control circuit 300 provides the intermediate random number generated by the random number generation circuit 100 as input data to the second address encoding unit 220 to continue the iteration process; when the number of iterations is equal to the preset number of iterations r, the iteration control circuit 300 ends the iteration process and provides the intermediate random number generated by the random number generation circuit 100 to the first address encoding unit 210.

[0080] In the above embodiments of this disclosure, the iterative control circuit 300 can realize repeated iterations between the input data and intermediate random numbers of the random number generation circuit 100, which can further improve the randomness of the final generated intermediate random numbers, increase the data complexity between the original input to the input data in the circuit 10 that implements PUF and the output fingerprint data, and effectively overcome the data correlation problem.

[0081] For example, in at least one embodiment of this disclosure, the first address encoding unit 210 is configured to encode an intermediate random number received from the iterative control circuit 300 to obtain first address information.

[0082] For example, after the iteration loop ends, the iteration control circuit 300 provides the intermediate random number from the random number generation circuit 100 to the first address encoding unit 210 of the address encoding circuit 200. The first address encoding unit 210 encodes the intermediate random number to obtain the first address information for selecting the target memristor from the first memristor array 401.

[0083] For example, in at least one embodiment of this disclosure, the fingerprint data generation circuit 400 is configured to select a plurality of first memristors from the first memristor array 401 according to first address information to generate fingerprint data.

[0084] For example, the first memristor array 401 addresses according to the first address information, selects multiple first memristors, obtains multiple data stored in the selected multiple first memristors, and then outputs the final fingerprint data.

[0085] For example, in at least one example of the embodiments of this disclosure, the fingerprint data generation circuit 400 is further configured to read multiple resistance values ​​of multiple first memristors and output multiple data corresponding to the multiple resistance values ​​as fingerprint data. For example, by reading multiple first memristors, multiple resistance values ​​of multiple memristors are read, thereby obtaining the data (e.g., binary data 0 or 1) stored in multiple first memristors.

[0086] For example, in at least one example of the embodiments of this disclosure, the fingerprint data generation circuit 400 may also apply a read voltage to a plurality of first memristors, obtain the output current of the plurality of first memristors from the source line corresponding to the plurality of first memristors, and obtain the data (e.g., binary data 0 or 1) stored in the plurality of first memristors by comparing the output current with the reference current.

[0087] The circuit 10 for implementing PUF provided in the above embodiments of this disclosure uses multiple memristor arrays to implement a strongly physically unclonable function, overcoming the problems of data randomness and stability. It has the advantages of simple circuit structure, small area, and low cost. The data correlation problem is solved by the interaction of multiple memristor arrays and iterative control circuits, which enables the output fingerprint data to change significantly with small changes in the input data, effectively improving data complexity and enhancing hardware security.

[0088] For example, in some embodiments of this disclosure, the second address encoding unit includes a second address encoding subunit connected to the second memristor array and a third address encoding subunit connected to the third memristor array. The second address encoding subunit encodes the input data input in the positive direction to obtain second address information, and the third address encoding subunit encodes the input data input in the negative direction to obtain third address information. The intermediate address information includes the second address information and the third address information.

[0089] For example, in some embodiments of this disclosure, the intermediate random number includes a first intermediate result generated by the second memristor array based on the second address information and a second intermediate result generated by the third memristor array based on the third address information.

[0090] Figure 7 This is a schematic diagram of the structure of an exemplary circuit implementing a physically unclonable function (PUF) provided for at least one embodiment of this disclosure. Figure 7As shown, the circuit 20 implementing the PUF includes a random number generation circuit, an address encoding circuit, an iterative control circuit 301, and a fingerprint data generation circuit. The random number generation circuit includes array A (e.g., corresponding to the second memristor array in this disclosure) and array B (e.g., corresponding to the third memristor array in this disclosure); the fingerprint data generation circuit includes array C (e.g., corresponding to the first memristor array in this disclosure); the address encoding circuit includes a second address encoding subunit 220-A connected to array A, a third address encoding subunit 220-B connected to array B, and a first address encoding subunit 210-C connected to array C.

[0091] For example, the circuit 20 implementing the PUF includes multiple memristor arrays: array A, array B, and array C. These three memristor arrays have the same array structure, each including multiple memristor cells arranged in multiple arrays, with each memristor cell including a transistor and a memristor. For example, arrays A, B, and C store multiple randomly distributed binary data (e.g., each memristor stores one bit of data 1 or 0).

[0092] For example, the initial input data provided to the circuit 20 implementing the PUF is C1, which is 2N bits of binary data. For example, the input data C1 is input to the second address encoding subunit 220-A and the third address encoding subunit 220-B in both forward (i.e., the most significant and least significant bits remain unchanged) and reverse (i.e., the most significant bit becomes the least significant bit, and the least significant bit becomes the most significant bit). For example, as... Figure 7 As shown, the second address encoding subunit 220-A receives the positive input data C1[1:1:2N] and encodes the positive input data C1[1:1:2N] to obtain the second address information E. A The third address encoding subunit 220-B receives the inverted input data C1[2N:-1:1] and encodes the inverted input data C1[2N:-1:1] to obtain the third address information E. B .

[0093] For example, array A connected to the second address encoding subunit 220-A is based on the second address information E. A Generate the first intermediate result M A The array B connected to the third address encoding subunit 220-B is based on the third address information E. B Generate the second intermediate result M B First intermediate result M A Second intermediate result M B Construct an intermediate random number Tc with the same length as the input data. For example, if the length of the input data C1 is 2N bits, the first intermediate result M... ASecond intermediate result M B The length of each is N bits, and the first intermediate result M is... A Second intermediate result M B All data are used as the valid part to form the intermediate random number, that is, the intermediate random number Tc = {M} A M B The length of the intermediate random number Tc is 2N bits, which ensures that the intermediate random number can be used as input data and input to the second address encoding subunit 220-A and the third address encoding subunit 220-B of the address encoding circuit through the iterative control circuit 301.

[0094] For example, the iterative control circuit 301 receives an intermediate random number Tc and determines whether the current iteration number is less than or equal to a preset iteration number r. If the current iteration number is less than or equal to the preset iteration number r, the iterative control circuit 301 provides the intermediate random number Tc as input data to the second address encoding subunit 220-A and the third address encoding subunit 220-B (e.g., ...). Figure 7 (As shown by the dashed line in the diagram), the iteration process continues. For example, the intermediate random number Tc is input forward into the second address encoding subunit 220-A and backward into the third address encoding subunit 220-B. The second address encoding subunit 220-A and the third address encoding subunit 220-B generate new second address information and third address information based on the intermediate random number Tc. Arrays A and B then generate new intermediate random numbers Tc' based on the new second address information and third address information, respectively, and provide them to the iteration control circuit 301. The preset number of iterations r can be set according to actual needs. For example, r=1, and the data complexity can be significantly improved through one iteration, effectively solving the data correlation problem. For example, by increasing the number of iterations, the data complexity can be further improved, making it possible to eliminate the correlation between data.

[0095] For example, if the current iteration number is greater than the preset iteration number r, the iteration stops, and the iteration control circuit 301 provides the intermediate random number Tc to the first address encoding unit 210-C connected to the array C. The first address encoding unit 210-C encodes the intermediate random number Tc to obtain the first address information E. C and the first address information E C Provided to array C, array C uses the first address information E C Generate the final fingerprint data R1.

[0096] For example, in at least one example of the embodiments of this disclosure, the intermediate address information includes intermediate start address bits, input data address bits, and intermediate addressing rules.

[0097] For example, the second address information E generated by the second address encoding subunit 220-AA The third address information E generated by the third address encoding subunit 220-B B This includes the intermediate start address, input data address, and intermediate addressing rules.

[0098] For example, in at least one example of the embodiments of this disclosure, the first address information includes a first starting address bit, a random number data address bit, and a first addressing rule.

[0099] For example, the first address information E generated by the first address encoding subunit 220-C C It includes the first starting address bit, the random number data address bit, and the first addressing rule.

[0100] For example, in one example, the circuit structures of the first address encoding subunit 220-C, the second address encoding subunit 220-A, and the third address encoding subunit 220-B are the same, for example, they all use... Figure 6 The circuit structure is shown below. The intermediate address information has a similar composition to the first address information. For ease of description, the generation of the second address information E will be explained in detail below using the second address encoding subunit 220-A as an example. A The process.

[0101] For example, in one example, the second address encoding subunit 220-A includes K+1 XOR tree circuits and K XOR gate circuits for generating intermediate start address bits. The number of XOR tree circuits depends on the size of the second memristor array (array A) connected to the second address encoding subunit 220-A; for example, array A has a size of 2... 11 row × 2 5 If the column is K, then K = 11 + 5.

[0102] For example, the positive input data C1 (2N bits in length) is divided into K+1 data groups, each containing 2N / (K+1) bits of data. The data from each of the K+1 data groups is then input into K+1 XOR tree circuits to obtain K+1 bits of intermediate output data. Alternatively, these K bits of intermediate output data can be input one-to-one into K XOR gate circuits, and the 1 bit of intermediate output data can also be input into K XOR gate circuits. After the K XOR gate circuits perform XOR operations on the K bits and 1 bit of intermediate output data, a K bits of intermediate starting address A1 is obtained.

[0103] It should be noted that, in some embodiments of this disclosure, the number of XOR tree circuits (e.g., K) and the size of the memristor array (e.g., the number of rows and columns) in the address encoding circuit can be designed based on the length of the input data (e.g., the length of C1 is 2N). That is, during circuit design, the length of the input data can be determined first, and then the circuit structure of the address encoding circuit (e.g., the number of XOR tree circuits and XOR gates) and the size of the memristor array can be further determined based on the length of the input data.

[0104] For example, in addition to generating an intermediate starting address bit A1 of length K bits, the second address encoding subunit 220-A can also obtain input data C1 of length 2N bits as input data address bits to obtain the second address information E. A The address bits. For example, the second address information E A The address bits include the intermediate start address bit A1 and the input data address bit, and the second address information E. A The total length of the address bits is M bits, where M = K + 2N.

[0105] For example, in the example above, the target memristor is first determined from array A based on the address of the intermediate starting address bit A1. Then, starting from the target memristor, multiple memristors are selected based on the input data address bits and intermediate addressing rules.

[0106] For example, in at least one example of the embodiments of this disclosure, the intermediate address information or the first address information further includes a region slice selection bit, which is used to select a target region from the partitions of the first memristor array, the second memristor array, or the third memristor array.

[0107] For example, in another example, the circuit structure of the second address encoding subunit 220-A is as follows: Figure 6 As shown, this includes K+2 XOR tree circuits for generating intermediate start address bits, K XOR gate circuits, and k (e.g., k=2) XOR tree circuits for generating region slice select bits. The number K of XOR tree circuits depends on the size of the second memristor array (array A) connected to the second address encoding subunit 220-A and the number of partitions; for example, the size of array A is 2... 11 row × 2 5 The number of columns and partitions is 2. 2 Then K = (11-1) + (5-1).

[0108] For example, the positive input data C1 (2N bits in length) is divided into K+2 data groups, each containing 2N / (K+2) bits of data. These K+2 data groups are then input into K+2 XOR tree circuits to obtain K+2 bits of intermediate output data. Alternatively, these K bits of intermediate output data can be input one-to-one into K XOR gate circuits, and the 2 bits of intermediate output data can also be input into K XOR gate circuits. After the K XOR gate circuits perform XOR operations on the K bits and 2 bits of intermediate output data, the starting address A2, which is K bits in length, is obtained.

[0109] For example, the intermediate address bit A2 and the 2 bits of intermediate output data are divided into two data groups. Each data group includes data of length K / 2+1 bits. The data of these two data groups are respectively input into two XOR tree circuits used to generate the area slice selection bit, resulting in an area slice selection bit CS of length 2 bits.

[0110] For example, in addition to generating a K-bit intermediate start address bit A2 and a K-bit region slice select bit CS, the second address encoding subunit 220-A can also acquire 2N-bit input data C1 as input data address bits to obtain the second address information E. A The address bits. For example, the second address information E A The address bits include the intermediate start address bit A1, the input data address bits, and the area slice select bit CS, and the second address information E. A The total length of the address bits is M bits, where M = K + 2N + k.

[0111] For example, in the example above, the target region is first selected from the four partitions of array A according to the region selection bit CS. Then, the target memristor is determined from the target region of array A according to the address of the intermediate starting address bit A1. Finally, starting from the target memristor, multiple memristors are selected according to the input data address bit and the intermediate addressing rules.

[0112] For example, addressing rules (intermediate addressing rules or first addressing rules) include rules applicable to start address bits (intermediate start address bits or first start address bits), data address bits (input data address bits or random number data address bits), or area selection bits.

[0113] For example, in some embodiments of this disclosure, the rules for the start address bits include: finding the row address of the target memristor (or the first memristor in this disclosure) based on the high-order bits of the start address bits, and finding the column address of the target memristor (or the first memristor in this disclosure) based on the low-order bits of the start address bits. For example, when the size of the memristor array is 2... 10row × 2 4 When the starting address is 001111 10000011, the high 10 bits of the starting address are the row address of the target memristor, and the low 4 bits are the column address of the target memristor. For example, based on this starting address, the memristor located in row 249 and column 4 of the memristor array can be identified as the target memristor.

[0114] For example, in some embodiments of this disclosure, the rules for the data address bits include: determining the addressing order in units of 2 bits. For example, in response to a data address bit of 00, the memristor located above the current memristor is selected in the next addressing step; in response to a data address bit of 01, the memristor located to the right of the current memristor is selected in the next addressing step; in response to a data address bit of 10, the memristor located below the current memristor is selected in the next addressing step; and in response to a data address bit of 11, the memristor located to the left of the current memristor is selected in the next addressing step.

[0115] For example, in some embodiments of this disclosure, the rules for data address bits further include: if the next addressing position exceeds the boundary of the memristor array, then the next addressing continues from the boundary opposite to the overflow boundary. For example, in response to the next addressing position overflowing the upper boundary of the memristor array, the next addressing continues from the lower boundary of the memristor array; in response to the next addressing position overflowing the right boundary of the memristor array, the next addressing continues from the left boundary of the memristor array; in response to the next addressing position overflowing the lower boundary of the memristor array, the next addressing continues from the upper boundary of the memristor array; in response to the next addressing position overflowing the left boundary of the memristor array, the next addressing continues from the right boundary of the memristor array.

[0116] For example, in some embodiments of this disclosure, the rules for region selection include: determining the partitions of the memristor array based on the length of the region selection bit. For example, if the length of the region selection bit CS is 1 bit, the memristor array can be divided into two regions, left and right (or top and bottom). When CS = 0, one partition is selected as the target region; when CS = 1, the other partition is selected as the target region. For example, if the length of the region selection bit CS is 2 bits, the memristor array can be divided into four regions, denoted as 00, 01, 10, and 11 respectively. The length of CS can also be 3 bits, etc., and the embodiments of this disclosure do not limit this.

[0117] It should be noted that the addressing rules (including intermediate addressing rules or first addressing rules) can be set according to actual needs, and the embodiments disclosed herein do not impose any restrictions on this.

[0118] For example, the above process can be implemented using the following code. For example, the memristor array has m rows and n columns, the input data C has a length of N, the memristor's row address is addr_col, and the column address is...

[0119]

[0120]

[0121] For example, such as Figure 10 As shown in (a), the memristor array (e.g., array A) includes 2 2 ×2 2 Given a memristor array with a starting address A1 = 1101, the memristor in the 4th row and 2nd column can be identified as the target memristor according to the addressing rules described above. For example, ... Figure 10 As shown in (b), the input data address C1 = 01000110. According to the addressing rules described above, four memristors can be selected. For example, using every two bits of the input data address as a unit, the first memristor in the 4th row and 3rd column, the second memristor in the 3rd row and 3rd column, the third memristor in the 3rd row and 4th column, and the fourth memristor in the 4th row and 4th column are selected sequentially according to "01", "00", "01", and "10". For example, if the first, second, third, and fourth memristors randomly store the data 1, 0, 0, and 1 respectively, then the first intermediate result M generated by array A will be... A It is 1001.

[0122] It should be noted that the intermediate addressing rules and the first addressing rules can be the same or different. For example, the rule for intermediate data address bits is 00 corresponding to the top, 01 to the right, 10 to the bottom, and 11 to the left; the rule for random number data address bits is 00 corresponding to the bottom, 01 to the left, 10 to the top, and 11 to the right. The intermediate addressing rules for the second address encoding subunit 220-A and the third address encoding subunit 220-B can be the same or different. For example, the rule for the area slice selection bit of array A is: when CS=0, the left area is selected as the target area; when CS=1, the right area is selected as the target area. The rule for the area slice selection bit of array B is: when CS=0, the right area is selected as the target area; when CS=1, the left area is selected as the target area.

[0123] For example, in some other embodiments of this disclosure, the random number generation circuit may further include a larger number of memristor arrays, such as a fourth memristor array and a fifth memristor array, thereby further increasing the complexity of the data and reducing data correlation. Correspondingly, the second address encoding unit may further include a fourth address encoding subunit connected to the fourth memristor array, a fifth address encoding subunit connected to the fifth memristor array, etc., and the embodiments of this disclosure do not limit this.

[0124] For example, in one example, the fourth address encoding subunit encodes the input data input in either the forward or reverse direction to obtain the fourth address information, and the intermediate address information includes the second address information, the third address information, and the fourth address information.

[0125] For example, in another example, the fourth address encoding subunit encodes the input data of the forward input to obtain the fourth address information, the fifth address encoding subunit encodes the input data of the reverse input to obtain the fifth address information, and the intermediate address information includes the second address information, the third address information, the fourth address information, and the fifth address information.

[0126] The following is a brief introduction to the circuit structure of multiple memristor arrays, using a random number generation circuit consisting of three memristor arrays as an example.

[0127] Figure 8 This is a schematic diagram of the structure of another exemplary circuit for implementing a physically unclonable function, provided for at least one embodiment of this disclosure. Figure 8 As shown, the circuit 30 implementing the PUF includes a random number generation circuit, an address encoding circuit, an iteration control circuit 302, and a fingerprint data generation circuit. The random number generation circuit includes array D (e.g., corresponding to the second memristor array in this disclosure), array E (e.g., corresponding to the third memristor array in this disclosure), and array F (e.g., corresponding to the fourth memristor array in this disclosure); the fingerprint data generation circuit includes array G (e.g., corresponding to the first memristor array in this disclosure); the address encoding circuit includes a second address encoding subunit 220-D connected to array D, a third address encoding subunit 220-E connected to array E, a fourth address encoding subunit 220-F connected to array F, and a first address encoding subunit 210-G connected to array G.

[0128] For example, the initial input data provided to the circuit 30 implementing the PUF is C2, and input data C2 is 2N bits of binary data. For example, as Figure 8 As shown, input data C2 is input into the second address encoding subunit 220-D, the third address encoding subunit 220-E, and the fourth address encoding subunit 220-F in forward, reverse, and reverse directions, respectively. For example, as... Figure 8As shown, the second address encoding subunit 220-D receives the positive input data C2[1:1:2N] and encodes the positive input data C2[1:1:2N] to obtain the second address information E. D The third address encoding subunit 220-E receives the inverted input data C2[2N:-1:1] and encodes the inverted input data C2[2N:-1:1] to obtain the third address information E. E The fourth address encoding subunit 220-F receives the inverted input data C2[2N:-1:1] and encodes the inverted input data C2[2N:-1:1] to obtain the fourth address information E. F .

[0129] For example, array D connected to the second address encoding subunit 220-D is based on the second address information E. D Generate the first intermediate result M D The array E connected to the third address encoding subunit 220-E is based on the third address information E E Generate the second intermediate result M E The array F connected to the fourth address encoding sub-unit 220-F is based on the fourth address information E. F Generate the fourth intermediate result M F First intermediate result M D Second intermediate result M E and the third intermediate result M F Construct intermediate random numbers Tc with the same length as the input data. For example, if the length of the input data C1 is 2N bits, the first intermediate result M... D Second intermediate result M E and the third intermediate result M F The length of each result is N bits, and the first intermediate result M is taken. D Second intermediate result M E and the third intermediate result M F A portion of the data is used as the valid part to form intermediate random numbers. For example, the first intermediate result M is taken. D The first N1 bits of data, the second intermediate result M E The first N2 bits of data and the third intermediate result M F The first N3 bits of data form the intermediate random number, that is, the length of the intermediate random number Tc is N1+N2+N3=2N bits, thus ensuring that the intermediate random number can be used as input data and input to the address encoding circuit through the iterative control circuit 302.

[0130] about Figure 8 For detailed descriptions of other units or circuit structures of the circuit 30 of the PUF shown, please refer to [link / reference]. Figure 7 The description of the circuit 20 of the PUF shown will not be repeated (or similar) in any way.

[0131] At least one embodiment of this disclosure also provides an operational method for implementing a circuit that implements a physically unclonable function (PUF). This operational method can be implemented by the circuit that implements the PUF provided in any embodiment of this disclosure, for example, by... Figure 3 The circuit 10 shown implements the PUF. Figure 7 The circuit 20 shown implements the PUF or Figure 8 The circuit 30 shown implements the PUF. For example, the circuit implementing the PUF includes a random number generation circuit, an address encoding circuit, a fingerprint data generation circuit, and an iterative control circuit. For example, the fingerprint data generation circuit includes a first memristor array, the random number generation circuit includes a second memristor array and a third memristor array, and the address encoding circuit includes a first address encoding unit connected to the fingerprint generation circuit and a second address encoding unit connected to the random number generation circuit.

[0132] Figure 9 This is a flowchart illustrating an operation method provided in at least one embodiment of this disclosure. Figure 9 As shown, the operation method includes steps S100 to S500.

[0133] Step S100: Based on the intermediate address information obtained by encoding the input data using the second address encoding unit, an intermediate random number is generated using the second memristor array and the third memristor array of the random number generation circuit.

[0134] Step S200: In response to the fulfillment of the iteration condition, the intermediate random number is provided as input data to the second address encoding unit through the iteration control circuit.

[0135] Step S300: In response to the failure to meet the iteration condition, the intermediate random number is provided to the first address encoding unit through the iteration control circuit.

[0136] Step S400: The intermediate random number received from the iterative control circuit is encoded by the first address encoding unit to obtain the first address information.

[0137] Step S500: The fingerprint data generation circuit selects multiple first memristors from the first memristor array based on the first address information to generate fingerprint data.

[0138] For example, step S100 can be performed by Figure 3 The random number generation circuit 100 in the middle is implemented, and steps S200 and S300 can be implemented by... Figure 3 The iterative control circuit 300 in the middle is implemented, and step S400 can be implemented by... Figure 3The first address encoding unit 210 of the address encoding circuit 200 in the middle is implemented, and step S500 can be implemented by... Figure 3 The fingerprint data generation circuit 400 in the above circuit is implemented. For detailed explanations of the above steps, please refer to the relevant descriptions of the circuits 10, 20, or 30 that implement the PUF, which will not be repeated here.

[0139] For example, in at least one example of the embodiments of this disclosure, step S100, which is to generate intermediate random numbers by encoding intermediate address information obtained by encoding input data according to the second address encoding unit, through the second memristor array and the third memristor array of the random number generation circuit, may include: reading the intermediate start address bit, input data address bit and intermediate addressing rule in the intermediate address information; determining the starting memristor in the second memristor array and the third memristor array according to the intermediate start address bit; selecting multiple memristors starting from the starting memristor according to the input data address bit and the intermediate addressing rule; and outputting multiple data stored in the multiple memristors as intermediate random numbers.

[0140] For example, in at least one example of the embodiments of this disclosure, step S500, which involves the fingerprint data generation circuit selecting multiple first memristors from the first memristor array according to the first address information to generate fingerprint data, may include: reading the first starting address bit, the random number data address bit, and the first addressing rule in the first address information; determining the starting memristor in the first memristor array according to the first starting address bit; selecting multiple first memristors starting from the starting memristor according to the random number data address bit and the first addressing rule; and outputting multiple data stored in the multiple first memristors as fingerprint data.

[0141] Figure 11 A probability distribution map of fingerprint data generated by a circuit implementing a physically unclonable function, provided in at least one embodiment of this disclosure. Figure 11 (a) illustrates at least one embodiment of this disclosure (such as...) Figure 7 The embodiment shown provides 128 sets of fingerprint data (i.e., ...) generated after one iteration of the circuit implementing PUF. Figure 7 The fingerprint data R1 generated by circuit 20 shown has a length N = 128. The memristor used is 27 rows × 27 columns, and the corresponding input data C (e.g., converted to decimal) increases from 1 to 128. If the input data is further increased to 10... 4 10 were obtained 4 128-bit fingerprint data as follows Figure 11 As shown in (b) in the diagram. From Figure 11As can be seen from (a) and (b), in the fingerprint data generated by the circuit implementing PUF, the probabilities of 0 and 1 are almost equal, with the probability of 1 appearing being 49.86%. The 0 and 1 in the fingerprint data are uniformly and randomly distributed. When the input data changes slightly, the fingerprint data output by the circuit implementing PUF will change significantly, showing no data correlation.

[0142] Figure 12 This is a Hamming distance distribution map of fingerprint data generated by a circuit implementing a physically unclonable function (PUF) according to at least one embodiment of this disclosure. The Hamming distance represents the difference between data sets; for example, a Hamming distance of 0 indicates that two sets of data are completely identical, and a Hamming distance of 0.5 indicates that half of the two sets of data are different. For a strong PUF circuit, the ideal value for the Hamming distance between the output fingerprint data is 0.5. Figure 12 As shown, for such Figure 7 The circuit 20 shown for implementing PUF demonstrates that, under conditions of very small input differences, the Hamming distance between different fingerprint data satisfies a Gaussian distribution with a mean of 0.5, proving that the circuit for implementing PUF provided in at least one embodiment of this disclosure has strong randomness and very weak data correlation.

[0143] For example, Figure 8 The circuit 30 shown is compared to Figure 7 The circuit 20 shown employs more memristor arrays, which can further improve data complexity and solve data correlation problems, and can be used in integrated chips and electronic devices with higher security requirements.

[0144] At least one embodiment of this disclosure also provides an integrated circuit chip, which includes the circuit structure for implementing a physically unclonable function (PUF) provided in any embodiment of this disclosure.

[0145] At least one embodiment of this disclosure also provides an electronic device that includes an integrated circuit chip. For example, the electronic device can be an Internet of Things (IoT) device, including but not limited to mobile terminal devices such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), smart wearable devices, and fixed terminal devices such as digital TVs, desktop computers, smart home devices, medical devices, and so on.

[0146] The integrated circuit chips and electronic devices provided in this disclosure can overcome data correlation problems, improve data complexity, enhance the ability of integrated circuit chips to resist machine learning algorithm attacks, and increase hardware security by implementing PUF circuits.

[0147] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0148] The following points should be noted regarding this disclosure:

[0149] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0150] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0151] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0152] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A circuit for implementing a physically unclonable function, comprising a random number generation circuit, an address encoding circuit, a fingerprint data generation circuit, and an iterative control circuit. in, The fingerprint data generation circuit includes a first memristor array, the random number generation circuit includes a second memristor array and a third memristor array, and the address encoding circuit includes a first address encoding unit connected to the first memristor array and a second address encoding unit connected to the random number generation circuit. The random number generation circuit is configured to generate intermediate random numbers through the second memristor array and the third memristor array based on the intermediate address information obtained by encoding the input data by the second address encoding unit. The iterative control circuit is configured to provide the intermediate random number as input data to the second address encoding unit in response to satisfying the iteration condition, and to provide the intermediate random number to the first address encoding unit in response to not satisfying the iteration condition. The first address encoding unit is configured to encode the intermediate random number received from the iterative control circuit to obtain first address information; The fingerprint data generation circuit is configured to select multiple first memristors from the first memristor array based on the first address information to generate fingerprint data.

2. The circuit according to claim 1, wherein, The second address encoding unit includes a second address encoding subunit connected to the second memristor array and a third address encoding subunit connected to the third memristor array. The second address encoding subunit encodes the input data input in the forward direction to obtain second address information, and the third address encoding subunit encodes the input data input in the reverse direction to obtain third address information. The intermediate address information includes the second address information and the third address information.

3. The circuit according to claim 2, wherein, The intermediate random number includes a first intermediate result generated by the second memristor array based on the second address information and a second intermediate result generated by the third memristor array based on the third address information.

4. The circuit according to claim 2, wherein, The random number generation circuit further includes a fourth memristor array, and the second address encoding unit further includes a fourth address encoding subunit connected to the fourth memristor array. The fourth address encoding subunit encodes the input data input in either the forward or reverse direction to obtain the fourth address information. The intermediate address information includes the second address information, the third address information, and the fourth address information.

5. The circuit according to claim 4, wherein, The intermediate random number includes a first intermediate result generated by the second memristor array based on the second address information, a second intermediate result generated by the third memristor array based on the third address information, and a third intermediate result generated by the fourth memristor array based on the fourth address information.

6. The circuit according to any one of claims 1-5, wherein, Multiple memristors in the first memristor array, the second memristor array, or the third memristor array store multiple randomly distributed data.

7. The circuit according to any one of claims 1-5, wherein, The intermediate address information includes intermediate starting address bits, input data address bits, and intermediate addressing rules. The first address information includes a first starting address bit, random number data address bits, and a first addressing rule.

8. The circuit according to claim 7, wherein, The intermediate address information or the first address information further includes a region slice selection bit, which is used to select a target region from the partitions of the first memristor array, the second memristor array, or the third memristor array.

9. The circuit according to claim 7, wherein, The intermediate addressing rule may be the same as or different from the first addressing rule.

10. The circuit according to any one of claims 1-5, wherein, The fingerprint data generation circuit is further configured to read multiple resistance values ​​of the plurality of first memristors and output multiple data corresponding to the plurality of resistance values ​​as the fingerprint data.

11. The circuit according to any one of claims 1-5, wherein, The address encoding circuit includes an XOR tree circuit.

12. A method for operating a circuit that implements a physically unclonable function, wherein the circuit implementing the physically unclonable function includes a random number generation circuit, an address encoding circuit, a fingerprint data generation circuit, and an iterative control circuit. in, The fingerprint data generation circuit includes a first memristor array, the random number generation circuit includes a second memristor array and a third memristor array, and the address encoding circuit includes a first address encoding unit connected to the first memristor array and a second address encoding unit connected to the random number generation circuit. The operation method includes: Based on the intermediate address information obtained by encoding the input data using the second address encoding unit, an intermediate random number is generated using the second memristor array and the third memristor array of the random number generation circuit. In response to satisfying the iteration condition, the intermediate random number is provided as the input data to the second address encoding unit through the iteration control circuit; In response to the failure to meet the iteration condition, the intermediate random number is provided to the first address encoding unit through the iteration control circuit; The first address information is obtained by encoding the intermediate random number received from the iterative control circuit through the first address encoding unit; The fingerprint data generation circuit selects multiple first memristors from the first memristor array based on the first address information to generate fingerprint data.

13. The operating method according to claim 12, wherein, The step of selecting multiple first memristors from the first memristor array based on the first address information to generate fingerprint data by the fingerprint data generation circuit includes: Read the first starting address bit, the random number data address bit, and the first addressing rule from the first address information; The starting memristor in the first memristor array is determined based on the first starting address bit. The plurality of first memristors are selected starting from the initial memristor based on the random number data address bits and the first addressing rule; The multiple data stored in the multiple first memristors are output as the fingerprint data.

14. An integrated circuit chip comprising the circuit that implements a physically unclonable function as described in any one of claims 1-11.

15. An electronic device comprising the integrated circuit chip of claim 14.

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