Software simulation method and device of FPGA based on electrochemical model and electronic equipment

Abstract

The application provides a software simulation method and device based on an electrochemical model FPGA and electronic equipment, and the method comprises the following steps: running a hardware description language to obtain an FPGA hardware simulation environment; obtaining software code and hardware code of the electrochemical model, running the software code of the electrochemical model to obtain a plurality of software result variables of the electrochemical model, and running the hardware code of the electrochemical model in the FPGA hardware simulation environment to obtain a plurality of hardware result variables of the electrochemical model; processing the plurality of software result variables and the plurality of hardware result variables to determine sensitive variables in the hardware result variables, and storing the determined sensitive variables in a simulation file library. Through the software simulation method and device based on the electrochemical model FPGA and the electronic equipment provided in the application, the development time of the hardware calculation device of the electrochemical model is shortened, and the development efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of computational simulation technology, and more specifically, to a software simulation method, apparatus, and electronic device for FPGA based on an electrochemical model. Background Technology

[0002] Currently, electrochemical models (models that describe the charge-discharge behavior of batteries from an electrochemical mechanism perspective by quantifying the microscopic reaction processes such as electrochemical reaction kinetics, mass transfer, and heat transfer within the battery) require a large amount of computation as predictive models for batteries. Developing new hardware computing devices for electrochemical models necessitates referencing previous experience. Because electrochemical models involve numerous and complex calculations, relying on past experience requires manually running the electrochemical model many times on the hardware computing device, which leads to a very long development time for the entire hardware computing device for electrochemical models. Summary of the Invention

[0003] To address the aforementioned issues, the purpose of this application is to provide a software simulation method, apparatus, and electronic device for FPGA based on an electrochemical model.

[0004] In a first aspect, embodiments of this application provide a software simulation method for FPGA based on an electrochemical model, comprising:

[0005] Run the hardware description language to obtain the FPGA hardware simulation environment;

[0006] Obtain the software and hardware code of the electrochemical model, run the software code of the electrochemical model to obtain multiple software result variables of the electrochemical model, and run the hardware code of the electrochemical model in the FPGA hardware simulation environment to obtain multiple hardware result variables of the electrochemical model.

[0007] The multiple software result variables and the multiple hardware result variables are processed to determine the sensitive variables among the hardware result variables, and the determined sensitive variables are stored in the simulation file library.

[0008] Secondly, embodiments of this application also provide a software simulation device for an FPGA based on an electrochemical model, comprising:

[0009] The runtime module is used to run the hardware description language to obtain the FPGA hardware simulation environment;

[0010] The first processing module is used to retrieve the software code and hardware code of the electrochemical model, run the software code of the electrochemical model to obtain multiple software result variables of the electrochemical model, and run the hardware code of the electrochemical model in the FPGA hardware simulation environment to obtain multiple hardware result variables of the electrochemical model.

[0011] The second processing module is used to process the multiple software result variables and the multiple hardware result variables, determine the sensitive variables among the hardware result variables, and store the determined sensitive variables in the simulation file library.

[0012] Thirdly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the method described in the first aspect above.

[0013] Fourthly, embodiments of this application also provide an electronic device, the electronic device including a memory, a processor and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor using the steps of the method described in the first aspect above.

[0014] In the solutions provided in the first to fourth aspects of this application, an FPGA hardware simulation environment is obtained by running a hardware description language, the software code of the electrochemical model is run to obtain multiple software result variables of the electrochemical model, and the hardware code of the electrochemical model is run in the FPGA hardware simulation environment to obtain multiple hardware result variables of the electrochemical model. The multiple software result variables and the multiple hardware result variables are processed to determine the sensitive variables among the hardware result variables. Compared with the related technologies that require manual running of the electrochemical model many times in the hardware computing device to obtain previous experience when designing a new hardware computing device to run the electrochemical model, the sensitive variables in the hardware results can be determined by running the hardware code of the electrochemical model in the FPGA hardware simulation environment. This eliminates the need for manual running of the electrochemical model multiple times in the hardware computing device to obtain the sensitive variables in the hardware result variables, shortening the development time of the hardware computing device for the electrochemical model and improving development efficiency.

[0015] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1A flowchart of a software simulation method for an FPGA based on an electrochemical model, as provided in Embodiment 1 of this application, is shown.

[0018] Figure 2 A schematic diagram of the structure of an FPGA-based software simulation device based on an electrochemical model provided in Embodiment 2 of this application is shown.

[0019] Figure 3 A schematic diagram of the structure of an electronic device provided in Embodiment 3 of this application is shown. Detailed Implementation

[0020] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0023] Currently, electrochemical models (models that describe the charge-discharge behavior of batteries from an electrochemical mechanism perspective by quantifying the microscopic reaction processes such as electrochemical reaction kinetics, mass transfer, and heat transfer within the battery) require a large amount of computation as predictive models for batteries. Developing new hardware computing devices for electrochemical models necessitates referencing previous experience. Because electrochemical models involve numerous and complex calculations, relying on past experience requires manually running the electrochemical model many times on the hardware computing device, which leads to a very long development time for the entire hardware computing device for electrochemical models.

[0024] Based on this, this embodiment proposes a software simulation method, device, and electronic device for FPGA based on an electrochemical model. By running a hardware description language, an FPGA hardware simulation environment is obtained. The software code of the electrochemical model is run to obtain multiple software result variables of the electrochemical model. The hardware code of the electrochemical model is then run in the FPGA hardware simulation environment to obtain multiple hardware result variables of the electrochemical model. These multiple software result variables and multiple hardware result variables are processed to determine the sensitive variables among the hardware result variables. Thus, sensitive variables in the hardware results can be determined by running the hardware code of the electrochemical model in the FPGA hardware simulation environment. This eliminates the need for manual multiple runs of the electrochemical model in the hardware computing device, shortening the development time of the hardware computing device for the electrochemical model and improving development efficiency.

[0025] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0026] Example 1

[0027] The server is the main execution entity for the FPGA software simulation method based on the electrochemical model proposed in this embodiment.

[0028] See Figure 1 The flowchart shown illustrates a software simulation method for FPGA based on an electrochemical model. This embodiment proposes a software simulation method for FPGA based on an electrochemical model, which includes the following specific steps:

[0029] Step 100: Run the hardware description language to obtain the FPGA hardware simulation environment.

[0030] In step 100 above, the hardware description language may be, but is not limited to, Verilog, VHDL, SystemVerilog, or Chisel hardware description language.

[0031] The specific process of running a hardware description language to obtain an FPGA hardware simulation environment is existing technology and will not be elaborated here.

[0032] Step 102: Obtain the software code and hardware code of the electrochemical model, run the software code of the electrochemical model to obtain multiple software result variables of the electrochemical model, and run the hardware code of the electrochemical model in the FPGA hardware simulation environment to obtain multiple hardware result variables of the electrochemical model.

[0033] In step 102 above, in one embodiment, the software code is Python software code; the hardware code is Verilog hardware code.

[0034] The software and hardware code are pre-written and stored on the server.

[0035] For example, the electrochemical model can be an electrodecoupling model, and the specific formulas for the electrodecoupling model are shown in Formulas 1 to 5 below:

[0036] η=y[i]-yy[i] (1)

[0037] di=a*i*(t-1 / t) (2)

[0038] cur[i+1]=cur[i]-di*dX (3)

[0039] y[i+1]=y[i]-cur[i+1]*dX / ds (4)

[0040] yy[i+1]=yy[i]-(in_cur-cur[i])*dX / σ+(1-tc)*(ce[i]-ce[i+1]) (5)

[0041] Where η is the overpotential, representing the difference between the solid-phase voltage and the liquid-phase voltage; y[i] is the solid-phase voltage at the current time i; yy[i] is the liquid-phase voltage at the current time i; y[i+1] is the iterative solid-phase voltage at the next time after the current time i; yy[i+1] is the iterative liquid-phase voltage at the next time after the current time i; di is the reaction rate per unit area of ​​the battery; a is the effective cross-sectional area of ​​the battery; i is the exchange current value; and t is the e η , cur[i] is the reaction current value at the current time i, cur[i+1] is the reaction current value at the next time after the current time i, dX is the thickness of each equal part of the positive / negative electrode separator, ds is the solid-phase diffusion coefficient, in_cur is the input current, σ is the solid-phase conductivity, tc is the lithium-ion transport number, ce[i] is the liquid phase concentration at the current time i, and ce[i+1] is the liquid phase velocity at the next time after the current time i.

[0042] Here, e ηIn this context, e is the natural constant.

[0043] In Equations 1 to 5 above, y[i], yy[i], a, i, dX, ds, and tc are known quantities, while the remaining parameters are unknown quantities, i.e., the physical quantities to be solved in the electro-decoupling model.

[0044] If the electrochemical model is an electrodecoupling model, then the software code of the electrodecoupling model is the software code that contains the contents of Formulas 1 to 5 above; and the hardware code of the electrodecoupling model is the hardware code that contains the contents of Formulas 1 to 5 above.

[0045] Running the software code of the electrochemical model in a Python program yields multiple software result variables of the electrochemical model. If the electrochemical model is an electrodecoupling model, then these multiple software result variables are the variable calculation results obtained by running the software code of the electrodecoupling model in Python to solve for the unknowns in Equations 1 to 5 above.

[0046] The result of variable calculation is the result of unknown calculation.

[0047] The multiple software result variables of the obtained electrochemical model are stored in text files in the simulation file library by the server.

[0048] The simulation file library runs on the server.

[0049] The specific process of running the software code of the electrochemical model in a Python program to obtain multiple software result variables of the electrochemical model is existing technology and will not be elaborated here.

[0050] In the FPGA hardware simulation environment obtained using the Verilog hardware description language, the hardware code of the electrochemical model is run to obtain multiple hardware result variables of the electrochemical model. If the electrochemical model is an electrodecoupled model, then these multiple hardware result variables are the variable calculation results obtained by running the hardware code of the electrodecoupled model in the FPGA hardware simulation environment to solve the unknowns of Equations 1 to 5 above.

[0051] The specific process of running the hardware code of the electrochemical model and obtaining multiple hardware result variables of the electrochemical model in the FPGA hardware simulation environment obtained by the Verilog hardware description language is existing technology and will not be elaborated here.

[0052] The resulting hardware outcome variables of the electrochemical model are stored in text files in the simulation file library by the server.

[0053] Step 104: Process the multiple software result variables and the multiple hardware result variables to determine the sensitive variables among the hardware result variables, and store the determined sensitive variables in the simulation file library.

[0054] In step 104 above, the multiple software result variables and the multiple hardware result variables are processed using Python in the simulation file library. Specifically, the following steps (1) to (6) can be performed:

[0055] (1) Calculate the difference between the software result variables and the hardware result variables with the same dimension among the plurality of software result variables and the plurality of hardware result variables;

[0056] (2) Among the plurality of hardware result variables, the hardware result variables whose difference from the software result variables is greater than the difference threshold are identified as sensitive variables;

[0057] (3) Input a distorted clock signal into the FPGA hardware simulation environment to interfere with the clock signal of the FPGA hardware simulation environment;

[0058] (4) Run the hardware code of the electrochemical model in the FPGA hardware simulation environment where the clock signal is interfered with, and obtain multiple hardware output variables of the electrochemical model.

[0059] (5) Calculate the difference between the software result variables and the hardware output variables with the same dimension among the plurality of software result variables and the plurality of hardware output variables;

[0060] (6) Among the plurality of hardware output variables, the hardware output variable whose difference from the software result variable is greater than the difference threshold is identified as a sensitive variable.

[0061] In step (1) above, the server reads multiple hardware result variables and multiple software result variables recorded in the text file, obtains software result variables and hardware result variables with the same dimensions, and calculates the difference between software result variables and hardware result variables with the same dimensions.

[0062] In step (2) above, in one embodiment, the difference threshold can be set to 10.

[0063] Of course, the difference threshold can be set to other values ​​according to actual needs, which will not be elaborated here.

[0064] In step (3) above, the distorted clock signal includes, but is not limited to, a triangular wave clock signal and a trapezoidal wave clock signal.

[0065] In order to interfere with the clock signal of the FPGA hardware simulation environment, the following steps can be performed:

[0066] A triangular wave clock signal or a trapezoidal wave clock signal is input into the FPGA hardware simulation environment to interfere with the clock signal of the FPGA hardware simulation environment.

[0067] In step (4) above, multiple hardware output variables are the results of variable calculation of the electrochemical model obtained by running the hardware code of the electrochemical model in the FPGA hardware simulation environment where the clock signal is interfered with, obtained by the Verilog hardware description language.

[0068] In step (5) above, the specific process of calculating the difference between the software result variables and hardware output variables with the same dimension among the multiple software result variables and the multiple hardware output variables is similar to the process of calculating the difference between the software result variables and hardware output variables with the same dimension among the multiple software result variables and the multiple hardware result variables in step (1) above, and will not be repeated here.

[0069] In step (6) above, the sensitive variable is the variable among multiple hardware output variables or multiple hardware result variables that has a large calculation error with the software result variable and is prone to calculation error.

[0070] Continuing with the example of an electrochemical model that is an electrodecoupling model, through the process executed in steps (1) to (6) above, not only can the final calculation results such as η, di, y[i+1], and yy[i+1] in the electrodecoupling model be output, but also intermediate variables such as tc, in_cur, cur[i], dX, and ds in the solution process can be obtained. Thus, the sensitive variables among the intermediate variables of the electrodecoupling model can be determined. Compared with the method in related technologies that can only obtain the sensitive variables of the final calculation results of the electrochemical model, the sensitive variables that are prone to calculation errors among the intermediate variables in the electrochemical model can be further obtained. Thus, it is possible to find out which intermediate variable errors caused the errors in the final results, so as to find out the source of the problem as soon as possible and solve it, further shortening the development time of the hardware computing device of the electrochemical model and improving the development efficiency.

[0071] The FPGA software simulation method based on an electrochemical model proposed in this embodiment directly compares the results of software and hardware simulations to identify sensitive variables, making it simple and convenient to operate. Moreover, the identified sensitive variables can be stored in a simulation file library, providing experience for the hardware implementation of subsequent analysis programs and shortening hardware development time. Furthermore, feedback from problems in actual modules can be used to modify the simulation file library, thereby gradually improving the simulation file library and ultimately significantly reducing the development cycle of a series of hardware products.

[0072] In summary, this embodiment proposes a software simulation method for FPGA based on an electrochemical model. By running a hardware description language, an FPGA hardware simulation environment is obtained. The software code of the electrochemical model is then run to obtain multiple software result variables. The hardware code of the electrochemical model is then run in the FPGA hardware simulation environment to obtain multiple hardware result variables. These multiple software and hardware result variables are processed to determine the sensitive variables among them. Compared to related technologies that require manual execution of the electrochemical model multiple times on a hardware computing device to gain prior experience when designing a new hardware computing device that runs the electrochemical model, this method determines the sensitive variables in the hardware results by running the hardware code of the electrochemical model in the FPGA hardware simulation environment. This eliminates the need for multiple manual runs of the electrochemical model on the hardware computing device, shortening the development time of the electrochemical model hardware computing device and improving development efficiency.

[0073] Example 2

[0074] This embodiment proposes a software simulation device for FPGA based on an electrochemical model, used to execute the software simulation method for FPGA based on an electrochemical model proposed in Embodiment 1 above.

[0075] See Figure 2 The diagram shows a structural schematic of an FPGA software simulation device based on an electrochemical model. This embodiment proposes an FPGA software simulation device based on an electrochemical model, comprising:

[0076] The runtime module 200 is used to run the hardware description language to obtain the FPGA hardware simulation environment.

[0077] The first processing module 202 is used to retrieve the software code and hardware code of the electrochemical model, run the software code of the electrochemical model to obtain multiple software result variables of the electrochemical model, and run the hardware code of the electrochemical model in the FPGA hardware simulation environment to obtain multiple hardware result variables of the electrochemical model.

[0078] The second processing module 204 is used to process the plurality of software result variables and the plurality of hardware result variables, determine the sensitive variables among the hardware result variables, and store the determined sensitive variables in the simulation file library.

[0079] Specifically, the second processing module 204 is used for:

[0080] Calculate the difference between the software result variables and the hardware result variables that have the same dimension among the plurality of software result variables and the plurality of hardware result variables;

[0081] Among the multiple hardware outcome variables, the hardware outcome variables whose difference from the software outcome variables is greater than a difference threshold are identified as sensitive variables.

[0082] Furthermore, the second processing module 204 is also specifically used for:

[0083] A distorted clock signal is input into the FPGA hardware simulation environment to interfere with the clock signal of the FPGA hardware simulation environment.

[0084] The hardware code of the electrochemical model is run using the FPGA hardware simulation environment where the clock signal is interfered with, to obtain multiple hardware output variables of the electrochemical model;

[0085] Calculate the difference between the software result variables and the hardware output variables that have the same dimension among the plurality of software result variables and the plurality of hardware output variables;

[0086] Among the plurality of hardware output variables, the hardware output variables whose difference from the software result variables is greater than a difference threshold are identified as sensitive variables.

[0087] Specifically, the distorted clock signal includes a triangular wave clock signal and a trapezoidal wave clock signal.

[0088] The second processing module 204 is used to input a distorted clock signal into the FPGA hardware simulation environment to interfere with the clock signal of the FPGA hardware simulation environment, including:

[0089] A triangular wave clock signal or a trapezoidal wave clock signal is input into the FPGA hardware simulation environment to interfere with the clock signal of the FPGA hardware simulation environment.

[0090] In summary, this embodiment proposes a software simulation method for FPGA based on an electrochemical model. By running a hardware description language, an FPGA hardware simulation environment is obtained. The software code of the electrochemical model is then run to obtain multiple software result variables. The hardware code of the electrochemical model is then run in the FPGA hardware simulation environment to obtain multiple hardware result variables. These multiple software and hardware result variables are processed to determine the sensitive variables among them. Compared to related technologies that require manual execution of the electrochemical model multiple times on a hardware computing device to gain prior experience when designing a new hardware computing device that runs the electrochemical model, this method determines the sensitive variables in the hardware results by running the hardware code of the electrochemical model in the FPGA hardware simulation environment. This eliminates the need for multiple manual runs of the electrochemical model on the hardware computing device, shortening the development time of the electrochemical model hardware computing device and improving development efficiency.

[0091] Example 3

[0092] This embodiment proposes a computer-readable storage medium storing a computer program. When the computer program is run by a processor, it executes the steps of the FPGA software simulation method based on an electrochemical model described in Embodiment 1. For specific implementation details, please refer to Embodiment 1, which will not be repeated here.

[0093] In addition, see Figure 3 The diagram shows the structure of an electronic device. This embodiment also proposes an electronic device, which includes a bus 51, a processor 52, a transceiver 53, a bus interface 54, a memory 55, and a user interface 56. The electronic device includes a memory 55.

[0094] In this embodiment, the electronic device further includes: one or more programs stored in the memory 55 and executable on the processor 52, configured to be executed by the processor to perform the one or more programs for the following steps (1) to (3):

[0095] (1) Run the hardware description language to obtain the FPGA hardware simulation environment;

[0096] (2) Obtain the software code and hardware code of the electrochemical model, run the software code of the electrochemical model to obtain multiple software result variables of the electrochemical model, and run the hardware code of the electrochemical model in the FPGA hardware simulation environment to obtain multiple hardware result variables of the electrochemical model.

[0097] (3) Process the multiple software result variables and the multiple hardware result variables to determine the sensitive variables among the hardware result variables, and store the determined sensitive variables in the simulation file library.

[0098] Transceiver 53 is used to receive and send data under the control of processor 52.

[0099] The bus architecture (represented by bus 51) can include any number of interconnected buses and bridges, linking various circuits including one or more processors represented by processor 52 and memory represented by memory 55. Bus 51 can also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be further described in this embodiment. Bus interface 54 provides an interface between bus 51 and transceiver 53. Transceiver 53 can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. For example, transceiver 53 receives external data from other devices. Transceiver 53 is used to transmit data processed by processor 52 to other devices. Depending on the nature of the computing system, a user interface 56 may also be provided, such as a keypad, display, speaker, microphone, or joystick.

[0100] Processor 52 is responsible for managing bus 51 and general processing, such as running general-purpose operating system 551 as described above. Memory 55 can be used to store data used by processor 52 during operation.

[0101] Optionally, the processor 52 may be, but is not limited to, a central processing unit, a microcontroller, a microprocessor, or a programmable logic device.

[0102] It is understood that the memory 55 in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The memory 55 of the systems and methods described in this embodiment is intended to include, but is not limited to, these and any other suitable types of memory.

[0103] In some implementations, memory 55 stores elements such as executable modules or data structures, or subsets thereof, or extended sets thereof: operating system 551 and application programs 552.

[0104] The operating system 551 includes various system programs, such as the framework layer, core library layer, and driver layer, used to implement various basic business functions and handle hardware-based tasks. The application program 552 includes various applications, such as a media player and a browser, used to implement various application functions. Programs implementing the methods of the embodiments of this application can be included in the application program 552.

[0105] In summary, this embodiment proposes a computer-readable storage medium and electronic device. By running a hardware description language, an FPGA hardware simulation environment is obtained. The software code of an electrochemical model is run to obtain multiple software result variables of the electrochemical model. The hardware code of the electrochemical model is then run in the FPGA hardware simulation environment to obtain multiple hardware result variables. These multiple software and hardware result variables are processed to determine sensitive variables among the hardware result variables. Compared to related technologies that require manual execution of the electrochemical model multiple times in a hardware computing device to gain prior experience when designing a new hardware computing device to run the electrochemical model, this method of determining sensitive variables in the hardware results by running the hardware code of the electrochemical model in an FPGA hardware simulation environment eliminates the need for multiple manual runs of the electrochemical model in the hardware computing device. This shortens the development time of the hardware computing device for the electrochemical model and improves development efficiency.

[0106] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A software simulation method for FPGA based on an electrochemical model, characterized in that, include: Run the hardware description language to obtain the FPGA hardware simulation environment; Obtain the software and hardware code of the electrochemical model, run the software code of the electrochemical model to obtain multiple software result variables of the electrochemical model, and run the hardware code of the electrochemical model in the FPGA hardware simulation environment to obtain multiple hardware result variables of the electrochemical model. The multiple software result variables and the multiple hardware result variables are processed to determine the sensitive variables among the hardware result variables, and the determined sensitive variables are stored in the simulation file library; The process of processing the plurality of software result variables and the plurality of hardware result variables to determine the sensitive variables among the hardware result variables includes: Calculate the difference between the software result variables and the hardware result variables that have the same dimension among the plurality of software result variables and the plurality of hardware result variables; Among the plurality of hardware result variables, the hardware result variables whose difference from the software result variables is greater than a difference threshold are identified as sensitive variables; A distorted clock signal is input into the FPGA hardware simulation environment to interfere with the clock signal of the FPGA hardware simulation environment. The hardware code of the electrochemical model is run using the FPGA hardware simulation environment where the clock signal is interfered with, to obtain multiple hardware output variables of the electrochemical model; Calculate the difference between the software result variables and the hardware output variables that have the same dimension among the plurality of software result variables and the plurality of hardware output variables; Among the plurality of hardware output variables, the hardware output variables whose difference from the software result variables is greater than a difference threshold are identified as sensitive variables.

2. The method according to claim 1, characterized in that, The distorted clock signal includes: a triangular wave clock signal and a trapezoidal wave clock signal; The step of inputting a distorted clock signal into the FPGA hardware simulation environment to interfere with the clock signal of the FPGA hardware simulation environment includes: A triangular wave clock signal or a trapezoidal wave clock signal is input into the FPGA hardware simulation environment to interfere with the clock signal of the FPGA hardware simulation environment.

3. A software simulation device for FPGA based on an electrochemical model, characterized in that, include: The runtime module is used to run the hardware description language to obtain the FPGA hardware simulation environment; The first processing module is used to acquire the software code and hardware code of the electrochemical model, run the software code of the electrochemical model to obtain multiple software result variables of the electrochemical model, and run the hardware code of the electrochemical model in the FPGA hardware simulation environment to obtain multiple hardware result variables of the electrochemical model. The second processing module is used to process the plurality of software result variables and the plurality of hardware result variables, determine the sensitive variables among the hardware result variables, and store the determined sensitive variables in the simulation file library; The second processing module is specifically used for: Calculate the difference between the software result variables and the hardware result variables that have the same dimension among the plurality of software result variables and the plurality of hardware result variables; Among the plurality of hardware result variables, the hardware result variables whose difference from the software result variables is greater than a difference threshold are identified as sensitive variables; A distorted clock signal is input into the FPGA hardware simulation environment to interfere with the clock signal of the FPGA hardware simulation environment. The hardware code of the electrochemical model is run using the FPGA hardware simulation environment where the clock signal is interfered with, to obtain multiple hardware output variables of the electrochemical model; Calculate the difference between the software result variables and the hardware output variables that have the same dimension among the plurality of software result variables and the plurality of hardware output variables; Among the plurality of hardware output variables, the hardware output variables whose difference from the software result variables is greater than a difference threshold are identified as sensitive variables.

4. The apparatus according to claim 3, characterized in that, The distorted clock signal includes: a triangular wave clock signal and a trapezoidal wave clock signal; The second processing module is used to input a distorted clock signal into the FPGA hardware simulation environment to interfere with the clock signal of the FPGA hardware simulation environment, including: A triangular wave clock signal or a trapezoidal wave clock signal is input into the FPGA hardware simulation environment to interfere with the clock signal of the FPGA hardware simulation environment.

5. A computer-readable storage medium storing a computer program thereon, characterized in that, The computer program, when executed by a processor, performs the steps of the method described in any one of claims 1-2.

6. An electronic device, characterized in that, The electronic device includes a memory, a processor, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor of the steps of the method according to any one of claims 1-2.

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