Multi-modal physically unclonable functions as an entropy source to generate true random bits

Abstract

A circuit and related method of providing a true random and unclonable output from a circuit. In the circuit and method, an enable signal is received at a first port of a latch and a data input signal is received at a second port of the latch. An inverted signal of the output data of the latch is generated via an inverter coupled to the latch circuit. The inverted signal is fed into the second port and the latch circuit and inverter are operated to provide a true random and unclonable output.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a random number generation algorithm. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices, also known as data storage devices. The data storage device serves as either the main memory or auxiliary memory in the portable electronic device.

[0003] Data storage devices that use memory devices have excellent stability, durability, high data access speed, and low power consumption because they have no moving parts. Examples of data storage devices with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs).

[0004] An SSD may include a flash memory component and a controller, the controller including electronics that bridge the flash memory component to the SSD input / output (I / O) interface. The SSD controller may include an embedded processor running functional components such as firmware. SSD functional components are typically device-specific and, in most cases, updatable.

[0005] The two main types of flash memory are named after NAND and NOR logic gates. Individual flash memory cells exhibit internal characteristics similar to their corresponding gates. NAND flash memory can be written to and read from blocks (or pages), which are typically much smaller than the entire memory space. NAND flash memory primarily operates in memory cards, USB flash drives, solid-state drives (SSDs), and similar products for general data storage and transfer.

[0006] Modern NAND flash memory devices use different types of physical blocks, distinguished by the type of memory cells they contain. Physical blocks can include (i) single-level cells (SLC), each capable of storing one bit; (ii) multi-level cells (MLC), each capable of storing two bits; (iii) triple-level cells (TLC), each capable of storing three bits; or (iv) quad-level cells (QLC), each capable of storing four bits. Memory cells within a given block are grouped to define pages. To increase overall storage capacity, the trend is to implement NAND flash memory devices with higher capacity memory cells, i.e., from SLC to MLC to TLC to QLC. However, this leads to reliability issues.

[0007] Physically unclonable functions (PUFs) can be used for a variety of purposes, including security. Typically, semiconductor chips are used to implement PUFs due to manufacturing variations. Even with precise manufacturing processes, the random noise generated by the manufactured semiconductor chip is virtually impossible to replicate, thus providing a reliable physically unclonable function for generating unclonable outputs.

[0008] As described in U.S. Patent Application Publication No. 2021 / 0055912 (the entire contents of which are incorporated herein by reference), Physically Unclonable Functions (PUFs) are widely used as hardware primitives for unique integrated circuit identification and True Random Number Generation (TRNG).

[0009] As described in U.S. Patent No. 9,201,630 (the entire contents of which are incorporated herein by reference), non-volatile mass storage memory drives present various security issues when used to store sensitive data. To prevent these security issues, some drives automatically encrypt data when storing it.

[0010] As detailed in patent 9,201,630, the generated random numbers can be used as part of a cryptographic algorithm. For example, some cryptographic algorithms rely on unpredictable data. To achieve this unpredictability, some cryptographic algorithms may require a stable supply of random numbers. The strength of such a cryptographic algorithm is typically only about as good as the random number generation process itself.

[0011] More specifically, random numbers can be used to generate encryption keys, which are then used to provide encrypted secure communication. Many cryptographic algorithms use random numbers (numbers used only once). Hard disk drives have several sources of physical entropy that can be used to initialize a cryptographic random number generator or to generate a seed for it. Many of these sources of physical entropy originate from the mechanical movement of the disk drive components. The entropy of such physical sources provides a degree of confidence that the generated random numbers are truly random.

[0012] In practice, True Random Number Generators (TRNGs) are used in a wide range of applications, such as cryptography, statistical sampling, simulation, and computer games. The main advantage of TRNGs compared to Pseudo-Random Number Generators (PRNGs) lies in the uniqueness and unpredictability of their generated output values.

[0013] TRNGs are devices or parts of devices that generate random numbers based on certain inherent physical processes. One possible method for extracting random data from electronic devices involves a physically unclonable function (PUF). PUFs are commonly used for stable key and random number generation. Summary of the Invention

[0014] In one aspect of the invention, a latch circuit is provided. The latch circuit has a latch including a first input port, a second input port, and an output port. The latch is configured to receive an enable signal at the first input port. The latch circuit has an inverter connected to the latch, configured to generate an inverted signal of data output from the latch, and configured to provide the inverted signal back to the second input port. When the enable signal has a first level, the latch and inverter operate as a memory; when the enable signal has a second level, the latch and inverter operate as a ring oscillator; and when the enable signal changes from the second level to the first level, the latch and inverter may have a metastable state.

[0015] In another aspect of the invention, there is a method for providing an unclonable output from a circuit. The method receives an enable signal at a first port of a latch, receives a data input signal at a second port of the latch, generates an inverted signal of the output data from the latch via an inverter connected to the latch circuit, sends the inverted signal to the second port, and operates the latch circuit and the inverter to provide an unclonable output.

[0016] Other aspects of the invention will become apparent from the following description. Attached Figure Description

[0017] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the present invention.

[0018] Figure 2 This is a block diagram illustrating a memory system according to another embodiment of the present invention.

[0019] Figure 3 This is a circuit diagram illustrating a memory block of a memory device according to yet another embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of a PUF circuit according to an embodiment of the present invention.

[0021] Figure 5 This is a diagram depicting a D-type (ROLD) circuit of a ring oscillator and latch according to an embodiment of the present invention.

[0022] Figure 6 yes Figure 5 A diagram depicting the equivalent circuit of the ROLD circuit.

[0023] Figure 7 yes Figure 5 A diagram depicting the equivalent bistable element circuit of the ROLD circuit.

[0024] Figure 8 yes Figure 5A diagram depicting another equivalent circuit of the ROLD circuit.

[0025] Figure 9 This is a diagram depicting the equivalent ROLD circuit.

[0026] Figure 10A This is a diagram showing the SR latch timing as it varies with the EN signal.

[0027] Figure 10B This is a diagram depicting a scenario used to generate metastable values.

[0028] Figure 10C This is a depiction of another scenario used to generate metastable values.

[0029] Figure 11 It is a diagram of a multi-bit latch used to store a unique ID or random value generated by a PUF circuit.

[0030] Figure 12 This is a graph showing the probabilities of '0' and '1' values ​​in the initialization mode of the PUF circuit.

[0031] Figure 13 It is a graph depicting the observed frequencies in the RO mode of the ring oscillator of the PUF circuit.

[0032] Figure 14 This is a graph showing the probabilities of '0' and '1' values ​​in the metastable mode of the PUF circuit.

[0033] Figure 15 It is a graph showing the distribution of 128-bit random values ​​generated by the PUF circuit.

[0034] Figure 16 This is a diagram illustrating a method for providing an unclonable output from a circuit according to another embodiment of the present invention. Detailed Implementation

[0035] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will convey the scope of the invention to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. The term “embodiment” as used herein does not necessarily refer to all embodiments. Throughout this disclosure, the same reference numerals refer to the same parts in the drawings and embodiments of the invention.

[0036] This invention can be embodied in a variety of ways, including as a process; an apparatus; a system; a component of a computer program product embodied on a computer-readable storage medium; and / or a processor, such as a processor adapted to execute instructions stored on and / or provided by memory linked to the processor. In this specification, these embodiments or any other form in which the invention may be adopted can be referred to as technology. Generally, the order of operation of the disclosed processes can be varied within the scope of this invention. Unless otherwise stated, components such as processors or memory described as suitable for performing tasks can be implemented as general-purpose means or circuit components configured or otherwise programmed to perform tasks at a given time, or as specific means or circuit components manufactured to perform tasks. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores adapted to process data such as computer program instructions.

[0037] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or those other than those described herein. Because the algorithms that form the basis of the methods (or the operation of the computer, processor, controller, or other signal processing device) are described herein, the code or instructions for implementing the operations of the method embodiments can convert a computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods herein.

[0038] If implemented at least in part as software, the controller, processor, device, module, unit, multiplexer, generator, logic circuit, interface, decoder, driver, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing, for example, code or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device.

[0039] The following provides a detailed description of embodiments of the present invention, along with accompanying drawings illustrating various aspects of the invention. The invention is described in conjunction with these embodiments, but is not limited to any specific embodiment. The invention includes many alternatives, modifications, and equivalents. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes; the invention may be practiced without some or all of these specific details, as described in the claims. For clarity, known technical materials in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0040] Figure 1This is a block diagram schematically illustrating a memory system according to an embodiment of the present invention.

[0041] Reference Figure 1 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200, which may represent more than one such device. Generally, the invention can be implemented as part of any digital hardware system. In various embodiments, the semiconductor memory device 200 is preferably a flash memory device, particularly MLC, TLC, and / or QLC NAND type. For simplicity, the semiconductor memory device 200 is sometimes simply referred to as memory device 200 or NAND flash memory 200.

[0042] The memory controller 100 can control the overall operation of the semiconductor memory device 200.

[0043] The semiconductor memory device 200 can perform one or more erase, program, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output (I / O) lines. The semiconductor memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. The control signals (CTRL) may include command latch enable signals, address latch enable signals, chip enable signals, write enable signals, and read enable signals, etc.

[0044] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device such as a solid-state drive (SSD). The SSD may include a storage device for storing data therein. When the semiconductor memory system 10 is used with an SSD, the operating speed of a host (not shown) connected to the memory system 10 can be significantly improved.

[0045] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device, such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated to configure PC cards, Compact Flash (CF) cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC), Reduced Size Multimedia Cards (RS-MMC), Micro Size Versions of MMC (Micro MMC), Secure Digital (SD) cards, Mini Secure Digital (Mini SD) cards, Micro Secure Digital (Micro SD) cards, Secure Digital Mass Capacity (SDHC) cards, and / or Universal Flash Memory (UFS) cards, in accordance with the Personal Computer Memory Card International Association (PCMCIA).

[0046] In another embodiment, the memory system 10 may be configured as one of a variety of components in electronic devices such as: a computer, an ultra-mobile PC (UMPC), a workstation, a netbook computer, a personal digital assistant (PDA), a portable computer, a network tablet PC, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable gaming device, a navigation device, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a storage device for a data center, a device capable of receiving and transmitting information in a wireless environment, a radio frequency identification (RFID) device, and one of a variety of electronic devices in a home network, one of a variety of electronic devices in a computer network, one of a variety of electronic devices in a telematics network, or one of a variety of components in a computing system.

[0047] Figure 2 This is a detailed block diagram illustrating a memory system according to an embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 shown.

[0048] Reference Figure 2 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can operate in response to a request from a host device, and in particular, stores data to be accessed by the host device.

[0049] The host device can be implemented using any of a variety of electronic devices. In some embodiments, the host device may include electronic devices such as: desktop computers, workstations, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, and / or digital video recorders and digital video players. In some embodiments, the host device may include portable electronic devices such as: mobile phones, smartphones, e-book readers, MP3 players, portable multimedia players (PMPs), and / or portable game consoles.

[0050] The memory device 200 can store data to be accessed by the host device.

[0051] The memory device 200 may be implemented using volatile memory devices (such as dynamic random access memory (DRAM) and / or static random access memory (SRAM)) or non-volatile memory devices (such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM)).

[0052] The controller 100 can control the storage of data in the memory device 200. For example, the controller 100 can control the memory device 200 in response to a request from a host device. The controller 100 can provide the host device with data read from the memory device 200, and can store data provided by the host device into the memory device 200.

[0053] The controller 100 may include a storage device 110 connected via a bus 160, a control component 120 which may be implemented as a processor such as a central processing unit (CPU), an error correction code (ECC) component 130, a scrambler 170, a host interface (I / F) 140, and a memory interface (I / F) 150.

[0054] Storage device 110 can be used as working memory for memory system 10 and controller 100, and stores data for driving memory system 10 and controller 100. When controller 100 controls the operation of memory device 200, storage device 110 can store data for operations such as read operations, write operations, programming operations and erase operations performed by controller 100 and memory device 200.

[0055] Storage device 110 may be implemented using volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage device 110 may store data used by the host device in storage device 200 for read and write operations. For storing data, storage device 110 may include program memory, data memory, write buffers, read buffers, mapping buffers, etc. Storage device 110 may also include register 115 used as described below.

[0056] Control component 120 can control the general operation of memory system 10 and control write or read operations of memory device 200 in response to write or read requests from host device. Control component 120 can drive firmware called flash translation layer (FTL) 125 to control the general operation of memory system 10. For example, FTL 125 can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection (GC), and / or bad block handling. FTL 125 can be implemented as firmware in control component 120 or controller 100. L2P mapping is called logical block addressing (LBA).

[0057] ECC component 130 can detect and correct errors in data read from memory device 200 during a read operation. When the number of error bits is greater than or equal to the threshold number of correctable error bits, ECC component 130 may not correct the error bits, but instead may output an error correction failure signal indicating that the correction of error bits has failed.

[0058] ECC component 130 can perform error correction operations based on coded modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbine codes, turbine product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). ECC component 130 may include any and all circuitry, systems, or devices used for appropriate error correction operations.

[0059] Scrambler 170 can be used to uniformly distribute bits in data before it is stored in memory device 200. This helps increase the reliability of memory device 200 and reduce loss effects. Scrambler 170 can be implemented based on a linear feedback shift register (LFSR). Alternatively, scrambler 170 can be implemented in any other suitable manner.

[0060] The host interface 140 can communicate with the host device through one or more of the following interface protocols: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0061] Memory interface 150 can provide an interface between controller 100 and memory device 200, allowing controller 100 to control memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for memory device 200 and process data under the control of control components or CPU 120. When memory device 200 is flash memory such as NAND flash memory, memory interface 150 can generate memory control signals and process data under the control of CPU 120.

[0062] Memory device 200 may include memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer 250 (which may be in the form of a page buffer array), column decoder 260, and input / output circuitry 270. Memory cell array 210 may include multiple memory blocks 211 for storing data. Subsets of memory blocks may be grouped into corresponding superblocks (SBs) for certain operations.

[0063] Voltage generation circuit 230, row decoder 240, page buffer 250, column decoder 260, and input / output circuit 270 can form the peripheral circuitry of memory cell array 210. The peripheral circuitry can perform programming, reading, or erasing operations on memory cell array 210. Control circuit 220 can control the peripheral circuitry.

[0064] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0065] The row decoder 240 can be electrically connected to the voltage generation circuit 230 and a plurality of memory blocks 211. The row decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to the row address RADD generated by the control circuit 220, and transfer the operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0066] Page buffer 250 can communicate electrically with memory cell array 210 via bit line BL. Figure 3 (As shown). The page buffer 250 can precharge the bit line BL with a positive voltage in response to the page buffer control signal generated by the control circuit 220, and transfer data to and from the selected memory block during programming and reading operations, or temporarily store the transferred data.

[0067] The column decoder 260 can transmit data to and receive data from the page buffer 250, and can also exchange data with the input / output circuitry 270.

[0068] Input / output circuit 270 can transmit commands and addresses received from external devices (e.g., memory controller 100) to control circuit 220, transmit data from external devices to column decoder 260, or output data from column decoder 260 to external devices.

[0069] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0070] Figure 3 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present invention. For example, Figure 3 The storage block can be Figure 2 Any one of the storage blocks 211 in the memory cell array 200 shown.

[0071] Reference Figure 3 The exemplary storage block 211 may include multiple word lines WL0 to WLn-1, a drain select line DSL, and a source select line SSL connected to the line decoder 240. These lines may be arranged in parallel, with multiple word lines between DSL and SSL.

[0072] The exemplary memory block 211 may further include multiple cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each cell string may include one or more drain select transistors (DSTs) and one or more source select transistors (SSTs). In the illustrated embodiment, each cell string has one DST and one SST. Within the cell string, multiple memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the select transistors DST and SST. Each of the memory cells may be configured as a single-layer cell (SLC), multi-layer cell (MLC), three-layer cell (TLC), four-layer cell (QLC), or more layers for storing data information.

[0073] The source of each SST in a cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of each SST in a cell string can be connected to SSL, and the gate of each DST in a cell string can be connected to DSL. The gate of each memory cell in the cell string can be connected to the corresponding word line. That is, the gate of memory cell MC0 is connected to the corresponding word line WL0, the gate of memory cell MC1 is connected to the corresponding word line WL1, and so on. A group of memory cells connected to a specific word line can be called a physical page. Therefore, the number of physical pages in memory block 211 can correspond to the number of word lines.

[0074] As previously described, page buffer 250 can be in the form of a page buffer array, which includes multiple page buffers 251 connected to bit lines BL0 to BLm-1. Page buffers 251 can operate in response to page buffer control signals. For example, page buffers 251 can temporarily store data received through bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines during read or verification operations.

[0075] While the present invention can be implemented as part of any digital hardware system as described above, memory block 211 may include NAND or NOR flash memory cells of a specific capacity. Memory cell array 210 may also be implemented as a hybrid flash memory combining two or more types of memory cells, or as a single NAND flash memory with the controller embedded within the memory chip. Memory block 211 comprising larger capacity NAND flash memory cells (e.g., NAND MLC, NAND TLC, NAND QLC) is particularly suitable for the present invention.

[0076] As previously mentioned, increasing the capacity of memory cells used to implement NAND flash memory 200 can cause reliability issues. As described in the '912 publication mentioned above, this drawback can be used for the opposite purpose: faults in blocks and pages can be used as the sole source of chip identification and true random number generation (TRNG). Modern MLC, TLC, and QLC NAND flash memory devices 200 tend to have numerous ECC engines, which mitigate the effects of inherent NAND instability.

[0077] Hardware Design In one embodiment of the invention, the physically unclonable function circuit (referred to herein as the "PUF circuit") is based on the use of an inverter and a D-latch controlled by an enable (EN) signal. In one aspect of the invention, the PUF circuit requires hardware to generate noise and is not entirely implemented in software. While software can be used to control the circuit, it does not generate random numbers. The PUF circuit can operate in four modes: initial memory mode, ring oscillator mode, metastable mode, and latch mode. These modes will be described in more detail below. All of these modes can be used for different purposes, such as generating unique identifiers in initial memory mode, generating random numbers in ring oscillator or metastable mode, and storing generated IDs or random values ​​in latch mode.

[0078] Therefore, the PUF circuit of this invention supports different PUF routines in a single device. One of the main challenges of TRNG design is area consumption and performance (random bit generation rate). The PUF circuit of this invention provides a TRNG design that is compact because it consumes the area of ​​only four logic gates and is as fast as a ring oscillator, thus allowing operation at high frequencies, such as, but not limited to, [missing information]. Figure 13 The operation is shown at frequencies ranging from 250MHz to 400MHz.

[0079] Figure 4 This is a depiction of a PUF circuit according to an embodiment of the present invention. Here, in one embodiment of the invention, a PUF circuit is provided that serves as an entropy source (i.e., a physical source of noise in a true random number generator) for random bit generation. This circuit has the two elements described above: a D-type latch (LD) and an inverter INV. D-type latch circuits are known in the art, as illustrated in U.S. Patents Nos. 5410550, 5903175, 6414529, and 7872514 (the entire contents of each patent are incorporated herein by reference). Typically, a D-type latch is an electronic device capable of storing one bit of information; that is, it can capture or “latch”, for example, a logic level appearing on the data line input D when the enable signal is high. The D-type latch is an asynchronous device. If the data on the D line changes state when the enable pulse is high, then Q is output, followed by input D. When the enable input is low, the last state of the D input is captured and held in the D-type latch.

[0080] like Figure 4 As shown, in the PUF circuit of this invention, there is an inverter INV connected to the output Q of the latch LD. The inverter forms a negative feedback loop that returns the signal to the input D of the latch LD. An enable signal EN is provided to the input E of the latch LD. The operation of the PUF circuit is controlled by the enable signal EN. The enable signal can be controlled by control component 120 and / or control circuit 220 ( Figure 2 Provided by (as shown), or by, for example Figure 4 The dedicated controller 402 shown is provided.

[0081] As described above, the PUF circuit of the present invention supports four operating modes: Initial memory. This mode is designed for use during startup and when EN='0'. In this mode, the PUF circuit operates similarly to static random access memory (SRAM): data bits can be retained as long as power is supplied. In this mode, the latch LD can generate a stable '0', a stable '1', or a metastable value. Other (evaluation of SRAM behavior) indicates that the output Q has a 10% chance of generating a metastable value. When the output Q can be output stably (as in the PUF circuit of this invention), the output Q can be used as a bit for a unique device ID.

[0082] Ring oscillator (RO). If the enable signal remains EN='1' over time, the PUF circuit generates a ring oscillator with a unique frequency F. Q The curved flow signal, the unique frequency F Q It can be used for random bit generation and operates similarly to a ring oscillator (RO PUF). For example, a clock signal with a meandering shape will cause the signal level to change from high to low (e.g., periodically) or from low to high (e.g., periodically) while the frequency remains substantially the same.

[0083] Metastability. Because the latch LD is asynchronous and the values ​​on the latch's data input (D) are unpredictable, changing the EN signal value from '1' to '0' will interfere with the timing parameters of the latch LD. In this case, the latch LD can enter a metastable state, and the output Q can be '0' or '1' over time.

[0084] Latching. If the enable signal remains at EN='0' over time, the latch LD can store random bits received from the input D, and the output Q value is stable.

[0085] Therefore, the PUF circuit of the present invention can be used to generate a unique stable ID bit (mode 1) or a random value (modes 2 and 3) or to store the generated ID or random bit (mode 4).

[0086] Figure 5 This is a diagram depicting a type D (ROLD) circuit of a ring oscillator and latch according to an embodiment of the present invention. More specifically, Figure 5 Describes the use of Figure 4 The gate level of the entropy source circuit of the PUF circuit. Figure 5 The circuit shown is a combination of different circuits, namely a combination of a ring oscillator and a type D latch.

[0087] Figure 5 The D-latch assembly depicted includes a basic SR-latch circuit with S (set) and R (reset) inputs and two complementary data outputs Q. SR and nQ SRFor SR-latch configurations with NOR2 gates (e.g., Figure 5 The following operating modes are available for the NOR1 and NOR2 cases shown: Set to '1' (when S='1' and R='0'). Reset '0' (when S='0' and R='1'). Stored value mode (when S='0' and R='0') and Forbidden mode (when S='1' and R='1').

[0088] The transition from prohibited mode to stored value mode can be achieved in the output Q. SR and nQ SR Metastable values ​​are generated. D-type latches (such as...) Figure 5 (As shown) is configured with an SR latch to prevent the inhibit mode from occurring by keeping the S and R inputs to their opposite values. The stored mode is determined by an additional EN input to the enable signal and two additional AND2 gates (e.g., Figure 5 (AND1 and AND2) are provided.

[0089] The following describes the "equivalent circuit" operating during the four modes described above: Initial memory When EN='0' Figure 5 The circuit is equivalent to an SR-latch in storage mode (S='0', R='0'). Figure 6 yes Figure 5 The equivalent circuit diagram of the ROLD circuit is shown, where EN = '0'.

[0090] In this mode, the AND elements (AND1 and AND2) generate a constant '0' value and can be omitted for circuit analysis. The NOR elements (NOR1 and NOR2) operate as inverters. Therefore, the circuit in this mode operates as a bistable circuit, as shown below. Figure 7 As shown.

[0091] During the initialization (power-on) phase, due to differences in manufacturing processes (NOR gates NOR1 and NOR2 and the connections between them may be asymmetrical), the default value v (the output of the PUF circuit) is unknown. Therefore, a unique ID value can be obtained from this PUF circuit during power-on, similar to what is seen when an SRAM cell, which can also be considered a bistable element, is powered on.

[0092] Ring oscillator (RO) When EN='1', the SR-latch switches between setting (S='1', R='0') and reset (S='0', R='1') modes based on the value obtained from the inverter INV output, such as... Figure 8 As shown. Figure 8 yes Figure 5 The equivalent circuit diagram of the ROLD circuit is shown, where EN = '1'.

[0093] In this mode, the AND1 element acts as a repeating v or The value buffer operates, with the NOR2 element functioning as a constant '0' value generator, and AND2 and NOR1 functioning as two inverters. This operating mode is equivalent to a ring oscillator circuit with three inverters, such as... Figure 9 As shown.

[0094] Therefore, it has a unique frequency F Q The meandering signal (v→) →v→……) appears on the output Q of the PUF circuit. F Q This is determined by differences in manufacturing processes that cause unpredictable delays in the negative feedback loop.

[0095] Metastable state Figure 10A The timing diagram shows three output values ​​y0, y1, and y2 from the output Q. There are two possible ways in which metastability can occur on the output Q. First, the initial value y0... {v,X, (The time period is from t0 to t1, such as...) Figure 10A (As shown) can be a stable v {0,1}, stable {1,0} or metastable (X). In this case, metastable refers to a value with unknown stability, i.e., the output Q occasionally exhibits a value of '0' or '1' with different non-zero probabilities. The second case is more complex because, in addition to the three values ​​{v, X, ...} in the first case, ... In addition to this, it is also based on the SR-latch phenomenon that causes high-frequency oscillations. When inputs S and R are both input with a value of '1' (inhibited state) for a short period of time, and the EN signal changes from '1' to '0', the SR latch is attempting to store the inhibited state, thus generating damped high-frequency oscillations. The metastable oscillations also transition to a stable value of '0' or a stable value of '1' after a period of time. Therefore, the values ​​y1 (from t2 to t3) and y2 (after t4) will eventually become stable values ​​of '0' or stable values ​​of '1', with or without metastable oscillations. This phenomenon is based on the unique voltage and timing characteristics of the SR latch and can only be determined after manufacturing.

[0096] Figure 10B and Figure 10C Two scenarios are shown that generate metastable values. The possible values ​​in the first case are... Figure 10B The diagram shows the possible values ​​in the second case. Figure 10C As shown in [the image]. Figure 10B In the first case, the output value y0 initially transforms into a stable value v or Or, in the process of transforming into a stable value v or Previously, it could transform into a metastable state X. In Figure 10C In the second case, the output values ​​y1 and y2 initially transform into stable values ​​v and It may either transform into a metastable state X, or into a high-frequency oscillation mode. The high-frequency oscillation mode then transforms into a metastable state X. All states eventually transform into a stable value v or Therefore, although the oscillation in the second case eventually decays to a value v or However, compared to the first case, the final value Q is more uncertain. Therefore, the transition of the EN signal from '1' (ring oscillator mode) to '0' (latch mode) can lead to high-frequency oscillations, resulting in metastability observed in the output Q. Thus, metastability can be used to generate truly random numbers.

[0097] latch Figure 11 This is a diagram of a multi-bit latch used to store unique IDs or random values. When the EN signal is set to a value of "0", it allows the storage of random values ​​generated after initialization or after oscillations caused by ring oscillations or metastability. Figure 11 The circuit shown is used to store an N-bit unique ID (mode 1) or a random number (mode 2 or 3).

[0098] In one embodiment of the present invention, Figure 11 The PUF circuit shown provides an entropy source, which can be used to generate unique bits or to store generated data.

[0099] Work operation example Figure 11 The entropy source has been implemented in a Xilinx Artix-7 field-programmable gate array (FPGA) and features for each mode have been collected.

[0100] Initial memory A total of 128 entropy sources have been synthesized and implemented in the FPGA. Figure 12 This is a graph showing the probabilities of the '0' and '1' values ​​in the initialization mode. During the E=100 test (where each PUF circuit acting as an entropy source was tested 100 times), the probability of each element in the entropy source generating a result output of "1" is... Figure 12 The values ​​shown.

[0101] like Figure 12 As shown, the probability distribution for generating the value '1' is... )as follows: =0.0 has 61 elements. =1.0 has 56 elements, 0 < < 1 has 11 elements. Therefore, the PUF circuit of the present invention can be used as an entropy source to generate a reliable, unique, and reproducible ID, where the probability distribution represents the unique ID of a set of 128 PUF circuits implemented in a single FPGA chip. In one embodiment, all circuits will be located in a single FPGA chip.

[0102] Ring oscillator Figure 13 This is a graph depicting the frequencies observed in the ring oscillator RO mode of the aforementioned 128 generators. The 128 generators are described and tested in ring oscillator mode and are shown to illustrate the generated frequency values ​​F. Q Uniqueness. The simulated (or target) frequency is 350MHz. Figure 10A The horizontal line in the image is at the 350MHz y-axis value, and Figure 13 The table shows the estimated frequency values ​​(F) of each of the 128 PUF circuits that act as entropy sources. i ). Figure 13 The frequency value F of each of the 128 PUF circuits operating in RO mode is shown. Q Each source of entropy is unique and unpredictable.

[0103] Metastable state In metastable mode, the same 128 entropy sources were tested E=100 times (EN switched from '1' to '0' after k=32 system clock cycles). Figure 14 This shows the probability that each element will generate a '1' value after k system clock cycles in RO mode (EN='1'). .

[0104] Compared to the initialization mode, the metastable mode produces values ​​with lower reproducibility because all probabilities of generating a '1' value ( The values ​​are all above 0.2 and below 0.8. Therefore, this pattern is more suitable for generating truly random values. For example, if the output probability is neither '0' nor '1', the output will be unpredictable. Unpredictability (irreproducibility) is an important characteristic of generating truly random values.

[0105] latch To estimate the quality of the random values ​​generated by the PUF circuit, which acts as an entropy source, 128 elements were used. Therefore, one million 128-bit values ​​were generated by changing the EN signal from '1' to '0'. The duration of the EN signal in the '1' state is k = 32 system clock cycles. Figure 15The distribution of the generated 128-bit values ​​is shown. The generated values ​​are truly random, but not uniformly distributed. Therefore, to achieve the desired randomness, the random sequence can be post-processed (or otherwise adjusted).

[0106] Figure 16 This is a diagram illustrating a method for providing an unclonable output from a circuit according to another embodiment of the present invention. Figure 16 As depicted, at 1601, an enable signal is received at the first port of the latch. At 1603, a data input signal is received at the second port of the latch. At 1605, an inverted signal of the output data from the latch is generated via an inverter connected to the latch circuit. At 1607, the inverted signal is fed into the second port. At 1609, the latch circuit and the inverter are operated to provide a non-cloning output.

[0107] In this method, the latch and inverter can operate as a memory when the enable signal has a first level, as a ring oscillator when the enable signal has a second level, and can be metastable when the enable signal changes from the second level to the first level. Operating the latch and inverter as a ring oscillator or in a metastable state provides a random number output. The random number output includes physically unclonable random numbers. Operating the latch and inverter as a memory during circuit initialization provides an identification pattern as a device identifier for the circuit.

[0108] In this method, there can be multiple latches and inverters, and the method can provide a set of probabilities for the non-cloning output related to the probability that a single latch-inverter combination of multiple latches and inverters stores the value '0' or '1' during circuit initialization.

[0109] In this method, there can be multiple latches and inverters, and when multiple latches and inverters are operating as a ring oscillator, the method can provide a set of frequencies for a single latch-inverter combination of multiple latches and inverters for an unclonable output.

[0110] In this method, there can be multiple latches and inverters, and when multiple latches and inverters are operating in a metastable state, the method can provide a set of frequencies for a single latch-inverter combination of multiple latches and inverters for an unclonable output.

[0111] In one embodiment of the invention, as shown in the figure above, a latch circuit is provided. The latch circuit has a latch including a first input port, a second input port, and an output port. The latch is configured to receive an enable signal at the first input port. The latch circuit has an inverter connected to the latch, configured to generate an inverted signal of data output from the latch, and configured to provide the inverted signal back to the second input port. The latch and inverter operate as a memory when the enable signal has a first level, operate as a ring oscillator when the enable signal has a second level, and exhibit metastability when the enable signal changes from the second level to the first level.

[0112] In one embodiment, the latch circuitry further includes a controller configured to provide an enable signal to the latch.

[0113] In one embodiment, the controller is configured to provide an enable signal of one of a first level and a second level. In another embodiment, the controller is configured to change the enable signal from the first level to the second level, and the controller is also configured to change the enable signal from the second level to the first level.

[0114] In one embodiment, the latch (operating as a ring oscillator) outputs a physically non-clonable random number for randomized data. Optionally, the latch (operating in a metastable state) outputs a physically non-clonable random number for randomized data. Optionally, the latch (operating as a memory device during circuit initialization) outputs an identification pattern as a device identifier for the circuit.

[0115] In one embodiment, the latch includes a set-reset latch having a first NOR gate, a second NOR gate, a set input for the first NOR gate, a reset input for the second NOR gate, a first data output of the first NOR gate connected to the second NOR gate, and a second data output of the second NOR gate provided to an inverter. The latch may further include: a first AND gate connected to the set input of the first NOR gate; and a second AND gate connected to the reset input of the second NOR gate. In this embodiment, the inverter is configured to receive the second data output of the second NOR gate, invert the second data output, and provide the inverted second data output to the first AND gate and the second AND gate.

[0116] In another embodiment of the invention, a memory system is provided, comprising a semiconductor memory device having control circuitry and latching circuitry. The latching circuitry includes a latch having a first input port, a second input port, and an output port, the latch being configured to receive an enable signal at the first input port. The latching circuitry also includes an inverter coupled to the latch, configured to generate an inverted signal of data output from the latch, and configured to provide the inverted signal back to the second input port. In this embodiment, the controller is configured to operate the latching circuitry as a ring oscillator for generating random numbers or as a memory for storing data.

[0117] In this memory system, the latch circuit includes a set-reset latch having a first NOR gate, a second NOR gate, a set input for the first NOR gate, a reset input for the second NOR gate, a first data output of the first NOR gate connected to the second NOR gate, and a second data output of the second NOR gate provided to an inverter. In this memory system, the latch circuit also includes: a first AND gate connected to the set input of the first NOR gate; and a second AND gate connected to the reset input of the second NOR gate.

[0118] Although the foregoing embodiments have been shown and described in considerable detail for clarity and ease of understanding, the invention is not limited to the details provided. Those skilled in the art will understand from the foregoing disclosure that many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are illustrative and not restrictive. The invention is intended to include all modifications and alternatives to the disclosed embodiments. Furthermore, the disclosed embodiments can be combined to form other embodiments.

[0119] In fact, embodiments of the subject matter and functional operation described in this patent document can be implemented in various systems, digital electronic circuits, or in computer software, firmware, or hardware including the structures disclosed in this specification and their equivalents, or in combinations thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer-readable medium for execution by a data processing device or for controlling the operation of a data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composite of substances affecting machine-readable propagation signals, or combinations thereof. The terms "data processing unit" or "data processing device" encompass all devices, apparatuses, and machines for processing data, including, for example, programmable processors, computers, or multiple processors or computers. In addition to hardware, the device may also include code that creates an operating environment for the computer program in discussion, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, or combinations thereof.

[0120] Computer programs (also known as programs, software, software applications, scripts, or code) can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as standalone programs or as modules, components, subroutines, or other units suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored as part of a file containing other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinating files (e.g., a file storing parts of one or more modules, subroutines, or code). Computer programs can be deployed to run on a single computer, located in one place, or distributed across multiple computers interconnected by a communications network.

[0121] The processes and logic flows described in this specification can be executed by one or more programmable processors that run one or more computer programs to perform functions by manipulating input data and generating output. The processes and logic flows can also be executed by dedicated logic circuitry, and the device can also be implemented as dedicated logic circuitry, such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit).

[0122] Processors suitable for running computer programs include, for example, general-purpose and special-purpose microprocessors, and any one or more processors in any type of digital computer. Typically, a processor receives instructions and data from read-only memory or random access memory, or both. The fundamental components of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer also includes one or more mass storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks) for storing data, or is operatively coupled to receive data from or send data to the aforementioned mass storage devices, or both. However, a computer does not need to have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices. The processor and memory may be supplemented by or incorporated into dedicated logic circuitry.

[0123] Although this patent document includes numerous details, these details should not be construed as limiting the scope of any invention or potentially claimed protection, but rather as a description of features that may be specific to particular embodiments of a particular invention. Certain features described in the context of different embodiments in this patent document may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Furthermore, although these features may be described above as functioning in certain combinations, in some cases, one or more features may be removed from the combination, and the combination may then refer to a sub-combination or a variation of the sub-combination.

[0124] Similarly, although operations are described in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order or sequential order shown, or to perform all of the shown operations to achieve the desired result. Furthermore, the separation of various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

[0125] Only some implementation schemes and examples are described, and other implementation schemes, enhancements and variations can be derived based on the content described and shown in this patent document.

Claims

1. A latching circuit, comprising: A latch, the latch including a first input port, a second input port and an output port, the latch receiving an enable signal at the first input port; as well as An inverter, connected to the latch, generates an inverted signal of the data output from the latch and provides the inverted signal back to the second input port. When the enable signal has a first level, the latch and the inverter operate as a memory; when the enable signal has a second level, the latch and the inverter operate as a ring oscillator; and when the enable signal changes from the second level to the first level, the latch and the inverter are in a metastable state. The latch includes: A first NOR gate and a second NOR gate are connected in series. The first NOR gate has an output connected through the inverter. The inverter generates the inverted signal based on the output data of the first NOR gate. A first AND gate and a second AND gate, the second AND gate being connected in parallel with the first AND gate, each of the first AND gate and the second AND gate receiving both a) the enable signal and b) the inverted signal from the inverter, the inverted signal from the inverter being spun out and directly applied to the first AND gate and the second AND gate; The first AND gate provides input to the output of the second NOR gate; and The second AND gate provides input to the output of the first NOR gate.

2. The latch circuit according to claim 1, further comprising a controller, the controller providing the enable signal to the latch.

3. The latching circuit of claim 2, wherein the controller provides the enable signal of one of the first level and the second level.

4. The latching circuit according to claim 2, wherein... The controller changes the enable signal from the first level to the second level, and The controller changes the enable signal from the second level to the first level.

5. The latch circuit of claim 1, wherein the latch, operating as the ring oscillator, outputs a physically unclonable random number for the randomized data.

6. The latch circuit of claim 1, wherein the latch operating in the metastable state outputs a physically unclonable random number for the randomized data.

7. The latch circuit of claim 1, wherein during initialization of the latch circuit, the latch operating as the memory provides an identification mode as a device identifier of the latch circuit.

8. The latch circuit according to claim 1, wherein the latch includes a set-reset latch, the set-reset latch having a first NOR gate and a second NOR gate, the first NOR gate having a reset input, and the second NOR gate having a set input. The first data output of the first NOR gate is connected to the second NOR gate, and the second data output of the first NOR gate is provided to the inverter.

9. The latching circuit according to claim 8, wherein, The first AND gate is connected to the setting input of the second NOR gate, and The second AND gate is connected to the reset input of the first NOR gate.

10. The latch circuit of claim 9, wherein the inverter receives the second data output of the first NOR gate, inverts the second data output, and provides the inverted second data output to the first AND gate and the second AND gate.

11. A method for providing an unclonable output from a circuit, comprising: The enable signal is received at the first port of the latch; The latch receives a data input signal at its second port. An inverted signal of the output data from the latch is generated via an inverter connected to the latch; The inverted signal is sent to the second port; and Operate the latch and the inverter to provide the non-clonable output. When the enable signal has a first level, the latch and the inverter operate as a memory; when the enable signal has a second level, the latch and the inverter operate as a ring oscillator; and when the enable signal changes from the second level to the first level, the latch and the inverter are in a metastable state. The latch includes: A first NOR gate and a second NOR gate are connected in series. The first NOR gate has an output connected through the inverter. The inverter generates the inverted signal based on the output data of the first NOR gate. A first AND gate and a second AND gate, the second AND gate being connected in parallel with the first AND gate, each of the first AND gate and the second AND gate receiving both a) the enable signal and b) the inverted signal from the inverter, the inverted signal from the inverter being spun out and directly applied to the first AND gate and the second AND gate; The first AND gate provides input to the output of the second NOR gate; and The second AND gate provides input to the output of the first NOR gate.

12. The method of claim 11, wherein operating the latch and the inverter as the ring oscillator or operating the latch and the inverter in the metastable state provides a random number output.

13. The method of claim 12, wherein the random number output comprises physically unclonable random numbers.

14. The method of claim 11, wherein during the initialization of the circuit, the latch and the inverter, which operate as the memory, provide an identification pattern as a device identifier of the circuit.

15. The method of claim 11, wherein the latch and the inverter comprise a plurality of latches and inverters, and the method further comprises providing a set of probabilities for the non-clonable output, the set of probabilities relating to the probability that a single latch-inverter combination of the plurality of latches and inverters stores a value '0' or '1' during circuit initialization.

16. The method of claim 11, wherein the latch and the inverter comprise a plurality of latches and inverters, and the method further comprises providing a set of frequencies of a single latch-inverter combination of the plurality of latches and inverters for the unclonable output while the plurality of latches and inverters are operating as a ring oscillator.

17. The method of claim 11, wherein the latch and the inverter comprise a plurality of latches and inverters, and the method further comprises providing a set of frequencies of a single latch-inverter combination of the plurality of latches and inverters for the non-cloning output while the plurality of latches and inverters are operating in a metastable state.

18. A memory system, comprising: A semiconductor memory device having a control circuit and a latching circuit according to any one of claims 1-10, The control circuit operates the latch circuit as a ring oscillator for generating random numbers or as a memory for storing data.

19. The memory system of claim 18, wherein the latch circuit comprises: A set-reset latch has a first NOR gate and a second NOR gate. The first NOR gate has a reset input, and the second NOR gate has a set input. A first data output of the first NOR gate is connected to the second NOR gate, and a second data output of the first NOR gate is provided to the inverter. The first AND gate is connected to the setting input of the second NOR gate, and The second AND gate is connected to the reset input of the first NOR gate.

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