Control device and method for a read circuit of a flash memory

Abstract

The application discloses a control device of a read circuit of a flash memory. The memory unit adopts a split-gate floating-gate device, which comprises a first source and a second source-drain region, a plurality of first gate structures with floating gates, and a second gate structure between the first gate structures. The control gate of each first gate structure is connected to a control gate line. The second gate structure is connected to a corresponding word line. The control device is used for controlling the control gate voltage and the word line voltage of an unselected memory bit, and comprises the following steps: setting a first time period, setting the control gate voltage and the word line voltage as high voltage to realize reading; setting a second time period after the first time period, and setting the control gate voltage and the word line voltage as one or more than one middle voltage which is sequentially reduced in the second time period to prevent reading interference in the second time period. The application further provides a control method of a read circuit of a flash memory. The application improves the reading window, and can also prevent reading interference caused by high reading voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and in particular to a control device for a flash memory read circuit. This invention also relates to the control of a flash memory read circuit. Background Technology

[0002] like Figure 1 The diagram shown is a schematic diagram of the circuit structure of a conventional flash memory storage cell 101; as shown... Figure 2 The diagram shown is a cross-sectional view of a conventional flash memory cell 101; each of the aforementioned memory cells 101 employs a discrete-gate floating-gate device.

[0003] like Figure 2 As shown, the split-gate floating gate device includes: a first source-drain region 205 and a second source-drain region 206, a plurality of split first gate structures with floating gates 104 located between the first source-drain region 205 and the second source-drain region 206, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0004] The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are represented by the markings 102a and 102b respectively.

[0005] The separated gate floating gate device is an N-type device, and both the first source / drain region 205 and the second source / drain region 206 are composed of N+ regions.

[0006] The P-type doped channel region is located between the first source / drain region 205 and the second source / drain region 206 and is covered by each of the first gate structure and the second gate structure 103. The first source / drain region 205 and the second source / drain region 206 are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205 and the second source / drain region 206 or by further doping on the P-type semiconductor substrate 201.

[0007] The second source / drain region 206 of the storage cell 101 is connected to the bit line BL1.

[0008] The first source-drain region 205 of the storage unit 101 is connected to bit line BL0.

[0009] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0010] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0011] Figure 2 In this configuration, the two control gates 105 can be controlled separately and are connected to control gate lines CG0 and CG1 respectively, and the word line gate 106 is connected to the word line WL.

[0012] When reading from the storage unit 101, taking the reading operation on the storage bit 'a' corresponding to the first source-drain region 205 as an example:

[0013] The control gate line CG0 is connected to 0V;

[0014] The word line WL is connected to 3.5V;

[0015] The control gate line CG1 is connected to 5.3V;

[0016] The bit line BL0 is connected to 0V.

[0017] The bit line BL1 is connected to the read current Isense, with a value of 0.8A.

[0018] like Figure 3 The figure shows the read voltage curve of the read circuit of an existing flash memory cell during a read operation; Figure 3 In this context, the read voltage includes the control gate voltage for unselected memory bits and the word line voltage, where the word line voltage is also denoted by WL, and the control gate voltage for unselected memory bits is denoted by CG. Figure 3 In the reading, the voltage curve only represents the high and low levels of WL or CG, and does not represent the actual voltage. Therefore, the voltage changes of WL or CG use the same curve, and the corresponding curve is the WL / CG curve.

[0019] As can be seen from the WL / CG curve, the read voltage switches between a high voltage (high level 'H') and a low voltage (low level 'L'). The high level 'H' is further divided into two time periods, T1 and T2. Time period T1 completes the read of the selected memory bit; time period T2 is a voltage maintenance phase implemented after the read is completed to prevent the read voltage from dropping directly to the low level 'L'. Setting time period T2 reduces the switching frequency of the read voltage (WL or CG), thereby reducing the power consumption caused by frequent read voltage switching.

[0020] However, as the number of reads increases, the high voltage in time period T2 introduces read interference, which eventually alters the data in the corresponding memory bits. While reducing the read voltage to reduce read interference can reduce read accuracy, it cannot guarantee correct reading in time period T1. That is, in time period T1, as the high level 'H' of WL / CG decreases, the read window shrinks. Therefore, in the existing technology, the read voltage control cannot simultaneously satisfy the requirements of expanding the read window and reducing read interference during read operations. Summary of the Invention

[0021] The technical problem to be solved by this invention is to provide a control device for the read circuit of flash memory, which can provide sufficiently high read voltages, such as control gate voltage and word line voltage, during reading, thereby improving the read window and preventing read interference caused by high read voltages. To this end, this invention also provides a control method for the read circuit of flash memory.

[0022] Therefore, in the control device for the read circuit of the flash memory provided by the present invention, the flash memory includes multiple storage cells, and each storage cell adopts a discrete gate floating gate device.

[0023] The split-gate floating gate device includes: a first source-drain region and a second source-drain region, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate.

[0024] The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling a segment of the channel region.

[0025] Each of the floating gates of the first gate structure serves as a storage bit.

[0026] The control gate of each of the first gate structures is connected to the corresponding control gate line.

[0027] Each of the second gate structures is connected to the corresponding word line.

[0028] The read circuitry is used to provide control gate voltages to each of the control gate lines and word line voltages to the word lines during a read operation.

[0029] In a read operation on a selected memory cell, the control device controls the control gate voltage and the word line voltage for unselected memory bits, including:

[0030] A first time period is set, which is the time during which the selected storage bit of the selected storage unit is read.

[0031] The control gate voltage of the unselected memory bit during the first time period is set to a first high voltage and the word line voltage is set to a second high voltage. The first high voltage ensures that the channel region controlled by the first gate structure of the unselected memory bit is turned on and the second high voltage ensures that the channel region controlled by the second gate structure is turned on.

[0032] A second time period is set after the first time period. During the second time period, the control gate voltage of the unselected memory bit experiences one or more successively decreasing first intermediate voltages, and the word line voltage experiences one or more successively decreasing second intermediate voltages. Each first intermediate voltage is located between the first high voltage and the low voltage, and each second intermediate voltage is located between the second high voltage and the low voltage, in order to prevent read interference during the second time period.

[0033] A further improvement is that, during the read operation, the control gate voltage of the selected memory bit is set to the low voltage.

[0034] A further improvement is that, within the second time period, the time periods corresponding to each of the first voltages form multiple first time segments, and the time periods corresponding to each of the second voltages form multiple second time segments.

[0035] A further improvement is that the start and end times of each second time segment and the corresponding first time segment are the same.

[0036] A further improvement is that the start and end times of each first time segment corresponding to the first time period and the second time period are controlled by multiple read enable signals, and the number of read enable signals is the same as the number of each first time segment corresponding to the first time period and the second time period.

[0037] A further improvement is that all read enable signals are pulse signals.

[0038] A further improvement is that the control device also includes the following:

[0039] A chip enable signal, which sets the chip enable time period of the flash memory.

[0040] A further improvement is that, during the chip enable time period, the first time period and the second time period form a loop unit and cycle more than once.

[0041] When the chip enable period ends, the control gate voltage and word line voltage of the unselected memory bit are both set to the low voltage.

[0042] The chip enable signal also serves as the read enable signal with the largest pulse width.

[0043] A further improvement is that a third time period is included after the second time period ends, in which the control gate voltage and word line voltage of the unselected memory bit are both set to the low voltage.

[0044] During the chip enable time period, a loop unit is formed by the first time period, the second time period, and the third actual period, and the loop is repeated more than once.

[0045] A further improvement is that the control device further includes multiple charge pumps, and the first high voltage, each of the first intermediate voltages, the second high voltage, and each of the second intermediate voltages are output by the corresponding charge pumps.

[0046] A further improvement is that the control device also includes two of the charge pumps;

[0047] The first charge pump includes multiple output terminals, which respectively output the first high voltage and each of the first medium voltages;

[0048] The second charge pump includes multiple output terminals, which respectively output the second high voltage and each of the second medium voltages.

[0049] A further improvement is that the control device further includes a first selection circuit and a second selection circuit.

[0050] Each input terminal of the first selection circuit is connected to one of the first high voltage and one of the first medium voltages, and each selection terminal is connected to one of the read enable signals. Each read enable signal selects a voltage from the input terminals of the first selection circuit as the output voltage of the output terminal of the first selection circuit.

[0051] Each input terminal of the second selection circuit is connected to one of the second high voltage and one of the second medium voltages, and each selection terminal is connected to one of the read enable signals. Each read enable signal selects a voltage from the input terminals of the second selection circuit as the output voltage of the output terminal of the second selection circuit.

[0052] A further improvement is that the first selection circuit and the second selection circuit are identical; the first selection circuit includes:

[0053] Multiple first switching circuits, wherein the number of first switching circuits is the same as the number of read enable signals;

[0054] The first switching circuit includes:

[0055] The first PMOS transistor and the second PMOS transistor are connected together and serve as a selection terminal of the first selection circuit.

[0056] The drains of the first PMOS transistor and the drains of the second PMOS transistor are connected together;

[0057] The source of the first PMOS transistor serves as an input terminal of the first selection circuit.

[0058] The source of the second PMOS transistor is connected to the output of the first selection circuit.

[0059] To solve the above-mentioned technical problems, the flash memory read circuit control method provided by the present invention includes multiple memory cells, and each memory cell adopts a discrete gate floating gate device.

[0060] The split-gate floating gate device includes: a first source-drain region and a second source-drain region, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate.

[0061] The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling a segment of the channel region.

[0062] Each of the floating gates of the first gate structure serves as a storage bit.

[0063] The control gate of each of the first gate structures is connected to the corresponding control gate line.

[0064] Each of the second gate structures is connected to the corresponding word line.

[0065] The read circuitry is used to provide control gate voltages to each of the control gate lines and word line voltages to the word lines during a read operation.

[0066] In a read operation on a selected memory cell, the control steps for the control gate voltage and word line voltage of the unselected memory bit include:

[0067] A first time period is set, which is the time during which the selected storage bit of the selected storage unit is read.

[0068] The control gate voltage of the unselected memory bit during the first time period is set to a first high voltage and the word line voltage is set to a second high voltage. The first high voltage ensures that the channel region controlled by the first gate structure of the unselected memory bit is turned on and the second high voltage ensures that the channel region controlled by the second gate structure is turned on.

[0069] A second time period is set after the first time period. During the second time period, the control gate voltage of the unselected memory bit experiences one or more successively decreasing first intermediate voltages, and the word line voltage experiences one or more successively decreasing second intermediate voltages. Each first intermediate voltage is located between the first high voltage and the low voltage, and each second intermediate voltage is located between the second high voltage and the low voltage, in order to prevent read interference during the second time period.

[0070] A further improvement is that, during the read operation, the control gate voltage of the selected memory bit is set to the low voltage.

[0071] A further improvement is that, within the second time period, the time periods corresponding to each of the first voltages form multiple first time segments, and the time periods corresponding to each of the second voltages form multiple second time segments.

[0072] A further improvement is that the start and end times of each second time segment and the corresponding first time segment are the same.

[0073] A further improvement is that the start and end times of each first time segment corresponding to the first time period and the second time period are controlled by multiple read enable signals, and the number of read enable signals is the same as the number of each first time segment corresponding to the first time period and the second time period.

[0074] A further improvement is that all read enable signals are pulse signals.

[0075] A further improvement is that the control steps also include:

[0076] A chip enable signal is set, which sets the chip enable time period of the flash memory.

[0077] A further improvement is that, during the chip enable time period, the first time period and the second time period form a loop unit and cycle more than once.

[0078] When the chip enable period ends, the control gate voltage and word line voltage of the unselected memory bit are both set to the low voltage.

[0079] The chip enable signal also serves as the read enable signal with the largest pulse width.

[0080] A further improvement is that a third time period is included after the second time period ends, in which the control gate voltage and word line voltage of the unselected memory bit are both set to the low voltage.

[0081] During the chip enable time period, a loop unit is formed by the first time period, the second time period, and the third actual period, and the loop is repeated more than once.

[0082] This invention controls the control gate voltage and word line voltage of the unselected memory bit in the read voltage of the degree operation. Both read voltages are set to include a first time period and a second time period. The first time period is the time period for reading the selected memory bit of the selected memory cell. By setting the control gate voltage and word line voltage of the unselected memory bit in the first time period to high voltage, the read operation can be guaranteed and the read window can be improved.

[0083] In existing technologies, a second time period is set after the first time period to keep the control gate voltage and word line voltage of the unselected memory bit at the high voltage during reading, and then switch to a low voltage to reduce the voltage switching frequency of the control gate voltage and word line voltage of the unselected memory bit, thereby reducing power consumption. Unlike existing technologies, this invention sets a second time period after the first time period. In the second time period, the control gate voltage and word line voltage of the unselected memory bit are set to a medium voltage with more than one successively decreasing voltage. This avoids the need to switch the read voltage from high voltage to low voltage after reading is completed, thereby avoiding frequent voltage switching and reducing power consumption. At the same time, since the magnitude of the medium voltage is lower than the high voltage, it also avoids read interference caused by the high voltage of the read voltage to the memory bits of each memory cell of the flash memory in the second time period.

[0084] Furthermore, by setting a second time period, since the read voltage in the second time period is a medium voltage, which is different from the high voltage in the first time period, the present invention can continue the first time period after the second time period, thereby realizing the cycle of the first and second time periods; it can also switch the read voltage to a low level in the third time period after the second time period. Therefore, the present invention has more flexible and diverse settings for switching the read voltage, which is conducive to further optimizing the read performance of flash memory, such as further reducing power consumption and read interference. Attached Figure Description

[0085] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0086] Figure 1 This is a schematic diagram of the circuit structure of an existing flash memory storage cell;

[0087] Figure 2 This is a cross-sectional structural diagram of an existing flash memory storage cell;

[0088] Figure 3 It is the read voltage curve of the read circuit of the existing flash memory cell during a read operation;

[0089] Figures 4A-4C These are three read voltage curves controlled by the control device of the read circuit of the flash memory in this embodiment of the invention.

[0090] Figure 5 This is a structural block diagram of the first selection circuit of the control device for the read circuit of the flash memory in an embodiment of the present invention;

[0091] Figure 6 This is a circuit diagram of the first selection circuit of the control device for the read circuit of the flash memory in an embodiment of the present invention;

[0092] Figure 7 This is a structural diagram of the charge pump of the control device for the read circuit of the flash memory in an embodiment of the present invention. Detailed Implementation

[0093] The flash memory in this embodiment of the invention does not require changes to the structure of the storage cell 101; therefore, the circuit structure of the storage cell 101 in this embodiment of the flash memory is still referred to. Figure 1 Please refer to the diagram and cross-sectional structure shown. Figure 2 In the control device for the read circuit of the flash memory in the embodiment of the present invention, the flash memory includes a plurality of storage cells 101, and each of the storage cells 101 adopts a split-gate floating gate 104 device.

[0094] The separate gate floating gate 104 device includes: a first source / drain region 205 and a second source / drain region 206, a plurality of separate first gate structures with floating gates 104 located between the first source / drain region 205 and the second source / drain region 206, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.

[0095] The channel region is located between the first source / drain region 205 and the second source / drain region 206 and is covered by each of the first gate structure and the second gate structure 103, each of the first gate structure and the second gate structure 103 controlling a segment of the channel region.

[0096] Each of the floating gates 104 of the first gate structure serves as a storage bit.

[0097] The control gate 105 of each of the first gate structures is connected to the corresponding control gate line.

[0098] Each of the second gate structures 103 is connected to the corresponding word line WL.

[0099] In this embodiment of the invention, the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are respectively represented by the markings 102a and 102b.

[0100] The separated gate floating gate device is an N-type device, and both the first source / drain region 205 and the second source / drain region 206 are composed of N+ regions. The channel region is P-type doped.

[0101] The first source / drain region 205 and the second source / drain region 206 are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205 and the second source / drain region 206 or by further doping on the P-type semiconductor substrate 201.

[0102] The second source / drain region 206 of the storage cell 101 is connected to the bit line BL1.

[0103] The first source-drain region 205 of the storage unit 101 is connected to bit line BL0.

[0104] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0105] Each of the second gate structures 103 is formed by stacking a word line WL gate dielectric layer 204 and a word line WL gate 106.

[0106] Figure 2 In this configuration, the two control gates 105 can be controlled separately and are connected to control gate lines CG0 and CG1 respectively, and the word line WL gate 106 is connected to the word line WLWL.

[0107] The read circuitry is used to provide control gate voltages to each of the control gate lines and word line voltages to the word line WL during a read operation.

[0108] During a read operation on the selected memory cell 101, the control device is used to control the control gate voltage and the word line voltage for unselected memory bits, for example: Figure 2 In this context, storage bit 'a' corresponds to the storage bit corresponding to the floating gate 104 of the first gate structure CG0, and this storage bit 'a' is located near the first source / drain region 205; thus, the storage bit corresponding to the floating gate 104 of the first gate structure CG1 is an unselected storage bit. Figure 4AThe diagram shown is a read voltage curve controlled by the control device of the read circuit of the flash memory according to an embodiment of the present invention. In this embodiment, the control device controls the control gate voltage and the word line voltage for unselected memory bits, including:

[0109] A first time period T1 is set, which is the time during which the selected storage bit of the selected storage unit 101 is read.

[0110] The control gate voltage of the unselected memory bit during the first time period T1 is set to a first high voltage and the word line voltage is set to a second high voltage. The first high voltage ensures that the channel region controlled by the first gate structure of the unselected memory bit is turned on and the second high voltage ensures that the channel region controlled by the second gate structure 103 is turned on. Figure 4A In this embodiment, the control gate voltage for the unselected memory bit is represented by CG, and the word line voltage is represented by WL. Both the control gate voltage and the word line voltage for the unselected memory bit are represented by relative magnitudes, not actual values. Since the voltage changes of the control gate voltage and the word line voltage for the unselected memory bit are the same, they are represented by the same curve, namely the curve WL / CG. It can be seen that during the first time period T1, the curve WL / CG is a high level 'H'. For CG, the high level 'H' corresponds to the first high voltage; for WL, the high level 'H' corresponds to the second high voltage.

[0111] A second time period T2 is set after the first time period T1. During the second time period T2, the control gate voltage of the unselected storage bit experiences one or more successively decreasing first intermediate voltages, and the word line voltage experiences one or more successively decreasing second intermediate voltages. Each first intermediate voltage is located between the first high voltage and the low voltage, and each second intermediate voltage is located between the second high voltage and the low voltage, in order to prevent read interference during the second time period T2. Figure 4A In the curve WL / CG, a medium level 'M' is implemented. For CG, the medium level 'M' corresponds to a first medium voltage; for WL, the medium level 'M' corresponds to a second medium voltage.

[0112] and Figure 3 By comparison, it can be seen that Figure 4A In the second time period T2, the voltage of curve WL / CG is reduced, thus reducing read interference; at the same time, in the first time period T1, the voltage of curve WL / CG remains at a high value, thus still having a large read window and good reading effect.

[0113] In the read operation, the control gate voltage of the selected memory bit is set to the low voltage. Figure 4A The control gate voltage of the selected memory bit is not displayed.

[0114] In some embodiments, within the second time period T2, the time periods corresponding to each of the first voltages form multiple first time segments, and the time periods corresponding to each of the second voltages form multiple second time segments. For example... Figure 4B The diagram shown is another read voltage curve controlled by the control device of the read circuit of the flash memory according to an embodiment of the present invention; and Figure 4A The difference is that, Figure 4B In this context, there are two intermediate levels, 'M1' and 'M2', where 'M2' is less than 'M1'. Each intermediate level corresponds to a time segment, such as T21 for 'M1' and T22 for 'M2'. The second time segment T2 is the sum of time segments T21 and T22.

[0115] For CG, time segments T21 and T22 are each of the first time segments; for WL, time segments T21 and T22 are each of the second time segments. The start and end times of each second time segment and the corresponding first time segment are the same.

[0116] In this embodiment of the invention, the start and end times of each first time segment corresponding to the first time period T1 and the second time period T2 are controlled by multiple read enable signals, and the number of read enable signals is the same as the number of each first time segment corresponding to the first time period T1 and the second time period T2.

[0117] All read enable signals are pulse signals.

[0118] The control device also includes:

[0119] The chip enable signal CE sets the chip enable time period of the flash memory.

[0120] In some implementations, during the chip enable period, a loop unit consisting of the first time period T1 and the second time period T2 is formed and looped more than once. At the end of the chip enable period, the control gate voltage and the word line voltage of the unselected memory bit are both set to the low voltage 'L'.

[0121] The chip enable signal CE also serves as the read enable signal with the largest pulse width.

[0122] like Figure 4AIn the corresponding embodiment, two read enable signals are included: signal SEN and signal CE. Signal SEN represents a read enable signal, and signal CE represents the chip enable signal CE. That is, the chip enable signal CE is directly used as a read enable signal. It can be seen that the pulse width of signal SEN controls the length of the first time period T1, and the spacing between two adjacent pulses of signal SEN controls the length of the second time period T2. Figure 4A As shown, T1 and T2 are repeated twice within the pulse width range of the chip enable signal CE. In other embodiments, T1 and T2 may also be repeated more than three times within the pulse width range of the chip enable signal CE.

[0123] like Figure 4B In the corresponding embodiment, three read enable signals are included: SEN, SEN_D1, and CE / SEN_D2. SEN_D1 is the second read enable signal, SEN_D2 is the third read enable signal, and SEN_D2 can directly use signal CE. It can be seen that the rising edges of SEN and SEN_D1 are aligned. The pulse width of SEN controls the length of the first time period T1, and the distance between the falling edge of the SEN pulse and the falling edge of the SEN_D1 pulse controls the duration of the time segment T21 corresponding to 'M1'. The distance between two adjacent SEN_D1 pulses controls the length of the time segment T22. Figure 4B As shown, T1 and T2 are repeated twice within the pulse width range of the chip enable signal CE. In other embodiments, T1 and T2 may also be repeated more than three times within the pulse width range of the chip enable signal CE.

[0124] In other embodiments of the present invention, such as Figure 4C The figure shown is another read voltage curve controlled by the control device of the read circuit of the flash memory in an embodiment of the present invention; after the second time period T2 ends, a third time period T3 is also included, in which the control gate voltage and the word line voltage of the unselected storage bit are both set to the low voltage 'L'.

[0125] During the chip enable time period, a loop unit is formed by the first time period T1, the second time period T2, and the third actual segment, and the loop is repeated more than once.

[0126] Figure 4CThe image shows three read enable signals: SEN, SEN_D1, and SEN_D2. SEN_D1 is the second read enable signal, and SEN_D2 is the third. Signal CE is not shown. It can be seen that the rising edges of signals SEN, SEN_D1, and SEN_D2 are aligned. The pulse width of signal SEN controls the length of the first time period T1. The distance between the falling edge of the pulse of signal SEN and the falling edge of the pulse of signal SEN_D1 controls the duration of the time segment T21 corresponding to 'M1'. The distance between the falling edge of the pulse of signal SEN_D1 and the falling edge of the pulse of signal SEN_D2 controls the length of the time segment T22. The distance between two adjacent pulses of signal SEN_D2 controls the length of T3. Although signal CE is not shown in the 4C image, T1, T2, and T3 are repeated multiple times within the pulse width range of the chip enable signal CE.

[0127] In this embodiment of the invention, the control device further includes a plurality of the charge pumps.

[0128] The first high voltage, each of the first intermediate voltages, the second high voltage, and each of the second intermediate voltages are all output by the corresponding charge pumps. Since the control gate voltage and the word line voltage for the unselected storage bit are actually different, denoted by CG and WL respectively: In some embodiments, during reading, the high voltage of CG is 5.3V, and the high voltage of WL is 3.5V.

[0129] Therefore, it is necessary to output the required first high voltage, each of the first medium voltages, the second high voltage, and each of the second medium voltages through multiple charge pumps.

[0130] In some preferred embodiments, the control device further includes two of the charge pumps.

[0131] The first charge pump includes multiple output terminals, which respectively output the first high voltage and each of the first medium voltages;

[0132] The second charge pump includes multiple output terminals, which respectively output the second high voltage and each of the second medium voltages.

[0133] like Figure 7 The diagram shown is a structural diagram of the charge pump of the control device for the read circuit of the flash memory according to an embodiment of the present invention. Figure 7 Corresponding to one of the first charge pump and the second charge pump, charge pump 401 includes a multi-stage charge pump unit 402. Figure 7The image shows three multi-stage charge pump units 402, which are also labeled CP1, CP2, and CP3 respectively; a corresponding voltage is output at the corresponding charge pump unit 402, such as... Figure 7 The image shows three output voltages: VH, VM1, and VM2. If... Figure 7 When the charge pump shown is the first charge pump, VH, VM1, and VM2 are the first high voltage and two successively decreasing first intermediate voltages, respectively; if Figure 7 When the charge pump shown is the second charge pump, VH, VM1, and VM2 are the second high voltage and two successively decreasing second intermediate voltages, respectively.

[0134] In this embodiment of the invention, the control device further includes a first selection circuit 301 and a second selection circuit.

[0135] like Figure 5 The diagram shown is a structural block diagram of the first selection circuit 301 of the control device for the read circuit of the flash memory according to an embodiment of the present invention. Each input terminal of the first selection circuit 301 is connected to one of the first high voltage and one of the first medium voltages, and each selection terminal is connected to one of the read enable signals. Each read enable signal selects a voltage from the input terminals of the first selection circuit 301 as the output voltage of the output terminal of the first selection circuit 301. Figure 5 In the diagram, the first selection circuit 301 shows two input terminals, two selection terminals, and one output terminal. The input voltages are VH and VMx, respectively, where VH represents the first high voltage and VMx represents one of the first intermediate voltages. The selection terminals are input voltages SEN and SEN_Dx, respectively, and the signals SEN and... Figure 4A , Figure 4B and Figure 4C The signals SEN and Dx are the same; x in signal SEN_Dx is a number, and x = 1 corresponds to... Figure 4B or Figure 4C The signal SEN_D1, when x is 2, corresponds to Figure 4B or Figure 4C The signal SEN_D2 in the middle, and so on; the voltage VR at the output terminal is a voltage selected from VH and VMx.

[0136] Each input terminal of the second selection circuit is connected to one of the second high voltage and one of the second medium voltages, respectively. Each selection terminal is connected to one of the read enable signals, and each read enable signal selects a voltage from the input terminals of the second selection circuit as the output voltage of the second selection circuit. The first selection circuit 301 is the same as the second selection circuit, except that the voltages connected to its input terminals are different. The voltages input to the selection terminals are the same, but the output voltage changes according to the voltage at the input terminals.

[0137] like Figure 6 The diagram shown is a circuit diagram of the first selection circuit 301 of the control device for the read circuit of the flash memory according to an embodiment of the present invention; the first selection circuit 301 includes:

[0138] Multiple first switch circuits 302, the number of first switch circuits 302 being the same as the number of read enable signals;

[0139] The first switching circuit 302 includes:

[0140] The first PMOS transistor MP1 and the second PMOS transistor MP2 are connected together and serve as a selection terminal of the first selection circuit 301. Figure 6 In the two selection terminals of the first switching circuit 302, the signals are SEN_H and SEN_Dx_H, which are obtained from the signals SEN and SEN_Dx, respectively.

[0141] The drain of the first PMOS transistor MP1 and the drain of the second PMOS transistor MP2 are connected together;

[0142] The source of the first PMOS transistor MP1 serves as an input terminal of the first selection circuit 301;

[0143] The source of the second PMOS transistor MP2 is connected to the output of the first selection circuit 301.

[0144] In this embodiment of the invention, the control gate voltage and word line voltage of the unselected memory bit in the read voltage of the degree operation are controlled. Both read voltages are set to include a first time period T1 and a second time period T2. The first time period T1 is the time period for reading the selected memory bit of the selected memory cell 101. By setting the control gate voltage and word line voltage of the unselected memory bit in the first time period T1 to high voltage, the read operation can be guaranteed and the read window can be improved.

[0145] In the prior art, a second time period T2 is set after the first time period T1 to keep the control gate voltage and word line voltage of the unselected memory bit at the high voltage during reading, and then switch to low voltage to reduce the voltage switching frequency of the control gate voltage and word line voltage of the unselected memory bit, thereby reducing power consumption. Unlike the prior art, the embodiment of the present invention sets a second time period T2 after the first time period T1. In the second time period T2, the control gate voltage and word line voltage of the unselected memory bit are set to have one or more successively decreasing medium voltages. This can avoid the need to switch the read voltage from high voltage to low voltage after reading is completed, thereby avoiding frequent voltage switching and reducing power consumption. At the same time, since the magnitude of the medium voltage is lower than the high voltage, it can also avoid read interference caused by the high voltage of the read voltage to the memory bits of each memory cell 101 of the flash memory in the second time period T2.

[0146] Furthermore, in this embodiment of the invention, after setting the second time period T2, since the read voltage in the second time period T2 is a medium voltage, which is different from the high voltage in the first time period T1, the first time period T1 can continue after the second time period T2, thereby realizing the cycle of the first time period T1 and the second time period T2; it can also switch the read voltage to a low level in the third time period T3 after the second time period T2. Therefore, the switching settings of the read voltage in this embodiment of the invention are more flexible and diverse, which is conducive to further optimizing the read performance of flash memory, such as further reducing power consumption and read interference.

[0147] The flash memory in this embodiment of the invention does not require changes to the structure of the storage cell 101; therefore, the circuit structure of the storage cell 101 in this embodiment of the flash memory is still referred to. Figure 1 Please refer to the diagram and cross-sectional structure shown. Figure 2 In the control device for the read circuit of the flash memory in the embodiment of the present invention, the flash memory includes a plurality of storage cells 101, and each of the storage cells 101 adopts a split-gate floating gate 104 device.

[0148] The separate gate floating gate 104 device includes: a first source / drain region 205 and a second source / drain region 206, a plurality of separate first gate structures with floating gates 104 located between the first source / drain region 205 and the second source / drain region 206, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.

[0149] The channel region is located between the first source / drain region 205 and the second source / drain region 206 and is covered by each of the first gate structure and the second gate structure 103, each of the first gate structure and the second gate structure 103 controlling a segment of the channel region.

[0150] Each of the floating gates 104 of the first gate structure serves as a storage bit.

[0151] The control gate 105 of each of the first gate structures is connected to the corresponding control gate line.

[0152] Each of the second gate structures 103 is connected to the corresponding word line WL.

[0153] In this embodiment of the invention, the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are respectively represented by the markings 102a and 102b.

[0154] The separated gate floating gate device is an N-type device, and both the first source / drain region 205 and the second source / drain region 206 are composed of N+ regions. The channel region is P-type doped.

[0155] The first source / drain region 205 and the second source / drain region 206 are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205 and the second source / drain region 206 or by further doping on the P-type semiconductor substrate 201.

[0156] The second source / drain region 206 of the storage cell 101 is connected to the bit line BL1.

[0157] The first source-drain region 205 of the storage unit 101 is connected to bit line BL0.

[0158] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0159] Each of the second gate structures 103 is formed by stacking a word line WL gate dielectric layer 204 and a word line WL gate 106.

[0160] Figure 2 In this configuration, the two control gates 105 can be controlled separately and are connected to control gate lines CG0 and CG1 respectively, and the word line WL gate 106 is connected to the word line WLWL.

[0161] The read circuitry is used to provide control gate voltages to each of the control gate lines and word line voltages to the word line WL during a read operation.

[0162] During a read operation on the selected memory cell 101, the control device is used to control the control gate voltage and the word line voltage for unselected memory bits, for example: Figure 2In this context, storage bit 'a' corresponds to the storage bit corresponding to the floating gate 104 of the first gate structure CG0, and this storage bit 'a' is located near the first source / drain region 205; thus, the storage bit corresponding to the floating gate 104 of the first gate structure CG1 is an unselected storage bit. Figure 4A The diagram shown is a read voltage curve controlled by the control device of the read circuit of the flash memory according to an embodiment of the present invention. In the method of this embodiment, during a read operation on the selected memory cell 101, the control steps for the control gate voltage and the word line voltage of the unselected memory bit include:

[0163] A first time period T1 is set, which is the time during which the selected storage bit of the selected storage unit 101 is read.

[0164] The control gate voltage of the unselected memory bit during the first time period T1 is set to a first high voltage and the word line voltage is set to a second high voltage. The first high voltage ensures that the channel region controlled by the first gate structure of the unselected memory bit is turned on and the second high voltage ensures that the channel region controlled by the second gate structure 103 is turned on. Figure 4A In this embodiment, the control gate voltage for the unselected memory bit is represented by CG, and the word line voltage is represented by WL. Both the control gate voltage and the word line voltage for the unselected memory bit are represented by relative magnitudes, not actual values. Since the voltage changes of the control gate voltage and the word line voltage for the unselected memory bit are the same, they are represented by the same curve, namely the curve WL / CG. It can be seen that during the first time period T1, the curve WL / CG is a high level 'H'. For CG, the high level 'H' corresponds to the first high voltage; for WL, the high level 'H' corresponds to the second high voltage.

[0165] A second time period T2 is set after the first time period T1. During the second time period T2, the control gate voltage of the unselected storage bit experiences one or more successively decreasing first intermediate voltages, and the word line voltage experiences one or more successively decreasing second intermediate voltages. Each first intermediate voltage is located between the first high voltage and the low voltage, and each second intermediate voltage is located between the second high voltage and the low voltage, in order to prevent read interference during the second time period T2. Figure 4A In the curve WL / CG, a medium level 'M' is implemented. For CG, the medium level 'M' corresponds to a first medium voltage; for WL, the medium level 'M' corresponds to a second medium voltage.

[0166] and Figure 3 By comparison, it can be seen that Figure 4AIn the second time period T2, the voltage of curve WL / CG is reduced, thus reducing read interference; at the same time, in the first time period T1, the voltage of curve WL / CG remains at a high value, thus still having a large read window and good reading effect.

[0167] In the read operation, the control gate voltage of the selected memory bit is set to the low voltage. Figure 4A The control gate voltage of the selected memory bit is not displayed.

[0168] In some embodiments, within the second time period T2, the time periods corresponding to each of the first voltages form multiple first time segments, and the time periods corresponding to each of the second voltages form multiple second time segments. For example... Figure 4B The diagram shown is another read voltage curve controlled by the control device of the read circuit of the flash memory according to an embodiment of the present invention; and Figure 4A The difference is that, Figure 4B In this context, there are two intermediate levels, 'M1' and 'M2', where 'M2' is less than 'M1'. Each intermediate level corresponds to a time segment, such as T21 for 'M1' and T22 for 'M2'. The second time segment T2 is the sum of time segments T21 and T22.

[0169] For CG, time segments T21 and T22 are each of the first time segments; for WL, time segments T21 and T22 are each of the second time segments. The start and end times of each second time segment and the corresponding first time segment are the same.

[0170] In this embodiment of the invention, the start and end times of each first time segment corresponding to the first time period T1 and the second time period T2 are controlled by multiple read enable signals, and the number of read enable signals is the same as the number of each first time segment corresponding to the first time period T1 and the second time period T2.

[0171] All read enable signals are pulse signals.

[0172] The control device also includes:

[0173] The chip enable signal CE sets the chip enable time period of the flash memory.

[0174] In some implementations, during the chip enable period, a loop unit consisting of the first time period T1 and the second time period T2 is formed and looped more than once. At the end of the chip enable period, the control gate voltage and the word line voltage of the unselected memory bit are both set to the low voltage 'L'.

[0175] The chip enable signal CE also serves as the read enable signal with the largest pulse width.

[0176] like Figure 4A In the corresponding embodiment, two read enable signals are included: signal SEN and signal CE. Signal SEN represents a read enable signal, and signal CE represents the chip enable signal CE. That is, the chip enable signal CE is directly used as a read enable signal. It can be seen that the pulse width of signal SEN controls the length of the first time period T1, and the spacing between two adjacent pulses of signal SEN controls the length of the second time period T2. Figure 4A As shown, T1 and T2 are repeated twice within the pulse width range of the chip enable signal CE. In other embodiments, T1 and T2 may also be repeated more than three times within the pulse width range of the chip enable signal CE.

[0177] like Figure 4B In the corresponding embodiment, three read enable signals are included: SEN, SEN_D1, and CE / SEN_D2. SEN_D1 is the second read enable signal, SEN_D2 is the third read enable signal, and SEN_D2 can directly use signal CE. It can be seen that the rising edges of SEN and SEN_D1 are aligned. The pulse width of SEN controls the length of the first time period T1, and the distance between the falling edge of the SEN pulse and the falling edge of the SEN_D1 pulse controls the duration of the time segment T21 corresponding to 'M1'. The distance between two adjacent SEN_D1 pulses controls the length of the time segment T22. Figure 4B As shown, T1 and T2 are repeated twice within the pulse width range of the chip enable signal CE. In other embodiments, T1 and T2 may also be repeated more than three times within the pulse width range of the chip enable signal CE.

[0178] In other embodiments of the present invention, such as Figure 4C The figure shown is another read voltage curve controlled by the control device of the read circuit of the flash memory in an embodiment of the present invention; after the second time period T2 ends, a third time period T3 is also included, in which the control gate voltage and the word line voltage of the unselected storage bit are both set to the low voltage 'L'.

[0179] During the chip enable time period, a loop unit is formed by the first time period T1, the second time period T2, and the third actual segment, and the loop is repeated more than once.

[0180] Figure 4CThe image shows three read enable signals: SEN, SEN_D1, and SEN_D2. SEN_D1 is the second read enable signal, and SEN_D2 is the third. Signal CE is not shown. It can be seen that the rising edges of signals SEN, SEN_D1, and SEN_D2 are aligned. The pulse width of signal SEN controls the length of the first time period T1. The distance between the falling edge of the pulse of signal SEN and the falling edge of the pulse of signal SEN_D1 controls the duration of the time segment T21 corresponding to 'M1'. The distance between the falling edge of the pulse of signal SEN_D1 and the falling edge of the pulse of signal SEN_D2 controls the length of the time segment T22. The distance between two adjacent pulses of signal SEN_D2 controls the length of T3. Although signal CE is not shown in the 4C image, T1, T2, and T3 are repeated multiple times within the pulse width range of the chip enable signal CE.

[0181] In this embodiment of the invention, the control device further includes a plurality of the charge pumps.

[0182] The first high voltage, each of the first intermediate voltages, the second high voltage, and each of the second intermediate voltages are all output by the corresponding charge pumps. Since the control gate voltage and the word line voltage for the unselected storage bit are actually different, denoted by CG and WL respectively: In some embodiments, during reading, the high voltage of CG is 5.3V, and the high voltage of WL is 3.5V.

[0183] Therefore, it is necessary to output the required first high voltage, each of the first medium voltages, the second high voltage, and each of the second medium voltages through multiple charge pumps.

[0184] In some preferred embodiments, the control device further includes two of the charge pumps.

[0185] The first charge pump includes multiple output terminals, which respectively output the first high voltage and each of the first medium voltages;

[0186] The second charge pump includes multiple output terminals, which respectively output the second high voltage and each of the second medium voltages.

[0187] like Figure 7 The diagram shown is a structural diagram of the charge pump of the control device for the read circuit of the flash memory according to an embodiment of the present invention. Figure 7 Corresponding to one of the first charge pump and the second charge pump, charge pump 401 includes a multi-stage charge pump unit 402, at which a corresponding voltage is output, such as... Figure 7 The image shows three output voltages: VH, VM1, and VM2. If... Figure 7When the charge pump shown is the first charge pump, VH, VM1, and VM2 are the first high voltage and two successively decreasing first intermediate voltages, respectively; if Figure 7 When the charge pump shown is the second charge pump, VH, VM1, and VM2 are the second high voltage and two successively decreasing second intermediate voltages, respectively.

[0188] In this embodiment of the invention, the control device further includes a first selection circuit 301 and a second selection circuit.

[0189] like Figure 5 The diagram shown is a structural block diagram of the first selection circuit 301 of the control device for the read circuit of the flash memory according to an embodiment of the present invention. Each input terminal of the first selection circuit 301 is connected to one of the first high voltage and one of the first medium voltages, and each selection terminal is connected to one of the read enable signals. Each read enable signal selects a voltage from the input terminals of the first selection circuit 301 as the output voltage of the output terminal of the first selection circuit 301. Figure 5 In the diagram, the first selection circuit 301 shows two input terminals, two selection terminals, and one output terminal. The input voltages are VH and VMx, respectively, where VH represents the first high voltage and VMx represents one of the first intermediate voltages. The selection terminals are input voltages SEN and SEN_Dx, respectively, and the signals SEN and... Figure 4A , Figure 4B and Figure 4C The signals SEN and Dx are the same; x in signal SEN_Dx is a number, and x = 1 corresponds to... Figure 4B or Figure 4C The signal SEN_D1, when x is 2, corresponds to Figure 4B or Figure 4C The signal SEN_D2 in the middle, and so on; the voltage VR at the output terminal is a voltage selected from VH and VMx.

[0190] Each input terminal of the second selection circuit is connected to one of the second high voltage and one of the second medium voltages, respectively. Each selection terminal is connected to one of the read enable signals, and each read enable signal selects a voltage from the input terminals of the second selection circuit as the output voltage of the second selection circuit. The first selection circuit 301 is the same as the second selection circuit, except that the voltages connected to its input terminals are different. The voltages input to the selection terminals are the same, but the output voltage changes according to the voltage at the input terminals.

[0191] like Figure 6 The diagram shown is a circuit diagram of the first selection circuit 301 of the control device for the read circuit of the flash memory according to an embodiment of the present invention; the first selection circuit 301 includes:

[0192] Multiple first switch circuits 302, the number of first switch circuits 302 being the same as the number of read enable signals;

[0193] The first switching circuit 302 includes:

[0194] The first PMOS transistor MP1 and the second PMOS transistor MP2 are connected together and serve as a selection terminal of the first selection circuit 301. Figure 6 In the two selection terminals of the first switching circuit 302, the signals are SEN_H and SEN_Dx_H, which are obtained from the signals SEN and SEN_Dx, respectively.

[0195] The drain of the first PMOS transistor MP1 and the drain of the second PMOS transistor MP2 are connected together;

[0196] The source of the first PMOS transistor MP1 serves as an input terminal of the first selection circuit 301;

[0197] The source of the second PMOS transistor MP2 is connected to the output of the first selection circuit 301.

[0198] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A control device for a flash memory read circuit, characterized in that, Flash memory includes multiple storage cells, each of which employs a discrete-gate floating-gate device; The split-gate floating gate device includes: a first source-drain region and a second source-drain region, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate. The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling a segment of the channel region; Each of the floating gates of the first gate structure serves as a storage bit; The control gate of each of the first gate structures is connected to the corresponding control gate line; Each of the second gate structures is connected to the corresponding word line; The read circuitry is used to provide control gate voltages to each of the control gate lines and word line voltages to the word lines during a read operation; In a read operation on a selected memory cell, the control device controls the control gate voltage and the word line voltage for unselected memory bits, including: A first time period is set, which is the time during which the selected storage bit of the selected storage unit is read; The control gate voltage of the unselected memory bit during the first time period is set to a first high voltage and the word line voltage is set to a second high voltage. The first high voltage ensures that the region segment of the channel controlled by the first gate structure of the unselected memory bit is turned on and the second high voltage ensures that the region segment of the channel controlled by the second gate structure is turned on. A second time period is set after the first time period. During the second time period, the control gate voltage of the unselected memory bit experiences one or more successively decreasing first intermediate voltages, and the word line voltage experiences one or more successively decreasing second intermediate voltages. Each first intermediate voltage is located between the first high voltage and the low voltage, and each second intermediate voltage is located between the second high voltage and the low voltage, in order to prevent read interference during the second time period.

2. The control device for the read circuit of flash memory as described in claim 1, characterized in that: In the read operation, the control gate voltage of the selected memory bit is set to the low voltage.

3. The control device for the read circuit of flash memory as described in claim 1, characterized in that: Within the second time period, the time periods corresponding to each of the first voltages form multiple first time segments, and the time periods corresponding to each of the second voltages form multiple second time segments.

4. The control device for the read circuit of flash memory as described in claim 3, characterized in that: The start and end times of each second time segment and the corresponding first time segment are the same.

5. The control device for the read circuit of flash memory as described in claim 4, characterized in that: The start and end times of each first time segment corresponding to the first time period and the second time period are controlled by multiple read enable signals. The number of read enable signals is the same as the number of each first time segment corresponding to the first time period and the second time period.

6. The control device for the read circuit of flash memory as described in claim 5, characterized in that: All read enable signals are pulse signals.

7. The control device for the read circuit of flash memory as described in claim 6, characterized in that: The control device also includes: A chip enable signal, which sets the chip enable time period of the flash memory.

8. The control device for the read circuit of flash memory as described in claim 7, characterized in that: During the chip enable time period, the first time period and the second time period constitute a loop unit and are cycled more than once; When the chip enable period ends, the control gate voltage and word line voltage of the unselected memory bit are both set to the low voltage. The chip enable signal also serves as the read enable signal with the largest pulse width.

9. The control device for the read circuit of flash memory as described in claim 7, characterized in that: After the second time period ends, a third time period is also included, in which the control gate voltage and word line voltage of the unselected memory bit are both set to the low voltage; During the chip enable time period, the first time period, the second time period, and the third time period constitute a loop unit and cycle at least once.

10. The control device for the read circuit of flash memory as described in claim 6, characterized in that: The control device also includes multiple charge pumps, and the first high voltage, each of the first intermediate voltages, the second high voltage, and each of the second intermediate voltages are output by the corresponding charge pumps.

11. The control device for the read circuit of the flash memory as described in claim 10, characterized in that: The control device also includes two of the charge pumps; The first charge pump includes multiple output terminals, which respectively output the first high voltage and each of the first medium voltages; The second charge pump includes multiple output terminals, which respectively output the second high voltage and each of the second medium voltages.

12. The control device for the read circuit of flash memory as described in claim 10, characterized in that: The control device further includes a first selection circuit and a second selection circuit; Each input terminal of the first selection circuit is connected to one of the first high voltage and one of the first medium voltages, and each selection terminal is connected to one of the read enable signals. Each read enable signal selects a voltage from the input terminals of the first selection circuit as the output voltage of the output terminal of the first selection circuit. Each input terminal of the second selection circuit is connected to one of the second high voltage and one of the second medium voltages, and each selection terminal is connected to one of the read enable signals. Each read enable signal selects a voltage from the input terminals of the second selection circuit as the output voltage of the output terminal of the second selection circuit.

13. The control device for the read circuit of flash memory as described in claim 12, characterized in that: The first selection circuit and the second selection circuit are the same; the first selection circuit includes: Multiple first switching circuits, the number of which is the same as the number of read enable signals; The first switching circuit includes: The first PMOS transistor and the second PMOS transistor are connected together and serve as a selection terminal of the first selection circuit. The drains of the first PMOS transistor and the drains of the second PMOS transistor are connected together; The source of the first PMOS transistor serves as an input terminal of the first selection circuit. The source of the second PMOS transistor is connected to the output of the first selection circuit.

14. A method for controlling the read circuit of a flash memory, characterized in that, Flash memory includes multiple storage cells, each of which employs a discrete-gate floating-gate device; The split-gate floating gate device includes: a first source-drain region and a second source-drain region, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate. The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling a segment of the channel region; Each of the floating gates of the first gate structure serves as a storage bit; The control gate of each of the first gate structures is connected to the corresponding control gate line; Each of the second gate structures is connected to the corresponding word line; The read circuitry is used to provide control gate voltages to each of the control gate lines and word line voltages to the word lines during a read operation; In a read operation on a selected memory cell, the control steps for the control gate voltage and word line voltage of the unselected memory bit include: A first time period is set, which is the time during which the selected storage bit of the selected storage unit is read; The control gate voltage of the unselected memory bit during the first time period is set to a first high voltage and the word line voltage is set to a second high voltage. The first high voltage ensures that the region segment of the channel controlled by the first gate structure of the unselected memory bit is turned on and the second high voltage ensures that the region segment of the channel controlled by the second gate structure is turned on. A second time period is set after the first time period. During the second time period, the control gate voltage of the unselected memory bit experiences one or more successively decreasing first intermediate voltages, and the word line voltage experiences one or more successively decreasing second intermediate voltages. Each first intermediate voltage is located between the first high voltage and the low voltage, and each second intermediate voltage is located between the second high voltage and the low voltage, in order to prevent read interference during the second time period.

15. The control method for the read circuit of flash memory as described in claim 14, characterized in that: In the read operation, the control gate voltage of the selected memory bit is set to the low voltage.

16. The control method for the read circuit of flash memory as described in claim 14, characterized in that: Within the second time period, the time periods corresponding to each of the first voltages form multiple first time segments, and the time periods corresponding to each of the second voltages form multiple second time segments.

17. The control method for the read circuit of flash memory as described in claim 16, characterized in that: The start and end times of each second time segment and the corresponding first time segment are the same.

18. The control method for the read circuit of flash memory as described in claim 17, characterized in that: The start and end times of each first time segment corresponding to the first time period and the second time period are controlled by multiple read enable signals. The number of read enable signals is the same as the number of each first time segment corresponding to the first time period and the second time period.

19. The control method for the read circuit of flash memory as described in claim 18, characterized in that: All read enable signals are pulse signals.

20. The control method for the read circuit of flash memory as described in claim 19, characterized in that: The control steps also include: A chip enable signal is set, which sets the chip enable time period of the flash memory.

21. The control method for the read circuit of flash memory as described in claim 20, characterized in that: During the chip enable time period, the first time period and the second time period constitute a loop unit and are cycled more than once; When the chip enable period ends, the control gate voltage and word line voltage of the unselected memory bit are both set to the low voltage. The chip enable signal also serves as the read enable signal with the largest pulse width.

22. The control method for the read circuit of flash memory as described in claim 20, characterized in that: After the second time period ends, a third time period is also included, in which the control gate voltage and word line voltage of the unselected memory bit are both set to the low voltage; During the chip enable time period, the first time period, the second time period, and the third time period constitute a loop unit and cycle at least once.

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