Semiconductor memory device

Abstract

The present invention provides a semiconductor memory device capable of performing a preferable erase operation. The semiconductor memory device performs: an erase voltage supply operation of supplying an erase voltage to a first wiring; a first erase verification operation of, after the erase voltage supply operation is performed, supplying a readout path voltage to a first conductive layer that is one of a plurality of conductive layers and supplying an erase verification voltage to a second conductive layer that is one of the plurality of conductive layers; and a second erase verification operation of, after the first erase verification operation is performed, supplying the erase verification voltage to the first conductive layer and supplying the readout path voltage to the second conductive layer. The erase voltage is increased by a first offset voltage from a first erase cycle to an a-th erase cycle, and the erase voltage is increased by a second offset voltage from an a+1-th erase cycle to a b-th erase cycle. The second offset voltage is greater than the first offset voltage.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2022-024627 (filed on February 21, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known, comprising: a substrate; a plurality of first conductive layers arranged along a first direction intersecting the surface of the substrate; and a semiconductor layer extending along the first direction and facing the plurality of first conductive layers. Summary of the Invention

[0005] A semiconductor memory device capable of performing a better erase operation is provided.

[0006] A semiconductor memory device according to one embodiment includes: a substrate; a plurality of conductive layers arranged along a first direction intersecting the surface of the substrate; a first semiconductor layer extending along the first direction and facing the plurality of conductive layers; a charge storage layer disposed between the plurality of conductive layers and the first semiconductor layer; a first wiring connected to one end of the first semiconductor layer in the first direction; and a control circuit electrically connected to the plurality of conductive layers and the first wiring; the control circuit is configured to perform an erase operation, the erase operation including a plurality of erase cycles, each of the plurality of erase cycles including: an erase voltage supply operation, supplying an erase voltage to the first wiring; and a first erase verification operation, after performing the erase voltage supply operation, verifying the first wiring as the first semiconductor layer. A first conductive layer, one of the plurality of conductive layers, is supplied with a first read path voltage smaller than the erase voltage; a second conductive layer, one of the plurality of conductive layers, is supplied with a first erase verification voltage smaller than the first read path voltage; and a second erase verification operation is performed, wherein after the first erase verification operation is performed, a second erase verification voltage is supplied to the first conductive layer, and a second read path voltage is supplied to the second conductive layer; from the first erase cycle to the a-th (a is an integer greater than or equal to 1) erase cycle, the erase voltage is increased by a first offset voltage; from the (a+1)-th erase cycle to the b-th (b is an integer greater than or equal to a+1) erase cycle, the erase voltage is increased by a second offset voltage, and the second offset voltage is greater than the first offset voltage. Attached Figure Description

[0007] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10.

[0008] Figure 2 This is a schematic block diagram showing the configuration of the memory die MD in the first embodiment.

[0009] Figure 3 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0010] Figure 4 It means Figure 3 A schematic circuit diagram of the configuration of the string component SU.

[0011] Figure 5 This is a schematic block diagram showing the configuration of the sense amplifier module (SAM).

[0012] Figure 6 This is a schematic 3D diagram representing a portion of a memory die (MD).

[0013] Figure 7 It means Figure 6 A schematic enlarged diagram consisting of a portion of it.

[0014] Figure 8 It is a schematic bar chart used to illustrate the threshold voltage of the storage unit MC that records 3 bits of data.

[0015] Figure 9 This is a flowchart for explaining the erasure operation of the memory die MD in the first embodiment.

[0016] Figure 10 This is a flowchart for explaining the erasure operation of the memory die MD in the first embodiment.

[0017] Figure 11 It is a timing diagram used to explain the erase voltage supply operation and the erase verification operation.

[0018] Figure 12 It is a schematic cross-sectional view used to illustrate the operation of erasing voltage supply.

[0019] Figure 13 It is a schematic cross-sectional view used to illustrate the erasure verification action.

[0020] Figure 14 It is a schematic cross-sectional view used to illustrate the erasure verification action.

[0021] Figure 15 This is a diagram used to illustrate the logical operation XOR.

[0022] Figure 16 This is a timing diagram used to explain the optimized erase voltage supply operation and erase verification operation of the first embodiment.

[0023] Figure 17 It is used for the number of cycles n in the first embodiment. E1 With erasure voltage V ERA A diagram illustrating the relationship.

[0024] Figure 18 This is a flowchart for explaining the erasure operation of the memory die MD in the second embodiment.

[0025] Figure 19 This is a timing diagram used to explain the optimized erase voltage supply operation and erase verification operation of the second embodiment.

[0026] Figure 20 It is used for the number of cycles n in the second embodiment. E1 and erase voltage V ERA A diagram illustrating the relationship.

[0027] Figure 21 This is a timing diagram used to explain the optimized erase voltage supply operation and erase verification operation of the third embodiment.

[0028] Figure 22 This is a flowchart for explaining the erasure operation of the memory die MD in the fourth embodiment.

[0029] Figure 23 This is a flowchart for explaining the erasure operation of the memory die MD in the fourth embodiment.

[0030] Figure 24 This is a flowchart for explaining the erasure operation of the memory die MD in the fifth embodiment. Detailed Implementation

[0031] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention.

[0032] Furthermore, in this specification, when we say "semiconductor memory device," it refers to both memory dies (memory chips) and memory systems that include controller dies, such as memory cards and SSDs (Solid State Drives). It also refers to devices that include a host computer, such as smartphones, tablets, and personal computers.

[0033] Furthermore, in this specification, when we say that the first component is "electrically connected" to the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an off state, the first transistor is "electrically connected" to the third transistor.

[0034] Additionally, in this specification, when we say that the first component is “connected” between the second and third components, it sometimes means that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0035] Furthermore, in this specification, when we say that a circuit or the like "connects" two wirings, for example, it sometimes means that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings and is in a switched-on state.

[0036] In addition, in this specification, the specified direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0037] In addition, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified surface is referred to as the third direction. The first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other.

[0038] Furthermore, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when we say the lower surface or lower end of a configuration, we mean the surface or end of that configuration on the substrate side; when we say the upper surface or upper end, we mean the surface or end of that configuration on the opposite side from the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0039] Additionally, in this specification, when we refer to the “width,” “length,” or “thickness” of a component or part in a specified direction, we sometimes mean the width, length, or thickness of a cross-section or the like as observed using SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0040] [First Implementation]

[0041] [Memory System 10]

[0042] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10.

[0043] The memory system 10 performs tasks such as reading, writing, and erasing user data based on signals sent from the host 20. The memory system 10 may be, for example, a memory chip, a memory card, an SSD, or other system capable of storing user data. The memory system 10 includes multiple memory dies (MDs) for storing user data, and a controller die (CD) connected to the multiple memory dies and the host 20. The controller die (CD) may include, for example, a processor, RAM (Random Access Memory), ROM (Read Only Memory), and ECC (Error Checking and Correcting) circuitry, performing processes such as logical address to physical address conversion, bit error detection / correction, and wear leveling.

[0044] [The structure of a memory die (MD)]

[0045] Figure 2 This is a schematic block diagram showing the configuration of the memory die MD in the first embodiment. Figure 3 This is a schematic circuit diagram representing a portion of a memory die (MD). Figure 4 It means Figure 3 A schematic circuit diagram of the configuration of the string component SU. Figure 5 This is a schematic block diagram showing the configuration of the sense amplifier module (SAM).

[0046] In addition, Figure 2 The diagram shows multiple control terminals. These control terminals may be shown as corresponding to a high-state active signal (positive logic signal), a low-state active signal (negative logic signal), or both a high-state active signal and a low-state active signal. Figure 2 In the diagram, the symbol for the control terminal corresponding to the active low-state signal includes an overline (hyperb). In this specification, the symbol for the control terminal corresponding to the active low-state signal includes a forward slash (" / ").

[0047] also, Figure 2The specific configuration can be adjusted as shown in the example. For instance, it is possible to make some or all of the high-state active signals low-state active signals, or to make some or all of the low-state active signals high-state active signals. Additionally, the following terminals RY / ( / BY) are for outputting a ready signal as a high-state active signal and a busy signal as a low-state active signal. The forward slash (" / ") between RY and ( / BY) indicates the separation between the ready signal and the busy signal.

[0048] like Figure 2 As shown, the memory die MD has a memory cell array MCA for storing data and peripheral circuitry PC connected to the memory cell array MCA.

[0049] [Circuit configuration of a memory cell array (MCA)]

[0050] like Figure 3 As shown, the memory cell array (MCA) has multiple memory blocks (BLK). Each memory block (BLK) has multiple string components (SU). Each string component (SU) has multiple memory strings (MS). One end of each memory string (MS) is connected to the peripheral circuitry (PC) via a bit line (BL). The other end of each memory string (MS) is connected to the peripheral circuitry (PC) via a common source line (SL).

[0051] The memory string (MS) has a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MCs) (memory cell transistors), and a source-side selection transistor (STS). Hereinafter, the drain-side selection transistor (STD) and the source-side selection transistor (STS) are sometimes referred to simply as selection transistors (STD, STS).

[0052] A memory cell (MC) is a field-effect transistor (memory transistor) that includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge storage film. The threshold voltage of the memory cell (MC) varies depending on the amount of charge in the charge storage film. A memory cell (MC) typically stores one or more bits of data. Furthermore, word lines (WL) are connected to the gate electrodes of multiple memory cells (MCs) corresponding to a memory string (MS). These word lines (WL) are collectively connected to all memory strings (MS) within a memory block (BLK).

[0053] A selection transistor (STD, STS) is a field-effect transistor comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of the selection transistor (STD, STS) is connected to a drain-side selection gate line (SGD) and a source-side selection gate line (SGS). The drain-side selection gate line (SGD) is provided corresponding to a string assembly (SU) and is commonly connected to all memory strings (MS) within a single string assembly (SU). The source-side selection gate line (SGS) is commonly connected to all memory strings (MS) within a memory block (BLK). Hereinafter, the drain-side selection gate line (SGD) and the source-side selection gate line (SGS) are sometimes simply referred to as the selection gate line (SGD, SGS).

[0054] [Number of word lines (WL) and bit lines in the string component SU]

[0055] like Figure 4 As shown, in this embodiment, the string assembly SU is connected to 2i word lines WL0 to WL2i-1. i is an integer greater than or equal to 1. The 2i word lines WL0 to WL2i-1 are the 1st to 2ith word lines WL counting from the source-side gate selection line SGS towards the drain-side gate selection line SGD. Furthermore, the 2i word lines WL0 to WL2i-1 are respectively connected to the gate electrodes of the 1st to 2ith memory cells MC0 to MC2i-1 in the memory string MS.

[0056] Sometimes, the odd-numbered word lines WL0, WL2, ..., WL2i-2 among the 2i word lines WL0 to WL2i-1 are called word lines WLodd. Conversely, the even-numbered word lines WL1, WL3, ..., WL2i-3, WL2i-1 among the 2i word lines WL0 to WL2i-1 are sometimes called word lines WLeven.

[0057] like Figure 4 As shown, in this embodiment, the string component SU is connected to m bit lines BL0 to BLm-1. m is an integer greater than or equal to 1. The m bit lines BL0 to BLm-1 are respectively connected to the first to the mth memory strings MS0 to MSm-1 in the string component SU.

[0058] [Circuit configuration of the peripheral circuit PC]

[0059] like Figure 2 As shown, the peripheral circuit PC includes a line decoder RD, a sense amplifier module SAM, a cache memory CM, a counter CNT, a voltage generation circuit VG, and a sequencer SQC. The peripheral circuit PC also includes an address register ADR, an instruction register CMR, and a status register STR. The peripheral circuit PC also includes input / output control circuitry (I / O) and logic circuitry CTR.

[0060] [The structure of the line decoder RD]

[0061] For example, like Figure 3 As shown, the line decoder RD( Figure 2 ) has address data D ADD ( Figure 2 Address decoder 22 performs decoding. Additionally, line decoder RD( Figure 2 It has a block selection circuit 23 and a voltage selection circuit 24 that transmit the operating voltage to the memory cell array MCA according to the output signal of the address decoder 22.

[0062] Address decoder 22 is connected to multiple block select lines BLKSEL and multiple voltage select lines 33. Address decoder 22, for example, is based on data from sequencer SQC (… Figure 2 The control signals are sequentially referenced by the address register ADR ( Figure 2 The row address RA of ).

[0063] The block select circuit 23 has multiple block select circuits 34 corresponding to the memory block BLK. Each block select circuit 34 has multiple block select transistors 35 corresponding to the word line WL and the select gate line (SGD, SGS).

[0064] The block select transistor 35 is, for example, a field-effect transistor. The drain electrode of the block select transistor 35 is electrically connected to the corresponding word line WL or select gate line (SGD, SGS). The source electrode of the block select transistor 35 is electrically connected to the voltage supply line 31 via wiring CG and voltage selection circuit 24. The gate electrode of the block select transistor 35 is commonly connected to the corresponding block select line BLKSEL.

[0065] The voltage selection circuit 24 includes multiple voltage selection sections 36 corresponding to word lines WL and select gate lines (SGD, SGS). Each of the multiple voltage selection sections 36 includes multiple voltage selection transistors 37. The voltage selection transistors 37 are, for example, field-effect transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS) via wiring CG and block selection circuit 23. The source terminals are electrically connected to the corresponding voltage supply lines 31. The gate electrodes are connected to the corresponding voltage selection lines 33.

[0066] [Composition of Sensing Amplifier Module (SAM) and Buffer Memory (CM)]

[0067] like Figure 5As shown, the sense amplifier module SAM has multiple sense amplifier components SAU0 to SAUm-1 corresponding to multiple bit lines BL0 to BLm-1. Each sense amplifier component SAU0 to SAUm-1 has a sense amplifier SA connected to the bit lines BL0 to BLm-1, a wiring LBUS connected to the sense amplifier SA, and latch circuits SDL, DL0 to DLk connected to the wiring LBUS. k is an integer greater than or equal to 1.

[0068] The sensing amplifier SA senses the data read from the storage cell MC. The latch circuits SDL, DL0 to DLk temporarily store the data sensed by the sensing amplifier SA. The wiring LBUS is connected to the wiring DBUS via the switching transistor DSW.

[0069] like Figure 5 As shown, the cache memory CM is connected to the DBUS wiring. The cache memory CM has multiple latch circuits XDL0 to XDLm-1 corresponding to multiple sense amplifier components SAU0 to SAUm-1. Data written to or read from the memory cell MC is stored in the multiple latch circuits XDL0 to XDLm-1 respectively.

[0070] Furthermore, during the write operation, the data DAT contained in the plurality of latch circuits XDL0 to XDLm-1 is sequentially transmitted to the latch circuits within the sense amplifier module SAM. Additionally, during the read and verification operations, the data contained in the latch circuits SDL and DL0 to DLk within the sense amplifier module SAM is sequentially transmitted to latch circuits XDL0 to XDLm-1. Furthermore, during the data output operation, the data DAT contained in latch circuits XDL0 to XDLm-1 is sequentially transmitted to the input / output control circuit I / O.

[0071] [Composition of the counter CNT]

[0072] Counter CNT( Figure 2 During verification actions, the number of "0" bits or "1" bits in the data sequentially transmitted from the latch circuits XDL0 to XDLm-1 of the cache memory CM is counted according to the control signal from the sequencer SQC.

[0073] [Construction of the voltage generation circuit VG]

[0074] For example, like Figure 3 As shown, the voltage generation circuit VG( Figure 2 The voltage generation circuit VG is connected to multiple voltage supply lines 31. It includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. These step-down and step-up circuits are respectively connected to the power supply voltage V. CC and grounding voltage VSS ( Figure 2 The voltage supply lines are as follows. The voltage generation circuit VG, for example, generates various operating voltages applied to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS) during read, write, and erase operations of the memory cell array MCA, based on control signals from the sequencer SQC, and simultaneously outputs these voltages to multiple voltage supply lines 31. The operating voltages output from the voltage supply lines 31 are appropriately adjusted according to the control signals from the sequencer SQC.

[0075] [Structure of Sequencer SQC]

[0076] Sequencer SQC ( Figure 2 According to the instruction data D stored in the instruction register CMR CMD The line decoder RD, sense amplifier module SAM, and voltage generation circuit VG output internal control signals. Additionally, the sequencer SQC outputs status data D representing the state of the memory die MD. ST Output the appropriate value to the status register STR.

[0077] Additionally, the sequencer SQC generates a ready / busy signal and outputs it to the RY / ( / BY) terminal. During the period when the RY / ( / BY) terminal is in the "L" (Low) state (busy period), access to the memory die MD is essentially disabled. Conversely, during the period when the RY / ( / BY) terminal is in the "H" (High) state (ready period), access to the memory die MD is permitted.

[0078] [Structure of the Address Register (ADR)]

[0079] like Figure 2 As shown, the address register ADR is connected to the input / output control circuit I / O and stores the address data D input from the input / output control circuit I / O. ADD The Address Register (ADR) may have multiple 8-bit register columns. These register columns, for example, store the address data D corresponding to the currently executing internal action, such as read, write, or erase operations. ADD .

[0080] In addition, address data D ADD For example, it contains the column address CA ( Figure 2 ) and row address RA ( Figure 2 The row address RA, for example, contains a specific outgoing memory block BLK. Figure 3 The block address of the specific output string element (SU) and the page address of the word line (WL), the memory plane address of the specific output memory cell array (MCA) (memory plane), and the chip address of the specific output memory die (MD).

[0081] [Structure of the Instruction Register (CMR)]

[0082] The instruction register (CMR) is connected to the input / output control circuit (I / O) and stores the instruction data (D) input from the I / O. CMD The instruction register (CMR) has, for example, at least one set of 8-bit register columns. The instruction data (D) is then transferred. CMD When stored in the instruction register CMR, a control signal is sent to the sequencer SQC.

[0083] [The structure of the status register STR]

[0084] The status register STR is connected to the input / output control circuit I / O and stores the status data D output to the input / output control circuit I / O. ST The status register STR, for example, has multiple 8-bit register columns. These register columns, for example, store status data D related to the internal action being performed, such as read, write, or erase operations. ST Additionally, register columns store, for example, the readiness / busy information of the memory cell array (MCA).

[0085] [Composition of Input / Output Control Circuit (I / O)]

[0086] Input / output control circuit I / O ( Figure 2 It has data signal input / output terminals DQ0~DQ7, data strobe signal input / output terminals DQS, / DQS, shift register, and buffer circuit.

[0087] Data input via data signal input / output terminals DQ0 to DQ7 is input from the buffer circuit to the cache memory CM, address register ADR, or instruction register CMR according to the internal control signals from the logic circuit CTR. Conversely, data output via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit according to the internal control signals from the logic circuit CTR.

[0088] Signals input via data strobe input / output terminals DQS and / DQS (e.g., data strobe signals and their complementary signals) are used when data is input via data signal input / output terminals DQ0 to DQ7. Data input via data signal input / output terminals DQ0 to DQ7 is loaded into a shift register within the input / output control circuit I / O at the rising edge of the voltage at data strobe input / output terminal DQS (input signal switching) and the falling edge of the voltage at data strobe input / output terminal / DQS (input signal switching), and at the falling edge of the voltage at data strobe input / output terminal DQS (input signal switching) and the rising edge of the voltage at data strobe input / output terminal / DQS (input signal switching).

[0089] [The structure of the logic circuit CTR]

[0090] Logic circuit CTR ( Figure 2 It has multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE, and logic circuits connected to these external control terminals. The logic circuit CTR receives external control signals from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and outputs internal control signals to the input / output control circuit (I / O) accordingly.

[0091] [Structure of memory die MD]

[0092] Figure 6 This is a schematic 3D diagram representing a portion of a memory die (MD). Figure 7 It means Figure 6 A schematic enlarged view comprising a portion of it. Furthermore, Figure 6 and Figure 7 This indicates an illustrative composition; the specific composition can be appropriately modified. Furthermore, in Figure 6 and Figure 7 In the text, a portion of the composition is omitted.

[0093] like Figure 6 As shown, the memory die MD includes a semiconductor substrate 100 and a transistor layer L disposed on the semiconductor substrate 100. TR and set in transistor layer L TR The upper storage cell array layer L MCA .

[0094] [Structure of semiconductor substrate 100]

[0095] The semiconductor substrate 100 is, for example, a single-crystal silicon (Si) semiconductor substrate containing P-type impurities. An N-type well containing N-type impurities such as phosphorus (P) is formed on a portion of the surface of the semiconductor substrate 100. Additionally, a P-type well containing P-type impurities such as boron (B) is formed on a portion of the surface of the N-type well. Furthermore, an insulating region 100I is formed on a portion of the surface of the semiconductor substrate 100.

[0096] [Transistor layer L] TR [Structure]

[0097] In transistor layer L TR Multiple transistors Tr are provided to form the peripheral circuit PC. The source region, drain region, and channel region of transistor Tr are disposed on the surface of semiconductor substrate 100. The gate electrode gc of transistor Tr is disposed on transistor layer L. TR In the plurality of transistors Tr, a contact CS is provided in the source region, drain region, and gate electrode gc. The plurality of contacts CS are connected via transistor layer L. TR The wiring D0, D1, and D2 in the circuit are connected to other transistors Tr and memory cell array layer L. MCA The composition, etc.

[0098] [Storage cell array layer L] MCA [Structure]

[0099] Storage cell array layer L MCA The device comprises multiple memory blocks BLK arranged alternately along the Y direction and multiple inter-block structures ST. Each memory block BLK comprises multiple conductive layers 110 and multiple insulating layers 101 arranged alternately along the Z direction, multiple semiconductor pillars 120 extending along the Z direction, and multiple gate insulating films 130 respectively disposed between the multiple conductive layers 110 and the multiple semiconductor pillars 120.

[0100] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction, and multiple layers are arranged in the Z direction. The conductive layer 110 may, for example, contain a multilayer film of titanium nitride (TiN) and tungsten (W), or it may contain polycrystalline silicon containing impurities such as phosphorus or boron.

[0101] Of the multiple conductive layers 110, one or more conductive layers 110 located at the bottom layer serve as the source-side selected gate line (SGS). Figure 3 The conductive layer 110 and its connected source-side selection transistors (STS) function as gate electrodes. Additionally, the multiple conductive layers 110 located above the conductive layer 110 serve as word lines (WL). Figure 3 ) and multiple storage units MC connected to it Figure 3The gate electrode of the transistor functions as a drain-side selected gate line (SGD) and a plurality of drain-side selected transistors (STDs) connected thereto. Additionally, one or more conductive layers 110 located above the conductive layer 110 serve as drain-side selected gate lines (SGD) and connected to them as a plurality of drain-side selected transistors (STDs). Figure 3 The gate electrode of the ) performs its function.

[0102] A conductive layer 112 is disposed below the conductive layer 110. The conductive layer 112 includes a semiconductor layer 113 connected to the lower end of the semiconductor pillar 120 and a conductive layer 114 connected to the lower surface of the semiconductor layer 113. The semiconductor layer 113 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 114 may, for example, contain a conductive layer of a metal such as tungsten (W), tungsten silicide, or other conductive layers. In addition, an insulating layer 101 such as silicon oxide (SiO2) is disposed between the conductive layer 112 and the conductive layer 110.

[0103] Conductive layer 112 serves as the source line SL ( Figure 3 ) to perform its function. Source line SL, for example, for memory cell arrays (MCA) Figure 3 All storage blocks (BLKs) contained in the ) have common settings.

[0104] Multiple semiconductor pillars 120 are arranged in the X and Y directions. The semiconductor pillars 120 are, for example, semiconductor films such as undoped polycrystalline silicon (Si). Each semiconductor pillar 120 has a generally cylindrical shape, with an insulating film 125, such as silicon oxide, disposed in its central portion. Furthermore, the outer peripheral surfaces of each semiconductor pillar 120 are surrounded by conductive layers 110. The lower end of each semiconductor pillar 120 is connected to the semiconductor layer 113 of the conductive layer 112. The upper end of each semiconductor pillar 120 is connected to the bit line BL via an impurity region 121 containing N-type impurities such as phosphorus (P) and contacts Ch and Cb. Each semiconductor pillar 120 serves as a memory string MS ( Figure 3 The multiple memory cells MC and the channel regions of the selection transistors STD and STS contained in the ) function.

[0105] For example, like Figure 7 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 deposited between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are insulating films such as silicon oxide. The charge storage film 132 is a film capable of storing charge, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120.

[0106] In addition, Figure 7The example shown is a gate insulating film 130 having a charge storage film 132 such as silicon nitride, but the gate insulating film 130 may also have a floating gate such as polysilicon containing N-type or P-type impurities.

[0107] For example, like Figure 6 As shown, the inter-block structure ST extends along the X and Z directions. The inter-block structure ST may include, for example, an insulating layer such as silicon oxide (SiO2). Alternatively, the inter-block structure ST may also include, for example, a conductive layer extending along the X and Z directions and connected to the conductive layer 112, and an insulating layer such as silicon oxide (SiO2) disposed on both sides of the conductive layer in the Y direction.

[0108] [Record the threshold voltage of the multi-bit memory cell MC]

[0109] Next, refer to Figure 8 The threshold voltage of the storage unit MC, which records multi-bit data, is explained. Figure 8 As an example, the threshold voltage of the storage cell MC that records 3 bits of data is shown.

[0110] Figure 8 (a) is a schematic bar chart illustrating the threshold voltage of the memory cell MC that records 3 bits of data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC. Figure 8 (b) is a table showing an example of the relationship between the threshold voltage of the storage unit MC that records 3 bits of data and the recorded data. Figure 8 (c) is another example of the relationship between the threshold voltage of the storage cell MC that records 3 bits of data and the recorded data.

[0111] exist Figure 8 In example (a), the threshold voltage of the memory cell MC is controlled to have 8 states. The threshold voltage of the memory cell MC controlled to the Er state is less than the erase verification voltage V. VFYEr Additionally, for example, the threshold voltage of the memory cell MC controlled in state A is greater than the verification voltage V. VFYA And less than the verification voltage V VFYB Additionally, for example, the threshold voltage of the memory cell MC controlled in state B is greater than the verification voltage V. VFYB And less than the verification voltage V VFYC Similarly, the threshold voltage of the memory cell MC controlled in states C to F is greater than the verification voltage V. VFYC ~Verification voltage V VFYF And less than the verification voltage V VFYD ~Verification voltage V VFYG Additionally, for example, the threshold voltage of the memory cell MC controlled in state G is greater than the verification voltage V. VFYGAnd less than the readout path voltage V READ .

[0112] In addition, Figure 8 In example (a), a readout voltage V is set between the threshold distribution corresponding to the Er state and the threshold distribution corresponding to the A state. CGAR Additionally, a readout voltage V is set between the threshold distribution corresponding to state A and the threshold distribution corresponding to state B. CGBR Similarly, readout voltages V are set between the threshold distribution corresponding to state B and the threshold distribution corresponding to state C, and between the threshold distribution corresponding to state F and the threshold distribution corresponding to state G. CGBR ~Read the voltage V CGGR .

[0113] For example, the Er state corresponds to the lowest threshold voltage. The memory cell MC in the Er state is, for example, the memory cell MC in the erase state. The memory cell MC in the Er state is, for example, assigned the data "111".

[0114] Furthermore, state A corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state Er. For example, data "101" is allocated to the storage cell MC in state A.

[0115] Furthermore, state B corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state A. For example, data "001" is allocated to the storage cell MC in state B.

[0116] Similarly, in the diagram, states C through G correspond to threshold voltages that are higher than the threshold voltages of states B through F. The storage cells MC for these states are, for example, assigned the data “011”, “010”, “110”, “100”, and “000”.

[0117] In addition, in such Figure 8 (b) In the illustrated allocation case, the data of the lower bit can be read through one read voltage V. CGDR To determine the median bit data, it can be obtained through three readout voltages V. CGAR V CGCR V CGFR To determine this, the data in the higher-order bit can be read through three readout voltages V. CGBR V CGER V CGGR This is used to make a judgment. Sometimes, such data allocation is called 1-3-3 encoding.

[0118] Furthermore, the number of bits, the number of states, and the data allocation for each state recorded in the storage unit MC can be changed appropriately.

[0119] For example, in such Figure 8(c) In the illustrated allocation case, the data of the lower bit can be read through one read voltage V. CGDR To determine this, the data in the median bit can be obtained through two readout voltages V. CGBR V CGFR To determine this, the data in the upper-level bit can be read through four readout voltages V. CGAR V CGCR V CGER V CGGR This is used to make a judgment. Sometimes, such data allocation is called 1-2-4 encoding.

[0120] [Erase action]

[0121] Next, the erasure operation of the semiconductor memory device in this embodiment will be described.

[0122] Figure 9 and Figure 10 This is a flowchart for explaining the erasure operation of the memory die MD in the first embodiment. Figure 11 It is a timing diagram used to explain the erase voltage supply operation and the erase verification operation. Figure 12 It is a schematic cross-sectional view used to illustrate the operation of erasing voltage supply. Figure 13 This is a schematic cross-sectional view used to illustrate the erase verification action for the even-numbered word line WLeven. Figure 14 This is a schematic cross-sectional view used to illustrate the erase verification action for the odd-numbered word line WLodd. Figure 15 This is a diagram used to illustrate the logical operation XOR. Figure 16 This is a timing diagram used to explain the optimized erase voltage supply operation and erase verification operation of the first embodiment. Figure 17 It is used for the number of cycles n in the first embodiment. E1 With erasure voltage V ERA A diagram illustrating the relationship.

[0123] Furthermore, the following description will illustrate an example of performing an erase operation on the storage block BLK that becomes the action object.

[0124] The erasure operation comprises multiple erasure loops. Each erasure loop includes actions to lower the threshold voltage of the memory cell MC (steps S103, S115, etc. described below) and actions to confirm the threshold voltage of the memory cell MC (steps S104, S105, etc. described below). In the erasure operation, for example, the following actions can be performed in the first to the a-th erasure loop (where a is an integer greater than or equal to 1): Figure 9 Steps S103 to S108 are executed in the (a+1)th to (b)th erasure loop (where b is an integer greater than or equal to a+1). Figure 10 Steps S111 to S115 and Figure 9 S104 to S106. The erasure cycle in the erasure operation of the second to fifth embodiments is also the same.

[0125] In step S101, for example, like Figure 9 As shown, the number of iterations n E1 Set to 1. Number of loops n E1 This is a variable representing the number of erase cycles. Additionally, the erase voltage V... ERA Set as the initial erase voltage V ERA0 This action, for example, in Figure 11 At time t101, the RY / ( / BY) signal can be changed to L, thereby disabling access to the chip.

[0126] In step S103, an erase voltage supply operation is performed. The erase voltage supply operation is as follows: a voltage V is supplied to word lines WL0~WL2i-1 (the odd-numbered word line WLodd and the even-numbered word line WLeven). WLEr And supply erase voltage V to bit line BL and source line SL. ERA This lowers the threshold voltage of the memory cell MC. This action, for example, occurs in... Figure 11 In the example, during the period from time t102 to time t103 ( Figure 11 The execution period of the erase voltage supply operation (1), and the period from time t108 to time t109. Figure 11 The erasure voltage supply action (2) is executed during the execution period.

[0127] In the process of erasing the voltage supply, for example, like Figure 11 and Figure 12 As shown, an erase voltage V is supplied to the bit line BL and the source line SL. ERA (This is the initial erase voltage V) ERA0 Erasure voltage V ERA For example, a voltage of around 17V to 25V.

[0128] Additionally, in the process of erasing the voltage supply, for example, like Figure 12 As shown, the gate line SGD is supplied with voltage V to the drain side. SG Voltage V SG Less than the erasure voltage V ERA This generates GIDL (Gate-Induced Drain Leakage) in the drain-side select transistor STD, producing electron-hole pairs. Additionally, electrons move to the bit line BL, and holes move to the memory cell MC.

[0129] Additionally, in the process of erasing the voltage supply, for example, like Figure 12As shown, a voltage V is supplied to the source-side gate lines SGS and SGSb. SG Voltage V SG "Less than the erase voltage V" ERA Therefore, GIDL is generated in the source-side selective transistors STS and STSb, and electron-hole pairs are generated. In addition, electrons move to the source line SL side, and holes move to the memory cell MC side.

[0130] Additionally, in the process of erasing the voltage supply, for example, like Figure 11 and Figure 12 As shown, a voltage V is supplied to word lines WL0 to WL2i-1 (the odd-numbered word line WLodd and the even-numbered word line WLeven). WLEr The voltage V WLEr For example, a voltage of approximately 0.5V. Furthermore, the voltage V... WLEr It can also be the ground voltage V SS (0V) can also be less than the ground voltage V SS The voltage is (0V). Therefore, holes in the channels of the semiconductor pillar 120 pass through the tunnel insulating film 131 ( Figure 7 ) tunneling to the charge storage membrane 132 ( Figure 7 This leads to a decrease in the threshold voltage of the memory cell MC.

[0131] In step S104 ( Figure 9 In the process, an erase verification operation is performed on the even-numbered word line WLeven (hereinafter referred to as the even-numbered erase verification operation). This even-numbered erase verification operation is used to detect the on / off state of the even-numbered memory cell MC and to detect whether the threshold voltage of the even-numbered memory cell MC has reached the target value. This operation is, for example, in... Figure 11 In the example, during the period from time t104 to time t105 ( Figure 11 The execution period of the erase verification action (1-1), and the period from time t110 to time t111 ( Figure 11 The erasure verification action (2-1) is executed during the execution period.

[0132] In even-numbered erase verification actions, such as... Figure 13 As shown, a voltage V is supplied to the bit line BL. DD Additionally, a voltage V is supplied to the source line SL. SRC Voltage V SRC It can be greater than the ground voltage V SS It can also be related to the ground voltage V SS Equal. Voltage V DD Greater than voltage V SRC .

[0133] Additionally, in even-numbered erase verification actions, such as... Figure 13 As shown, the gate line SGD is supplied with voltage V to the drain side. SG Voltage V SG Greater than voltage V DD Additionally, voltage V SG With voltage V DD The voltage difference is greater than the threshold voltage of the drain-side select transistor STD. Therefore, an electron channel is formed in the channel region of the drain-side select transistor STD, and the transfer voltage V... DD .

[0134] Additionally, in even-numbered erase verification actions, such as... Figure 13 As shown, a voltage V is supplied to the source-side gate lines SGS and SGSb. SG Voltage V SG Greater than voltage V SRC Additionally, voltage V SG With voltage V SRC The voltage difference is greater than the threshold voltage of the source-side select transistors STS and STSb. Therefore, an electron channel is formed in the channel region of the source-side select transistors STS and STSb, and the transport voltage V... SRC .

[0135] Additionally, in even-numbered erase verification actions, such as... Figure 13 As shown, the read path voltage V is supplied to the odd-numbered word line WLodd. READ Read the path voltage V READ Greater than voltage V DD V SRC Read the path voltage V READ For example, a voltage of around 6V. Additionally, regardless of the data recorded in the storage cell MC, the read path voltage V... READ With voltage V DD V SRC The voltage difference between the two cells is greater than the threshold voltage of the memory cell MC. Therefore, an electron channel is formed in the channel region of the odd-numbered memory cells MC0, MC2, ..., MC2i-2, and a voltage V is transferred to the even-numbered memory cells MC1, MC3, ..., MC2i-1. DD V SRC .

[0136] Additionally, in even-numbered erase verification actions, such as... Figure 13 As shown, the erase verification voltage V is supplied to the even-numbered select word line WLeven. VFYEr Erasure verification voltage V VFYEr Less than the readout path voltage V READ ( Figure 8 ). Erasure verification voltage VVFYEr For example, a voltage of around 1.0V. Therefore, as... Figure 13 As shown, the threshold voltage is the erase verification voltage V. VFYEr The following memory cell MC becomes active when the threshold voltage is greater than the erase verification voltage V. VFYEr The memory cell MC is in an off state. The signal is transmitted via the bit line BL through the sense amplifier module SAM (…). Figure 5 The system detects the on / off state of these memory cells (MCs) and acquires data representing the state of the MC. This action is called a "sensing action".

[0137] In sensing operations, for example, a voltage V is supplied to the alignment line BL. DD In the state of, make the sensing amplifier SA ( Figure 5 The sensing node and bit line BL are connected for a fixed period. After the sensing action is performed, the charge on the wiring LBUS is discharged or maintained according to the state of the sensing node. In addition, any latch circuit in the sensing amplifier assembly SAU is connected to the wiring LBUS, and the data of the wiring LBUS is latched by the latch circuit.

[0138] Data indicating the on / off state of the storage unit MC is transmitted via wiring LBUS, switching transistor DSW, and wiring DBUS ( Figure 5 The latch circuit XDL0~XDLm-1 that transmits data to the high-speed cache memory CM Figure 5 ).

[0139] The cache memory CM stores data in multiple latch circuits XDL0 to XDLm-1, representing the on / off state of the memory cells MC (here, the even-numbered memory cells MC1, MC3, ..., MC2i-1) corresponding to multiple bit lines BL0 to BLm-1.

[0140] For example, when all even-numbered memory cells MC1, MC3, ..., MC2i-1 corresponding to one bit line BL are in the ON state, the data "1" is stored in the latch circuit XDL corresponding to the bit line BL. The data "1" indicates that the data in all even-numbered memory cells MC1, MC3, ..., MC2i-1 corresponding to one bit line BL has been erased (that is, the threshold voltage of all even-numbered memory cells MC1, MC3, ..., MC2i-1 is the erase verification voltage V). VFYEr the following).

[0141] Additionally, for example, when at least one of the even-numbered memory cells MC1, MC3, ..., MC2i-1 corresponding to a bit line BL is in an off state, a "0" data is stored in the latch circuit XDL corresponding to the bit line BL. The "0" data indicates that the data in at least one of the even-numbered memory cells MC1, MC3, ..., MC2i-1 corresponding to the bit line BL has not been erased (that is, the threshold voltage of at least one of the even-numbered memory cells MC1, MC3, ..., MC2i-1 is greater than the erase verification voltage V). VFYEr ).

[0142] For example, with Figure 13 The five semiconductor pillars 120 shown are connected by bit lines BL0, BL1, BL2, BL3, and BL4, connecting the -X side to the +X side. In this case, the data stored in the latch circuits XDL0 to XDL4 is "1", "1", "1", "1", and "0". Hereinafter, the bits containing "1" data are sometimes referred to as bits indicating successful erasure. Conversely, the bits containing "0" data are sometimes referred to as bits indicating failed erasure.

[0143] In step S105 ( Figure 9 In the process, an erase verification operation is performed on the odd-numbered word line WLodd (hereinafter referred to as the odd-numbered erase verification operation). This odd-numbered erase verification operation is used to detect the on / off state of the odd-numbered memory cell MC and to detect whether the threshold voltage of the odd-numbered memory cell MC has reached the target value. This operation is, for example, in... Figure 11 In the example, during the period from time t106 to time t107 ( Figure 11 The execution period of the erase verification action (1-2), and the period from time t112 to time t113. Figure 11 The erasure verification action (2-2) is executed during the execution period.

[0144] The odd-number erase verification operation is basically the same as the even-number erase verification operation. However, as mentioned above, the even-number erase verification operation involves supplying the read path voltage V to the odd-numbered word line WLodd. READ The even-numbered word line WLeven is supplied with an erase verification voltage V. VFYEr ( Figure 13 On the other hand, odd-number erasure verification actions, such as... Figure 11 and Figure 14 As shown, the even-numbered word line WLeven is supplied with a read path voltage V. READ The erase verification voltage V is supplied to the odd-numbered word line WLodd. VFYEr .

[0145] For example, with Figure 14The five semiconductor pillars 120 shown are connected by bit lines BL0, BL1, BL2, BL3, and BL4 from the -X side to the +X side. In this case, the data stored in the latch circuits XDL0 to XDL4 is "1" "1" "1" "1" "1".

[0146] In step S106 ( Figure 9 In the process of erasure verification, the result of the erasure verification action is determined. For example, the data obtained by the even-number erasure verification action in step S104 (hereinafter referred to as even-number line data) is sequentially transferred from the latch circuits XDL0 to XDLm-1 to the counter CNT. Figure 2 The counter CNT counts the number of bits that failed to be erased in the even-digit data (the number of bits of "0" data). The counting of the number of bits that failed to be erased is performed at the end of step S104. The number of bits that failed to be erased is transmitted to the sequencer SQC. The sequencer SQC determines whether the number of bits that failed to be erased in the even-digit data is less than the first reference value Cr1.

[0147] In addition, the data obtained through the odd-number erasure verification action in step S105 (hereinafter referred to as odd-number line data) is sequentially transferred from the latch circuits XDL0 to XDLm-1 to the counter CNT ( Figure 2 The counter CNT counts the number of bits (the number of "0" bits) that failed to be erased in the odd-number line data. The counting of the failed-to-erase bits occurs at the end of step S105. The failed-to-erase bits are then transmitted to the sequencer SQC. The sequencer SQC determines whether the number of failed-to-erase bits in the odd-number line data is less than the first reference value Cr1.

[0148] When the number of even-numbered line data erasure failures is less than the first reference value Cr1, and the number of odd-numbered line data erasure failures is also less than the first reference value Cr1, the sequencer SQC determines that the verification is successful and proceeds to step S111. On the other hand, when the number of even-numbered line data erasure failures is greater than or equal to the first reference value Cr1, or when the number of odd-numbered line data erasure failures is greater than or equal to the first reference value Cr1, the sequencer SQC determines that the verification has failed and proceeds to step S107.

[0149] In step S107, the number of iterations n is determined. E1 Has the specified number of attempts (N) been reached? E1 If the condition is not met, proceed to step S108. If the condition is met, proceed to step S109.

[0150] In step S108, the number of iterations n is... E1 Add 1. Additionally, in step S108, the erase voltage V is... ERA Add an offset voltage ΔV1. Therefore, the erase voltage V ERAAs the number of loops n E1 The offset voltage ΔV1 is increased sequentially. Then, proceed to step S103.

[0151] In step S111, the XOR of the even-number line data and the odd-number line data is calculated. The XOR can be calculated, for example, using the sense amplifier module SAM.

[0152] For example, like Figure 15 As shown, assume the even-number and odd-number line data are 16 bits each. In this case, perform an XOR operation between the even-number line data "1111 0111 1111 1110" corresponding to bit lines BL0-BL15 and the odd-number line data "1111 1111 1111 1110" corresponding to bit lines BL0-BL15. In this example, the result of the XOR operation is "00001000 0000 0000".

[0153] The XOR result of each bit line BL0 to BLm-1 is transmitted to the latch circuit XDL0 to XDLm-1.

[0154] In step S112 ( Figure 10 In the sequencer, it is determined whether the number of inconsistencies between the even-number line data and the odd-number line data is less than the second reference value Cr2. The inconsistency bits between the even-number line data and the odd-number line data are the bits of "1" in the result of the XOR operation of the even-number line data and the odd-number line data. The counter CNT counts the number of inconsistencies (the number of "1"s) in the result data. The number of inconsistencies is transmitted to the sequencer SQC. The sequencer SQC determines whether the number of inconsistencies is less than the second reference value Cr2.

[0155] If the number of inconsistent bits is less than the second reference value Cr2, the sequencer SQC determines that the verification is successful and proceeds to step S110. Figure 9 On the other hand, if the number of inconsistent bits is greater than or equal to the second reference value Cr2, the sequencer SQC proceeds to step S113. Figure 10 ).

[0156] In step S113 ( Figure 10 In the loop, determine the number of iterations n. E1 Has the specified number of attempts (N) been reached? E1 If the condition is not met, proceed to step S114. If the condition is met, proceed to step S109. Figure 9 ).

[0157] In step S114 ( Figure 10 In ), the number of loops n E1 Add 1. Additionally, in step S114, the erase voltage V is...ERA Add the offset voltage ΔV2. Therefore, the erase voltage V ERA As the number of loops n E1 The offset voltage ΔV2 is increased successively as the voltage increases.

[0158] In step S115 ( Figure 10 In step S103, an optimized erase voltage supply operation is performed. This optimized erase voltage supply operation is similar to the erase voltage supply operation in step S103, namely, supplying voltage V to word lines WL0~WL2i-1 (the odd-numbered word line WLodd and the even-numbered word line WLeven). WLEr The erase voltage V is supplied to the bit line BL and the source line SL. ERA This reduces the threshold voltage of the memory cell MC.

[0159] However, during the voltage supply erasure operation, such as Figure 11 and Figure 17 As shown, each time the loop count n E1 When 1 is added, the erase voltage V is reduced. ERA Then the offset voltage ΔV1 is increased successively (steps S103, S108). On the other hand, in optimizing the erase voltage supply operation, such as Figure 16 and Figure 17 As shown, each time the loop count n E1 When 1 is added, the erase voltage V is reduced. ERA Then the offset voltage ΔV2 is increased successively (steps S114 and S115).

[0160] For example in Figure 17 In the example, when the number of loops n E1 When the value is 1, during the erase voltage supply operation, the initial erase voltage V is... ERA0 The supply is applied to the bit line BL and the source line SL. Then, each time the cycle number n... E1 When 1 is added, the erase voltage V is reduced. ERA The offset voltage ΔV1 is then gradually increased. The erase voltage supply operation is performed until the cycle number n is reached. E1 Up to time point 4. When the number of iterations n... E1 When the voltage is 5, the optimized erase voltage supply operation is performed. At this time, the erase voltage V... ERA It is the number of loops n E1 The erase voltage V when it is 4 ERA (=V ERA0 The voltage obtained by adding the offset voltage ΔV2 to +3ΔV1. The erase voltage V at this point... ERA Set as erase voltage V ERAS (=V ERA0 +3ΔV1+ΔV2). Then, whenever the number of iterations n E1 When 1 is added, the erase voltage V is reduced.ERA Then the offset voltage ΔV2 is increased successively.

[0161] The offset voltage ΔV2 is greater than the offset voltage ΔV1. For example, the offset voltage ΔV2 can also be about 2 to 3 times the offset voltage ΔV1. Therefore, optimizing the erase voltage supply operation makes it easier to reduce the threshold voltage of the memory cell MC than optimizing the erase voltage supply operation itself.

[0162] exist Figure 16 In the example, the optimized erase voltage supply action (1) occurs during the period from time t202 to time t203. Figure 16 The execution period of the optimized erase voltage supply action (1), and the period from time t208 to time t209 ( Figure 16 The optimized erase voltage supply action (2) is executed during the execution period. At the moment the optimized erase voltage supply action (1) is executed, the loop count n... E1 The value is 5, and the voltage V is erased. ERA For V ERAS (=V ERA0 +3ΔV1+ΔV2). Additionally, during the execution of the optimized erase voltage supply action (2), the number of cycles n... E1 The value is 6, and the erase voltage V is 6. ERA For V ERAS +ΔV2(=V ERA0 +3ΔV1+2ΔV2). Furthermore... Figure 16 The erase verification actions (1-1)(1-2)(2-1)(2-2) and Figure 11 The erase verification actions (1-1)(1-2)(2-1)(2-2) are the same.

[0163] After performing the optimized erase voltage supply action in step S115, the even-number erase verification action in step S104 and the odd-number erase verification action in step S105 are performed.

[0164] In step S109 ( Figure 9 The data DST, indicating that the erasure operation did not end properly, is stored in the status register STR. Figure 2 The erase operation is completed within the specified range. The RY / ( / BY) signal can be changed to H, thus enabling access to the chip.

[0165] In step S110 ( Figure 9 In the data, the content will be the status data D indicating that the erasure operation has been completed normally. ST Stored in the status register STR( Figure 2 The erase operation is completed within the specified range. The RY / ( / BY) signal can be changed to H, thus enabling access to the chip.

[0166] [Effect]

[0167] As the number of writes and erases in the memory cell array (MCA) increases, word lines (WL) may become faulty. When an erase voltage is supplied to the memory cell (MC) connected to such a word line (WL), it is sometimes difficult to effectively reduce the threshold voltage of the memory cell (MC).

[0168] Therefore, in Figure 9 and Figure 10 In the erasure operation, the threshold voltage of the memory cell MC corresponding to the word line WL of the even-numbered layer is determined by the erasure verification operation in step S104, which is lower than the erasure verification voltage V. VFYEr ( Figure 8 Additionally, the erase verification operation in step S105 determines whether the threshold voltage of the memory cell MC corresponding to the word line WL of the odd-numbered layer is lower than the erase verification voltage V. VFYEr ( Figure 8 ).

[0169] For example, suppose the word line WL that produces the defect as described above is the even-numbered word line WL. In this case, even if an erase voltage is supplied to the memory cell MC connected to such a word line WL, the threshold voltage is difficult to reduce. Therefore, even if the number of erase cycles n E1 As the number of erase failures detected in the erase verification operation of step S104 increases, it becomes difficult to reduce the number of bits. On the other hand, the threshold voltage of the memory cell MC connected to the word line WL that has not generated a fault continues to decrease. Therefore, if the number of erase cycles n E1 If the number of bits detected as failing to erase during the erase verification action in step S105 increases, the number of bits will decrease as usual.

[0170] In this situation, when both the even-numbered and odd-numbered line data are successfully verified in step S106, their contents can sometimes differ significantly. Therefore, by calculating the number of inconsistencies between the even-numbered and odd-numbered line data, defects such as those in the word line WL described above can be detected more effectively.

[0171] Here, for example, we also consider step S112 ( Figure 10 If the number of inconsistent bits in the memory is greater than or equal to the second reference value Cr2 (No in step S112), the memory block BLK, which is the target of the erasure operation, will be immediately determined as a bad memory block and will not be used in subsequent operations.

[0172] However, there are also cases where, even if the characteristics of the word line WL are slightly degraded, the threshold voltage of the memory cell MC can be reduced by further performing an erase voltage supply operation on the memory cell MC connected to such word line WL. Therefore, when a defective word line WL is detected in step S112, if the memory block BLK to be operated on is immediately set as a defective memory block BLK, then sometimes such memory block BLK cannot be effectively utilized.

[0173] Therefore, in the erasure operation of the first embodiment, an optimized erasure voltage supply operation is performed in step S115. The erasure voltage V in this optimized erasure voltage supply operation... ERA like Figure 16 and Figure 17 As shown, the erase voltage V during the erase voltage supply operation is... ERA This results in a faster increase. Therefore, optimizing the erase voltage supply action makes it easier to lower the threshold voltage of the memory cell (MC) than optimizing the erase voltage supply action itself. As a result, the number of memory blocks (BLKs) identified as bad memory blocks (BLKs) is suppressed, and BLKs can be utilized more effectively.

[0174] [Second Implementation]

[0175] In the first embodiment, by making the offset voltage ΔV2 greater than the offset voltage ΔV1, the optimized erase voltage supply operation makes it easier to reduce the threshold voltage of the memory cell MC than the erase voltage supply operation. In contrast, in the second embodiment, by making the erase voltage V in the optimized erase voltage supply operation... ERA The supply time is longer than the erase voltage V during the erase voltage supply operation. ERA The supply time makes it easier to reduce the threshold voltage of the memory cell MC by optimizing the erase voltage supply action compared to the erase voltage supply action.

[0176] Figure 18 This is a flowchart for explaining the erasure operation of the memory die MD in the second embodiment. Figure 19 This is a timing diagram used to explain the optimized erase voltage supply operation and erase verification operation of the second embodiment. Figure 20 It is used for the number of cycles n in the second embodiment. E1 and erase voltage V ERA A diagram illustrating the relationship.

[0177] Furthermore, in the erasure operation of the second embodiment, the same as the erasure operation of the first embodiment is performed. Figure 9 Steps S101 to S110. Additionally... Figure 18 Steps S111 to S113 and Figure 10 Steps S111 to S113 are the same. Therefore, detailed descriptions of these processes are omitted.

[0178] In step S113 of the erasure operation in the second embodiment, as follows Figure 18 As shown, when the number of iterations n E1 The required number of times N was not reached. E1 Then, proceed to step S114A. In step S114A, the loop count n is... E1 Add 1. Additionally, in step S114A, the erase voltage V is... ERA An offset voltage ΔV1 is applied. Additionally, in step S114A, the erasure voltage V is applied. ERA The supply time changes from time T1 to time T2.

[0179] In step S115A, the optimized erase voltage supply operation of the second embodiment is performed. In the optimized erase voltage supply operation of the second embodiment, similar to the optimized erase voltage supply operation of the first embodiment in step S115, a voltage V is supplied to word lines WL0 to WL2i-1 (the odd-numbered word line WLodd and the even-numbered word line WLeven). WLEr The erase voltage V is supplied to the bit line BL and the source line SL. ERA This reduces the threshold voltage of the memory cell MC.

[0180] Here, in the action of erasing voltage supply ( Figure 9 In step S103), such as Figure 11 and Figure 17 As shown, the erasure voltage V ERA The supply time (pulse width) is time T1. On the other hand, in the optimized erase voltage supply operation of the second embodiment ( Figure 18 In step S115A), such as Figure 19 and Figure 20 As shown, the erasure voltage V ERA The supply time (pulse width) is time T2 (=T1+ΔT) (steps S114A, S115A).

[0181] For example in Figure 20 In the example, when the number of loops n E1 When the value is 1 to 4, during the erase voltage supply operation, the erase voltage V ERA The supply time is time T1. Additionally, when the number of cycles n... E1 When the voltage is between 5 and 8, during the optimized erase voltage supply operation, the erase voltage V... ERA The supply time is time T2 (=T1+ΔT).

[0182] Furthermore, in the optimized erase voltage supply operation of the second embodiment, such as Figure 19 and Figure 20 As shown, each time the loop count nE1 When 1 is added, the erase voltage V is reduced. ERA Then the offset voltage ΔV1 is increased successively (steps S114A, S115A).

[0183] exist Figure 19 In the example, the optimized erase voltage supply action (1) occurs during the period from time t302 to time t303. Figure 19 The execution period of the optimized erase voltage supply action (1), and the period from time t308 to time t309. Figure 19 The optimized erase voltage supply action (2) is executed during the execution period. At the moment the optimized erase voltage supply action (1) is executed, the loop count n... E1 The value is 5, and the voltage V is erased. ERA For V ERAT (=V ERA0 +4ΔV1). Additionally, during the execution of the optimized erase voltage supply action (2), the number of cycles n E1 The value is 6, and the erase voltage V is 6. ERA For V ERAT +ΔV1(=V ERA0 +5ΔV1). Furthermore... Figure 19 The erase verification actions (1-1)(1-2)(2-1)(2-2) and Figure 11 The erase verification actions (1-1)(1-2)(2-1)(2-2) are the same.

[0184] After performing the optimized erase voltage supply action in step S115A, the even-number erase verification action in step S104 and the odd-number erase verification action in step S105 are performed.

[0185] The second implementation is similar to the first implementation, but optimizing the erase voltage supply operation makes it easier to reduce the threshold voltage of the memory cell (MC) than optimizing the erase voltage supply operation. As a result, the generation of bad memory blocks (BLKs) is suppressed, and BLKs can be utilized as effectively as possible.

[0186] [Third Implementation]

[0187] In the third embodiment, by making the offset voltage ΔV2 greater than the offset voltage ΔV1, and by making the voltage V supplied to the odd-numbered word line WLodd or the even-numbered word line WLeven greater than the offset voltage ΔV1, the voltage V is increased. WLEr Reduce offset voltage ΔV WL This makes it easier to lower the threshold voltage of the memory cell MC.

[0188] Figure 21 This is a timing diagram used to explain the optimized erase voltage supply operation and erase verification operation of the third embodiment. Furthermore, the erase operation of the third embodiment is related to... Figure 9 and Figure 10 Steps S101 to S115 are the same. Therefore, the description of the processes that are the same as in the first embodiment is omitted.

[0189] As described above, in step S106 ( Figure 9 In the sequencer, the counter CNT counts the number of bits that failed to erase in the even-number data (the number of bits of "0" data). These failed erasure bits are transmitted to the sequencer SQC. The sequencer SQC determines whether the number of failed erasure bits in the even-number data is less than the first reference value Cr1. Conversely, the counter CNT also counts the number of bits that failed to erase in the odd-number data (the number of bits of "0" data). These failed erasure bits are transmitted to the sequencer SQC. The sequencer SQC determines whether the number of failed erasure bits in the odd-number data is less than the first reference value Cr1.

[0190] Here, in the semiconductor memory device of the third embodiment, the sequencer SQC determines whether the number of bits in the even-numbered word line data that failed to erase or the number of bits in the odd-numbered word line data that failed to erase is greater. If the number of bits in the even-numbered word line data that failed to erase is greater, the sequencer SQC decides to reduce the voltage V supplied to the even-numbered word line WLeven. WLEr When a large number of bits fail to be erased on the odd-numbered word line, the sequencer SQC decides to reduce the voltage V supplied to the odd-numbered word line WLodd. WLEr .

[0191] Next, for step S115 ( Figure 10 The optimized erase voltage supply operation will be explained. For example, when it is decided to reduce the voltage V supplied to the even-numbered word line WLeven... WLEr At times, such as Figure 21 As shown, a specific voltage V is supplied to the even-numbered word line WLeven. WLEr Small offset voltage ΔV WL The voltage. Additionally, a voltage V is supplied to the odd-numbered word line WLodd. WLEr Additionally, for example, when deciding to reduce the voltage V supplied to the odd-numbered word line WLodd. WLEr At that time, a voltage V is supplied to the odd-numbered word line WLodd. WLEr Small offset voltage ΔV WL The voltage. Additionally, a voltage V is supplied to the even-numbered word line WLeven. WLEr Therefore, in the optimized erase voltage supply operation of the third embodiment, it is easier to reduce the threshold voltage of the memory cell MC. As a result, the generation of bad memory blocks (BLKs) is suppressed, and BLKs can be utilized as effectively as possible.

[0192] [Fourth Implementation]

[0193] Figure 22 and Figure 23 This is a flowchart illustrating the erasure operation of the memory die (MD) in the fourth embodiment. Furthermore, in Figure 22 In Figure 9 Step S102 is added after step S101. Additionally, in Figure 23 In, replacing Figure 10 Steps S113 and S114 are executed, and steps S113B and S114B are performed.

[0194] In step S102, for example, like Figure 22 As shown, the number of iterations n E2 Set to 1. Number of loops n E2 It is related to the number of loops n E2 Different variables represent the number of times the erase loop is executed.

[0195] In step S113B, the number of loops n is determined. E2 Has the specified number of attempts (N) been reached? E2 If the condition is not met, proceed to step S114B. If the condition is met, proceed to step S109.

[0196] In step S114B, the number of iterations n is... E2 Add 1. Additionally, in step S114B, the erase voltage V is... ERA Add the offset voltage ΔV2. Therefore, the erasure voltage V ERA As the number of loops n E2 The offset voltage ΔV2 is increased successively as the voltage increases.

[0197] In the first embodiment, the number of times the erase voltage supply action (step S103) and the optimized erase voltage supply action (step S115) are executed (number of loops n) E1 The upper limit of the number of times is N. E1 (Steps S107, S113). In contrast, in the fourth embodiment, the number of times the voltage supply erasure operation (step S103) is executed (number of cycles n) is recorded. E1 The upper limit of the number of times is N. E1 (Step S107) Optimize the number of executions (loop count n) of the voltage supply erasure action (step S115). E2 The upper limit of the number of times is N. E2 (S113B).

[0198] Based on this configuration, the number of times the voltage supply erasure action (step S103) is executed (number of cycles n) can be managed separately. E1 The number of times the optimized erase voltage supply action (step S115) is executed (number of loops n) E2 ).

[0199] [Fifth Implementation]

[0200] Figure 24 This is a flowchart illustrating the erasure operation of the memory die (MD) in the fifth embodiment. Furthermore, in Figure 24 In Figure 10 Step S201 is added before step S111.

[0201] In the fifth embodiment, the user can set whether the XOR calculation (step S111), the determination of inconsistent bits (step S112), and the execution / non-execution of the optimized erase voltage supply operation (step S115) are possible or not. For example, the host 20 sends data indicating whether it is possible or not to be executed to the controller die CD. The controller die CD sends the data indicating whether it is possible or not to be executed from the host 20 to the memory die MD. In the memory die MD, when the input / output control circuit I / O inputs data indicating whether it is possible or not to be executed, the data is output to, for example, the sequencer SQC. The sequencer SQC stores the data indicating whether it is possible or not to be executed in a designated register.

[0202] In step S201, the sequencer SQC determines whether to set it as executable based on data indicating whether it can be executed or not. If it is determined that it can be executed, step S111 and subsequent processing are executed. If it is determined that it cannot be executed, step S111 and subsequent processing are not executed, and the process proceeds to step S110.

[0203] Based on this configuration, the ability to perform / not perform XOR calculations (step S111), determine inconsistent bit values ​​(step S112), and optimize the erase voltage supply operation (step S115) can be configured according to the user's usage of the memory system 10. Furthermore, the configuration can also be configured so that the user can set whether the optimized erase voltage supply operation (step S115) can be performed or not.

[0204] [Other Implementation Methods]

[0205] The semiconductor memory device according to the embodiments has been described above. However, the above description is merely illustrative, and the configuration or method can be appropriately adjusted.

[0206] For example, the following example is shown: when the erase voltage supply operation and the optimized erase voltage supply operation in embodiments 1 to 5 are performed, an erase voltage V is supplied to both the bit line BL and the source line SL. ERA However, when performing the erase voltage supply operation and optimizing the erase voltage supply operation, it is also possible to omit the supply of erase voltage V to either the bit line BL or the source line SL. ERA .

[0207] Alternatively, the configurations of embodiments 1 to 5 can be appropriately combined. For example, the optimized erase voltage supply operations of embodiments 1 and 2 can be combined. In this case, during the optimized erase voltage supply operation, the erase voltage V... ERA The supply time changes from time T1 to time T2, and every time the number of cycles n... E1 When increased, the erase voltage V will be applied. ERA Add the offset voltage ΔV2. Alternatively, the optimized erase voltage supply operations of the second and third embodiments can be combined. In this case, during the optimized erase voltage supply operation, the erase voltage V... ERA The supply time changes from time T1 to time T2, and every time the number of cycles n... E1 When increased, the erase voltage V will be applied. ERA With the offset voltage ΔV1 applied, the voltage V supplied to the even-numbered word line WLeven or the odd-numbered word line WLodd is... WLEr Reduce offset voltage ΔV WL Alternatively, the optimized erase voltage supply operations of embodiments 1 to 3 can be combined. In this case, during the optimized erase voltage supply operation, the erase voltage V... ERA The supply time changes from time T1 to time T2, and every time the number of cycles n... E1 When increased, the erase voltage V will be applied. ERA With the offset voltage ΔV2 applied, the voltage V supplied to the even-numbered word line WLeven or the odd-numbered word line WLodd is... WLEr Reduce offset voltage ΔV WL Furthermore, embodiments 1 to 4 can be combined, and embodiments 1 to 5 can also be combined.

[0208] [other]

[0209] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

[0210] [Explanation of Symbols]

[0211] MC storage unit

[0212] MCA storage cell array

[0213] PC peripheral circuits (control circuits)

[0214] WL lettering (conductive layer, first conductive layer, second conductive layer)

[0215] WLeven, the even-numbered word line

[0216] WLodd, the odd-numbered word line

[0217] BL bit line (first wiring)

[0218] SL source line (first wiring)

[0219] 120 Semiconductor Layer

[0220] 130 Charge storage layer.

Claims

1. A semiconductor memory device comprising: Substrate; Multiple conductive layers are arranged along a first direction intersecting the surface of the substrate; The first semiconductor layer extends along the first direction and faces the plurality of conductive layers; A charge storage layer is disposed between the plurality of conductive layers and the first semiconductor layer; The first wiring is connected to one end of the first semiconductor layer in the first direction; and The control circuit is electrically connected to the plurality of conductive layers and the first wiring. The control circuit is configured to perform an erasure action. The erasure action includes multiple erasure cycles. The plurality of erasure cycles each include: The erase voltage supply operation supplies an erase voltage to the first wiring; The first erase verification action involves, after performing the erase voltage supply action, supplying a first readout path voltage smaller than the erase voltage to a first conductive layer (one of the plurality of conductive layers), and supplying a first erase verification voltage smaller than the first readout path voltage to a second conductive layer (one of the plurality of conductive layers); and The second erase verification action involves supplying a second erase verification voltage to the first conductive layer and a second readout path voltage to the second conductive layer after the first erase verification action is performed. From the first erase cycle to the a-th erase cycle, the erase voltage increases by the first offset voltage each time, where a is an integer greater than or equal to 1. From the (a+1)th erase cycle to the bth erase cycle, the erase voltage increases by the second offset voltage each time, where b is an integer greater than or equal to a+1. The second offset voltage is greater than the first offset voltage. From the first erase cycle to the a-th erase cycle, during the first supply time, the erase voltage is supplied to the first wiring. From the (a+1)th erase cycle to the bth erase cycle, during the second supply time, the erase voltage is supplied to the first wiring, and The second supply time is longer than the first supply time.

2. A semiconductor memory device comprising: Substrate; Multiple conductive layers are arranged along a first direction intersecting the surface of the substrate; The first semiconductor layer extends along the first direction and faces the plurality of conductive layers; A charge storage layer is disposed between the plurality of conductive layers and the first semiconductor layer; The first wiring is connected to one end of the first semiconductor layer in the first direction; and The control circuit is electrically connected to the plurality of conductive layers and the first wiring. The control circuit is configured to perform an erasure action. The erasure action includes multiple erasure cycles. The plurality of erasure cycles each include: The erase voltage supply operation supplies an erase voltage to the first wiring; The first erase verification action involves, after performing the erase voltage supply action, supplying a first readout path voltage smaller than the erase voltage to a first conductive layer (one of the plurality of conductive layers), and supplying a first erase verification voltage smaller than the first readout path voltage to a second conductive layer (one of the plurality of conductive layers); and The second erase verification action involves supplying a second erase verification voltage to the first conductive layer and a second readout path voltage to the second conductive layer after the first erase verification action is performed. From the first erase cycle to the a-th erase cycle, the erase voltage increases by the first offset voltage each time, where a is an integer greater than or equal to 1. From the (a+1)th erase cycle to the bth erase cycle, the erase voltage increases by the second offset voltage each time, where b is an integer greater than or equal to a+1. The second offset voltage is greater than the first offset voltage. The erase voltage supply operation from the first erase cycle to the a-th erase cycle involves supplying a first voltage, smaller than the erase voltage, to the first conductive layer and the second conductive layer. The erase voltage supply action from the (a+1)th erase cycle to the bth erase cycle involves supplying the first voltage to one of the first conductive layer and the second conductive layer, and supplying the other with a second voltage that is smaller than the first voltage.

3. A semiconductor memory device comprising: Substrate; Multiple conductive layers are arranged along a first direction intersecting the surface of the substrate; The first semiconductor layer extends along the first direction and faces the plurality of conductive layers; A charge storage layer is disposed between the plurality of conductive layers and the first semiconductor layer; The first wiring is connected to one end of the first semiconductor layer in the first direction; and The control circuit is electrically connected to the plurality of conductive layers and the first wiring. The control circuit is configured to perform an erasure action. The erasure action includes multiple erasure cycles. The plurality of erasure cycles each include: The erase voltage supply operation supplies an erase voltage to the first wiring; The first erase verification action involves, after performing the erase voltage supply action, supplying a first readout path voltage smaller than the erase voltage to a first conductive layer (one of the plurality of conductive layers), and supplying a first erase verification voltage smaller than the first readout path voltage to a second conductive layer (one of the plurality of conductive layers); and The second erase verification action involves supplying a second erase verification voltage to the first conductive layer and a second readout path voltage to the second conductive layer after the first erase verification action is performed. From the first erase cycle to the a-th erase cycle, the erase voltage increases by the first offset voltage each time, where a is an integer greater than or equal to 1. From the (a+1)th erase cycle to the bth erase cycle, the erase voltage increases by the second offset voltage each time, where b is an integer greater than or equal to a+1. The second offset voltage is greater than the first offset voltage. The data obtained through the first erasure verification action is set as the first result data. When the data obtained through the second erasure verification action is set as the second result data, The first result data and the second result data respectively include first data corresponding to the bits that were successfully erased and second data corresponding to the bits that were erased but failed to be erased. The plurality of erase cycles each include at least one of the first determination action and the second determination action. The first determination action is to determine whether the number of the second data contained in the first result data and the second result data is within a first reference value, and the second determination action is to determine whether the number of inconsistent bits between the first result data and the second result data is within a second reference value.

4. The semiconductor memory device according to claim 3, wherein Among the plurality of conductive layers The even-numbered conductive layer counting from the side closest to the first wiring is designated as a plurality of third conductive layers. When the odd-numbered conductive layer counting from the side closest to the first wiring is designated as multiple fourth conductive layers, The first determination action, The number of the second data contained in the first result data is compared with the number of the second data contained in the second result data. The erase voltage supply action When the number of second data corresponding to one of the plurality of third conductive layers and the plurality of fourth conductive layers is large, a first voltage smaller than the erase voltage is supplied to another of the plurality of third conductive layers and the plurality of fourth conductive layers, and a second voltage smaller than the first voltage is supplied to one of the plurality of third conductive layers and the plurality of fourth conductive layers.

5. The semiconductor memory device according to claim 3, wherein The control circuit includes: The arithmetic circuit calculates the XOR of the result data of the first erasure verification action and the result data of the second erasure verification action; and A counter is used to count the data in the arithmetic circuit.

6. The semiconductor memory device according to claim 5, wherein The XOR operation includes a third data point corresponding to the consistent bits of the result data of the first erasure verification action and the result data of the second erasure verification action, and a fourth data point corresponding to the inconsistencies. The counter determines whether the number of the fourth data included in the XOR operation is within the third reference value.

7. A semiconductor memory device comprising: Substrate; Multiple conductive layers are arranged along a first direction intersecting the surface of the substrate; The first semiconductor layer extends along the first direction and faces the plurality of conductive layers; A charge storage layer is disposed between the plurality of conductive layers and the first semiconductor layer; The first wiring is connected to one end of the first semiconductor layer in the first direction; The control circuit is electrically connected to the plurality of conductive layers and the first wiring; and Setting Department; The control circuit is configured to perform an erasure action. The erasure action includes multiple erasure cycles. The plurality of erasure cycles each include: The erase voltage supply operation supplies an erase voltage to the first wiring; The first erase verification action involves, after performing the erase voltage supply action, supplying a first readout path voltage smaller than the erase voltage to a first conductive layer, which is one of the plurality of conductive layers, and supplying a first erase verification voltage smaller than the first readout path voltage to a second conductive layer, which is one of the plurality of conductive layers; and The second erase verification action involves supplying a second erase verification voltage to the first conductive layer and a second readout path voltage to the second conductive layer after the first erase verification action is performed. From the first erase cycle to the a-th erase cycle, the erase voltage increases by the first offset voltage each time, where a is an integer greater than or equal to 1. From the (a+1)th erase cycle to the bth erase cycle, the erase voltage increases by the second offset voltage each time, where b is an integer greater than or equal to a+1. The second offset voltage is greater than the first offset voltage. The setting unit determines whether the erase voltage supply operation can or cannot be performed in the (a+1)th erase cycle to the bth erase cycle.

8. A semiconductor memory device comprising: Substrate; Multiple conductive layers are arranged along a first direction intersecting the surface of the substrate; The first semiconductor layer extends along the first direction and faces the plurality of conductive layers; A charge storage layer is disposed between the plurality of conductive layers and the first semiconductor layer; The first wiring is connected to one end of the first semiconductor layer in the first direction; and The control circuit is electrically connected to the plurality of conductive layers and the first wiring. The control circuit is configured to perform an erasure action. The erasure action includes multiple erasure cycles. The plurality of erasure cycles each include: The erase voltage supply operation supplies an erase voltage to the first wiring; The first erase verification action involves, after performing the erase voltage supply action, supplying a first readout path voltage smaller than the erase voltage to a first conductive layer, which is one of the plurality of conductive layers, and supplying an erase verification voltage smaller than the first readout path voltage to a second conductive layer, which is one of the plurality of conductive layers; and The second erase verification action involves supplying the erase verification voltage to the first conductive layer and the second readout path voltage to the second conductive layer after the first erase verification action is performed. From the first erase cycle to the a-th erase cycle, during the first supply time, the erase voltage is supplied to the first wiring, where a is an integer greater than or equal to 1. From the (a+1)th erase cycle to the bth erase cycle, during the second supply time, the erase voltage is supplied to the first wiring, where b is an integer greater than or equal to a+1. The second supply time is longer than the first supply time. The erase voltage supply operation from the first erase cycle to the a-th erase cycle involves supplying a first voltage, smaller than the erase voltage, to the first conductive layer and the second conductive layer. The erase voltage supply action from the (a+1)th erase cycle to the bth erase cycle involves supplying the first voltage to one of the first conductive layer and the second conductive layer, and supplying the other with a second voltage that is smaller than the first voltage.

9. A semiconductor memory device comprising: Substrate; Multiple conductive layers are arranged along a first direction intersecting the surface of the substrate; The first semiconductor layer extends along the first direction and faces the plurality of conductive layers; A charge storage layer is disposed between the plurality of conductive layers and the first semiconductor layer; The first wiring is connected to one end of the first semiconductor layer in the first direction; and The control circuit is electrically connected to the plurality of conductive layers and the first wiring. The control circuit is configured to perform an erasure action. The erasure action includes multiple erasure cycles. The plurality of erasure cycles each include: The erase voltage supply operation supplies an erase voltage to the first wiring; The first erase verification action involves, after performing the erase voltage supply action, supplying a first readout path voltage smaller than the erase voltage to a first conductive layer, which is one of the plurality of conductive layers, and supplying an erase verification voltage smaller than the first readout path voltage to a second conductive layer, which is one of the plurality of conductive layers; and The second erase verification action involves supplying the erase verification voltage to the first conductive layer and the second readout path voltage to the second conductive layer after the first erase verification action is performed. From the first erase cycle to the a-th erase cycle, during the first supply time, the erase voltage is supplied to the first wiring, where a is an integer greater than or equal to 1. From the (a+1)th erase cycle to the bth erase cycle, during the second supply time, the erase voltage is supplied to the first wiring, where b is an integer greater than or equal to a+1. The second supply time is longer than the first supply time. The data obtained through the first erasure verification action is set as the first result data. When the data obtained through the second erasure verification action is set as the second result data, The first result data and the second result data respectively include first data corresponding to the bits that were successfully erased and second data corresponding to the bits that were erased but failed to be erased. The plurality of erase cycles each include at least one of the first determination action and the second determination action. The first determination action is to determine whether the quantity of the second data contained in the first result data and the second result data is within a first benchmark value. The second determination action is to determine whether the number of inconsistencies between the first result data and the second result data is within a second reference value.

10. The semiconductor memory device according to claim 9, wherein Among the plurality of conductive layers The even-numbered conductive layer counting from the side closest to the first wiring is designated as a plurality of third conductive layers. When the odd-numbered conductive layer counting from the side closest to the first wiring is designated as multiple fourth conductive layers, The first determination action, The number of the second data contained in the first result data is compared with the number of the second data contained in the second result data. The erase voltage supply action When the number of second data corresponding to one of the plurality of third conductive layers and the plurality of fourth conductive layers is large, a first voltage smaller than the erase voltage is supplied to another of the plurality of third conductive layers and the plurality of fourth conductive layers, and a second voltage smaller than the first voltage is supplied to one of the plurality of third conductive layers and the plurality of fourth conductive layers.

11. The semiconductor memory device according to claim 9, wherein The control circuit includes: The arithmetic circuit calculates the XOR of the result data of the first erasure verification action and the result data of the second erasure verification action; and A counter is used to count the data in the arithmetic circuit.

12. The semiconductor memory device according to claim 11, wherein The XOR operation includes a third data point corresponding to the consistent bits of the result data of the first erasure verification action and the result data of the second erasure verification action, and a fourth data point corresponding to the inconsistencies. The counter determines whether the number of the fourth data included in the XOR operation is within the third reference value.

13. A semiconductor memory device comprising: Substrate; Multiple conductive layers are arranged along a first direction intersecting the surface of the substrate; The first semiconductor layer extends along the first direction and faces the plurality of conductive layers; A charge storage layer is disposed between the plurality of conductive layers and the first semiconductor layer; The first wiring is connected to one end of the first semiconductor layer in the first direction; The control circuit is electrically connected to the plurality of conductive layers and the first wiring; and Setting Department; The control circuit is configured to perform an erasure action. The erasure action includes multiple erasure cycles. The plurality of erasure cycles each include: The erase voltage supply operation supplies an erase voltage to the first wiring; The first erase verification action involves, after performing the erase voltage supply action, supplying a first readout path voltage smaller than the erase voltage to a first conductive layer, which is one of the plurality of conductive layers, and supplying an erase verification voltage smaller than the first readout path voltage to a second conductive layer, which is one of the plurality of conductive layers; and The second erase verification action involves supplying the erase verification voltage to the first conductive layer and the second readout path voltage to the second conductive layer after the first erase verification action is performed. From the first erase cycle to the a-th erase cycle, during the first supply time, the erase voltage is supplied to the first wiring, where a is an integer greater than or equal to 1. From the (a+1)th erase cycle to the bth erase cycle, during the second supply time, the erase voltage is supplied to the first wiring, where b is an integer greater than or equal to a+1. The second supply time is longer than the first supply time. The setting unit determines whether the erase voltage supply operation can or cannot be performed in the (a+1)th erase cycle to the bth erase cycle.

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