Test structure and test method

Abstract

The application discloses a test structure and a test method. The test structure comprises a substrate, a plurality of test metal layers, each of which comprises a serpentine metal line and a comb-shaped structure, a first test electrode, a second test electrode and a third test electrode, the first and second test electrodes being connected with the first end and the second end of each serpentine metal line respectively, and the third test electrode being connected with each comb-shaped structure, so that the first to third test branches are formed between the first and second test electrodes, between the first and third test electrodes and between the second and third test electrodes, and first and second preset MOS tubes are further connected in series between the first and second test electrodes and each serpentine metal line. The current of each first test branch under the same test voltage is different, the current of each second test branch under the same test voltage is different, and the current of each third test branch under the same test voltage is different. The test structure can save the wafer area and the test times by several times.

Description

Technical Field

[0001] This invention relates to the field of electrical testing technology in the design and manufacturing process of integrated circuits, and specifically to a test structure and test method. Background Technology

[0002] The most typical characteristics of integrated circuit development include the shrinking feature size of front-end devices and the increasing complexity of back-end metal wiring. Back-end metal processes mainly provide power or signal paths to the various ports of front-end devices through electrical connections, making back-end metal interconnect processes crucial.

[0003] To monitor the stability of downstream metal interconnect processes, in addition to controlling production process data, various electrical properties of the metal, such as sheet resistance, wire connectivity, and short circuits between wires, must also be monitored. Since the primary function of metal is as interconnect, short circuits and open circuits caused by process abnormalities are important electrical testing items.

[0004] Existing test structures for open and short circuits in the back-end metal interconnect layer follow a layered, individually designed approach. This means a set of test patterns is created for each metal interconnect layer. While this approach is highly targeted and facilitates easy problem tracing, it also has significant drawbacks. Because nanoscale integrated circuit manufacturing processes typically involve 6 to 10 or more metal interconnect layers, following this principle for test structures requires a large area for creating the necessary test patterns. Furthermore, each test pattern needs to be electrically tested individually, wasting testing resources.

[0005] Therefore, how to reduce the consumption of testing resources, improve testing efficiency, and promptly determine the location of defects are technical problems that need to be solved by those skilled in the art. Summary of the Invention

[0006] In view of the above problems, the purpose of the present invention is to provide a test structure and test method. The test structure can save a lot of wafer area, while also being convenient to use, simple to test, and able to accurately reflect the problems of the subsequent metal interconnect process.

[0007] To achieve the above objectives, a first aspect of the present invention is to provide a test structure, comprising:

[0008] Substrate;

[0009] At least two test metal layers are located on the substrate, each test metal layer including interlaced serpentine metal lines and comb-like structures;

[0010] The first test electrode to the third test electrode are respectively connected to the first end of the serpentine metal line in each test metal layer, the second test electrode is respectively connected to the second end of the serpentine metal line in each test metal layer, and the third test electrode is connected to the comb-shaped structure in each test metal layer, so that at least two first test branches are formed between the first test electrode and the second test electrode, at least two second test branches are formed between the first test electrode and the third test electrode, and at least two third test branches are formed between the second test electrode and the third test electrode.

[0011] Among them, a first preset MOS transistor is connected in series between the first test electrode and the first end of the serpentine metal line in each test metal layer, and a second preset MOS transistor is connected in series between the second test electrode and the second end of the serpentine metal line in each test metal layer; the current of each first test branch is different under the same test voltage, the current of each second test branch is different under the same test voltage, and the current of each third test branch is different under the same test voltage.

[0012] Preferably, the first preset MOS transistor and the second preset MOS transistor in the same first test branch are the same.

[0013] Preferably, the first preset MOS transistor and the second preset MOS transistor in the same first test branch can be connected in forward series through a serpentine metal wire.

[0014] Preferably, in the test structure, the difference in turn-on voltage between all first preset MOSFETs and second preset MOSFETs does not exceed 10%, and preferably does not exceed 5%.

[0015] Preferably, both the first preset MOS transistor and the second preset MOS transistor are formed based on a substrate.

[0016] Preferably, the third test electrode is located between the first test electrode and the second test electrode;

[0017] The serpentine metal wire comprises two connected parts, one part being located between the first test electrode and the third test electrode, and the other part being located between the third test electrode and the second test electrode.

[0018] Preferably, the comb-like structure includes a first comb-like structure and a second comb-like structure, wherein the first comb-like structure and the second comb-like structure are respectively inserted into the serpentine metal wire from both sides.

[0019] Preferably, the comb-like structure includes a comb handle and a plurality of toothed metal strips connected to the comb handle, wherein the comb handle of the first comb-like structure and the comb handle of the second comb-like structure are connected at a position around one end of the serpentine metal wire.

[0020] Preferably, the source and body electrodes of the first preset MOS transistor are connected to the first end of the serpentine metal line of the corresponding test metal layer, and the gate and drain of the first preset MOS transistor are connected to the first test electrode; the drain and gate of the second preset MOS transistor are connected to the second end of the serpentine metal line of the corresponding test metal layer, and the source and body electrodes of the second preset MOS transistor are connected to the second test electrode.

[0021] A second aspect of the present invention is to provide a testing method using the testing structure described in the first aspect, the testing method comprising the following steps:

[0022] A first preset voltage is applied between the first test electrode and the second test electrode, and a first current value between the first test electrode and the second test electrode is detected. The first preset voltage enables the first preset MOS transistor and the second preset MOS transistor in the first test branch to be forward-biased.

[0023] A second preset voltage is applied between the first test electrode and the third test electrode, and a second current value between the first test electrode and the third test electrode is detected. The second preset voltage enables the first preset MOS transistor in the second test branch to be forward-biased.

[0024] A third preset voltage is applied between the second test electrode and the third test electrode, and a third current value between the second test electrode and the third test electrode is detected. The third preset voltage can enable the second preset MOS transistor in the third test branch to be forward-biased.

[0025] Defects are identified and located based on the first, second, and third current values.

[0026] Preferably, the method further includes: establishing a judgment comparison table, which includes the mapping relationship between different combinations of the first current value to the third current value and the defect; judging and locating the defect based on the comparison results between the first current value to the third current value and the judgment comparison table.

[0027] Preferably, the voltage value of the first preset voltage is twice the voltage value of the second preset voltage, the voltage value of the third preset voltage is the same as the voltage value of the second preset voltage, and the voltage value of the second preset voltage is 0.9 to 1 times the highest turn-on voltage of the first preset MOSFET and the second preset MOSFET.

[0028] The test structure provided by this invention includes multiple test metal layers, each of which integrates existing test units for testing short circuits and open circuits, and each test metal layer corresponds to a metal interconnect layer. By connecting a pair of MOSFETs in series between the test metal layers and the test electrodes, a one-to-one mapping relationship is established between various short circuit or open circuit abnormalities and current values. Compared with the prior art, the wafer area occupied by the test structure of this invention is comparable to that of existing single composite test structures. Therefore, the wafer area occupied by the test structure of this invention is reduced to 1 / (N-1) of that of existing test structures, where N is the total number of metal interconnect layers, thereby effectively saving wafer area occupied by the test structure.

[0029] In actual testing, compared to existing layered composite test structures that require testing layer by layer, the test structure of this invention only requires a single test to identify and locate defects. In particular, by using a judgment lookup table, it can quickly pinpoint which specific test metal layer(s) the short circuit or open circuit problem occurs in, and can also determine the relative positions of short circuits and open circuits within the same test metal layer. Therefore, compared to existing testing methods, this method significantly reduces the number of tests, greatly improves testing efficiency, and the test results can provide important clues for subsequent failure analysis and localization. Attached Figure Description

[0030] The above and other objects, features, and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings. Furthermore, for clarity, the various parts in the drawings are not drawn to scale.

[0031] Figure 1 A top view of the existing layered test structure;

[0032] Figure 2 This is a three-dimensional structural diagram of the test structure according to the first embodiment of the present invention;

[0033] Figure 3a This is a schematic diagram of the equivalent circuit of the test structure according to the first embodiment of the present invention;

[0034] Figure 3b The table below shows the electrical performance of each MOS transistor in the first embodiment of the present invention.

[0035] Figure 3c This is a flowchart illustrating the testing method of the first embodiment of the present invention;

[0036] Figure 3d This is a judgment comparison table for the test structure of the first embodiment of the present invention;

[0037] Figure 4 This is a three-dimensional structural diagram of the test structure according to the second embodiment of the present invention;

[0038] Figure 5a This is a schematic diagram of the equivalent circuit of the test structure according to the second embodiment of the present invention;

[0039] Figure 5b The table below shows the electrical performance of each MOS transistor in the second embodiment of the present invention.

[0040] Figure 5c This is the first judgment comparison table for the test structure of the second embodiment of the present invention;

[0041] Figure 6a This is a schematic diagram of the equivalent circuit of the test structure in the second embodiment of the present invention when a short circuit anomaly occurs.

[0042] Figure 6b This is the second judgment comparison table for the test structure of the second embodiment of the present invention;

[0043] Figure 7a This is a schematic diagram of the equivalent circuit of the test structure in the second embodiment of the present invention when an open-circuit anomaly occurs.

[0044] Figure 7b Table 3 shows the determination comparison table for the test structure of the second embodiment of the present invention;

[0045] Figure 8a This is a schematic diagram of the equivalent circuit of the test structure of the second embodiment of the present invention, which simultaneously exhibits short-circuit and open-circuit anomalies.

[0046] Figure 8b Table 4 shows the determination comparison table for the test structure of the second embodiment of the present invention. Detailed Implementation

[0047] Various embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments. In the following detailed description of the invention, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these detailed descriptions. To avoid obscuring the essence of the invention, well-known methods, processes, and procedures are not described in detail.

[0048] Figure 1 A top view of the existing test structure; such as Figure 1As shown, the existing test structure includes a first sub-test pad 111, a second sub-test pad 121, and a third sub-test pad 131. According to current industry design practices, the three sub-test pads (PADs) are arranged sequentially along the cutting path, and the spacing between adjacent sub-test pads is usually consistent. The first sub-test pad 111 and the second sub-test pad 121 are connected by a serpentine metal wire 160, forming a test unit capable of detecting open circuits. The third sub-test pad 131 is connected to a comb-like structure. Specifically, the comb-like structure includes, for example, a first comb-like structure 170 and a second comb-like structure 180 arranged opposite each other. The two comb-like structures are arranged opposite each other and intersect with the serpentine metal wire 160 from both sides, forming a test unit capable of detecting short circuits.

[0049] The first comb-shaped structure 170 is similar to the second comb-shaped structure 180. Taking the first comb-shaped structure 170 as an example, the first comb-shaped structure 170 includes a comb handle 171 and multiple toothed metal strips 172. One end of each of the multiple toothed metal strips 172 is connected to the comb handle 171 on the same side. The comb handle 171 of the first comb-shaped structure 170 bypasses the second sub-test pad 121 and is connected to the comb handle of the second comb-shaped structure 180 to achieve same-layer connection. Of course, the first comb-shaped structure 170 can also bypass the first sub-test pad 111 and be connected to the second comb-shaped structure 180.

[0050] exist Figure 1 In this design, the serpentine metal wire 160 is divided into two connected segments, which are connected by a metal wire in the same layer. The third sub-test pad 131 is located between the two serpentine metal wire segments 160, and also between the first sub-test pad 111 and the second sub-test pad 121. The third sub-test pad 131 is connected to the comb handle 171 of the first comb-like structure 170. Of course, the third sub-test pad 131 can also be located in other positions, such as to the right of the second sub-test pad 121, connected to the comb-like structure.

[0051] In fact, Figure 1 The existing test structure shown is a composite test structure that can be used to detect short circuit and open circuit conditions. In this structure, a dielectric layer (not shown in the figure) is provided between all the toothed metal strips and between the toothed metal strips and the serpentine metal wires. The dielectric layer insulates and separates the adjacent conductive structures.

[0052] During the test, a first preset voltage is applied between the first sub-test pad 111 and the second sub-test pad 121, and the current value between the first sub-test pad 111 and the second sub-test pad 121 is detected; a second preset voltage is applied between the first sub-test pad 111 and the third sub-test pad 131, and the current value between the first sub-test pad 111 and the third sub-test pad 131 is detected; a third preset voltage is applied between the second sub-test pad 121 and the third sub-test pad 131, and the current value between the second sub-test pad 121 and the third sub-test pad 131 is detected. Based on the above three current values, it can be determined whether a short circuit and / or open circuit has occurred.

[0053] It's easy to understand that the length of the serpentine metal wire and the number of toothed metal strips in the comb-like structure are positively correlated with the sensitivity of the test structure to open-circuit and short-circuit anomalies in the metal wire. Given the allowable cut width and test pad spacing, the longer the serpentine metal wire and the more teeth in the comb-like structure, the greater the probability of capturing short-circuit / open-circuit defects. To further increase the sensitivity of the test structure, the width of the toothed metal strips, the spacing between adjacent toothed metal strips, and the spacing between the toothed metal strips and the serpentine metal wire should be selected to the minimum values ​​that satisfy the physical design rules of the corresponding process platform.

[0054] When an open circuit and / or short circuit appears in the test structure, it indicates that the integrated circuit in the corresponding device area of ​​the wafer likely also has a similar defect in the metal interconnect layer. Specifically, since the test metal layers in this test structure are formed synchronously with the metal interconnect layer of the device area, testing this test structure can provide feedback on whether the manufacturing process of the corresponding device area's metal interconnect layer is stable and normal, thereby promptly identifying problems and reducing the production of defective products.

[0055] As can be seen from the above introduction, in order to monitor the downstream metal processing, existing technologies require a separate test structure for each metal interconnect layer. Generally, the top metal lines are thicker and have larger spacing, so no monitoring pattern is needed. Therefore, the downstream process requires N-1 such test structures. Figure 1 The test structure shown is given by N, where N is the total number of metal interconnect layers. Correspondingly, the sum of the wafer areas occupied by these N-1 test structures is approximately S×(N-1), where S is the wafer area occupied by each test structure. Furthermore, during testing, each of the N-1 test structures needs to be tested individually according to the testing method described above, with the number of tests also being N-1. Therefore, optimizing existing test structures to reduce the wafer area occupied by the test structures and improve testing efficiency, while ensuring the accuracy of defect identification and location, is of great significance in the integrated circuit design and testing process.

[0056] Figure 2This is a three-dimensional structural diagram of the test structure according to the first embodiment of the present invention; as shown. Figure 2 As shown, the test structure includes, for example, a substrate 100, two test metal layers M1 and M2 stacked above the substrate 100 along the Z direction, and a first test electrode 110, a second test electrode 120, and a third test electrode 130 located above the test metal layers. Both test metal layers M1 and M2 include interlaced serpentine metal lines and comb-like structures. For details regarding the structure, relative position, and connection to the test electrodes of the serpentine metal lines and comb-like structures, please refer to the preceding text. Figure 1 I will not go into details.

[0057] The test structure provided in this embodiment includes four preset MOS transistors, all formed on substrate 100. These preset MOS transistors can be, for example, directly borrowed from different MOS transistors in an integrated circuit, or the same type of MOS transistor can be selected. Performance parameters can be adjusted by changing the channel length or width of the device. Preferably, the four preset MOS transistors formed on substrate 100 are of the same type, meaning that the formation process and other parameters of the preset MOS transistors are consistent. This allows for fine-tuning of the device's turn-on voltage by adjusting the channel length and / or width, achieving subtle differences in turn-on voltage and significant differences in conduction current under the same bias. For ease of explanation, among these four preset MOS transistors, MOS transistors 141 and 142 are collectively referred to as the first preset MOS transistor 140, located between the first test electrode 110 and the third test electrode 130; MOS transistors 151 and 152 are collectively referred to as the second preset MOS transistor 150, located between the third electrode 130 and the second electrode 120.

[0058] Further reference Figure 1 In addition to the serpentine metal lines and comb-like structures, the test metal layer M1 also includes a first sub-test pad 111, a second sub-test pad 121, and a third sub-test pad 131. One end of the serpentine metal lines in the test metal layer M1 is connected to the body electrode B and source electrode S of the MOS transistor 141 via a vertical metal plug; the gate G and drain D of the MOS transistor 141 are connected to the first test electrode 110 via the first sub-test pads 111 and 112 through the vertical metal plug. When the MOS transistor 141 is turned on, the first test electrode 110 can be electrically connected to the serpentine metal lines in the test metal layer M1. Similarly, the other end of the serpentine metal line in the test metal layer M1 is connected to the drain D and gate G of the MOS transistor 151 through a vertical metal plug. The source S and body electrode B of the MOS transistor 151 are connected to the second test electrode 120 through the second sub-test pads 121 and 122 via the vertical metal plug. When the MOS transistor 151 is turned on, the second test electrode 120 can be electrically connected to the serpentine metal line in the test metal layer M1.

[0059] Similar to M1, test metal layer M2, in addition to the serpentine metal lines and comb-like structure, also includes a first sub-test pad 112, a second sub-test pad 122, and a third sub-test pad 132. The lateral leads at both ends of the serpentine metal lines in the test units of test metal layer M2 are staggered from those of test metal layer M1 in the Y direction, ensuring that each test unit of the test metal layer is connected to its corresponding MOSFET.

[0060] One end of the serpentine metal line in the test metal layer M2 is connected to the body electrode B and source electrode S of the MOSFET 142 via two vertical metal plugs. The gate electrode G and drain electrode D of the MOSFET 142 are connected to the first test electrode 110 via the vertical metal plugs and the first sub-test pads 111 and 112. When the MOSFET 142 is turned on, the first test electrode 110 is electrically connected to the serpentine metal line in the test metal layer M2. Similarly, the other end of the serpentine metal line in the test metal layer M2 is connected to the drain electrode D and gate electrode G of the MOSFET 152 via two vertical metal plugs. The source electrode S and body electrode B of the MOSFET 152 are connected to the second test electrode 120 via the vertical metal plugs and the second sub-test pads 121 and 122. When the MOSFET 152 is turned on, the second test electrode 120 is electrically connected to the serpentine metal line in the test metal layer M2.

[0061] The test structure of the first embodiment includes two test metal layers, corresponding to two parallel first test branches located between the first test electrode 110 and the second test electrode 120, two parallel second test branches located between the first test electrode 110 and the third test electrode 130, and two parallel third test branches located between the second test electrode 120 and the third test electrode 130. One of the first test branches includes a serpentine metal line in the test metal layer M1 and MOS transistors 141 and 151 connected to the two ends of the serpentine metal line; the other first test branch includes a serpentine metal line in the test metal layer M2 and MOS transistors 142 and 152 connected to the two ends of the serpentine metal line. One second test branch includes a comb-shaped structure and a serpentine metal line interspersed between the first test electrode 110 and the third test electrode 130 in the test metal layer M1, and a MOS transistor 141; the other second test branch includes a comb-shaped structure and a serpentine metal line interspersed between the first test electrode 110 and the third test electrode 130 in the test metal layer M2, and a MOS transistor 142. One third test branch includes a comb-shaped structure and a serpentine metal line interspersed between the second test electrode 120 and the third test electrode 130 in the test metal layer M1, and a MOS transistor 151; the other third test branch includes a comb-shaped structure and a serpentine metal line interspersed between the second test electrode 120 and the third test electrode 130 in the test metal layer M2, and a MOS transistor 152.

[0062] Under normal circumstances, with both MOSFETs 141 and 151 turned on, there should be a conductive path between the first sub-test pad 111 and the second sub-test pad 121, meaning current flows through them. There should be no conductive path between the first sub-test pad 111 and the third sub-test pad 131, and no conductive path between the second sub-test pad 121 and the third sub-test pad 131, meaning no current flows through them. Similarly, with both MOSFETs 142 and 152 turned on, there should be a conductive path between the first sub-test pad 112 and the second sub-test pad 122, meaning current flows through them. There should be no conductive path between the first sub-test pad 112 and the third sub-test pad 132, and no conductive path between the second sub-test pad 122 and the third sub-test pad 132, meaning no current flows through them. If the actual test results differ from the above, it indicates a defect in the test structure, suggesting a potential problem with the manufacturing process of the corresponding metal interconnect layer.

[0063] Furthermore, the two parallel first test branches have different currents under the same test voltage, the two parallel second test branches have different currents under the same test voltage, and the two parallel second test branches have different currents under the same voltage. Therefore, the current between each test electrode is detected to provide feedback on whether the manufacturing process of each metal interconnect layer is normal. Of course, although Figure 2 The example shown only has two test metal layers, and a MOS transistor is connected in series at each end of the serpentine metal line. Based on the design of this example, more test metal layers and more MOS transistors can also be set accordingly.

[0064] Furthermore, the test units in each of the aforementioned test metal layers can also be different. Additionally, while the connection relationship of the test units in each test metal layer remains unchanged, their arrangement direction can be perpendicular to each other; for example... Figure 2 The toothed metal strips of the comb-like structure in the test metal layers M1 and M2 extend along the Y direction, so they can be regarded as the arrangement direction of the test units in the two test metal layers being parallel; or, the extension direction of the toothed metal strips of the comb-like structure in the test metal layers M1 and M2 can also be perpendicular to each other, that is, the arrangement direction of the test units in the two test metal layers is perpendicular.

[0065] Figure 3a This is a schematic diagram of the equivalent circuit of the test structure according to the first embodiment of the present invention. To simplify subsequent defect analysis, the comb-like structure on both sides of the serpentine metal line is simplified to a single-sided form for illustration. The MOS transistors connected in series at both ends of the same test metal layer are identical. Specifically, MOS transistors 141 and 151 are identical and both are MOS1; MOS transistors 142 and 152 are identical and both are MOS2, thus establishing an inherent mapping relationship between specific MOS transistors and specific test metal layers. To ensure that the MOS transistors can be turned on simultaneously without any breakdown, the difference in turn-on voltage between MOS1 and MOS2 is preferably controlled within 10%, and more preferably within 5%, so that all MOS transistors in the circuit can be turned on simultaneously under the test voltage and are all in a high-impedance state. Here, "difference" refers to the percentage of the absolute value of the maximum difference among all preset MOS transistors in the test structure relative to the larger of the two.

[0066] It is easy to understand that, in order to increase the sensitivity and resolution of the test structure, the greater the difference in the conduction current of the preset MOSFETs under the same test voltage within the measurable range, the better. In order to meet the above requirements, in the specific implementation process, the manufacturing process of the preset MOSFETs in the test structure is basically the same, and the only difference lies in the channel length L and / or width W. By controlling the channel size and utilizing the channel effect, the difference in the turn-on voltage of the preset MOSFETs can be kept within 10% or even 5%, while the current of each test branch can achieve an order of magnitude difference under the same test voltage.

[0067] from Figure 3a As can be seen, one end of the serpentine metal line in the test metal layer M1 is connected to the first test electrode 110 through MOS1 on one side, and the other end is connected to the second test electrode 120 through MOS1 on the other side. The comb-shaped structure in the test metal layer M1 is connected to the third test electrode 130. One end of the serpentine metal line in the test metal layer M2 is connected to the first test electrode 110 through MOS2 on one side, and the other end is connected to the second test electrode 120 through MOS2 on the other side. The comb-shaped structure in the test metal layer M2 is connected to the third test electrode 130.

[0068] Figure 3b This is a table showing the electrical performance of each MOS transistor in the test structure provided in the first embodiment of the present invention, wherein the turn-on voltage of MOS1 is denoted as V. t1 The turn-on voltage of MOS2 is denoted as V. t2 The turn-on voltages of MOS1 and MOS2 are different, for example, V. t1 <V t2 As mentioned earlier, the turn-on voltage of two MOSFETs can be controlled by changing the channel size. Utilizing the narrow or short channel effect of the devices, the turn-on voltage Vth can be adjusted. t1 and V t2 The difference should be controlled within 10%, preferably within 5%. The aforementioned MOSFET turn-on refers to the existence of a conductive channel between the source and drain of the device; in this case, the source and drain can be considered to be connected together through a resistor.

[0069] For each of the above MOSFETs, its drain (D) and gate (G) are shorted, and its source (S) and body (B) are shorted. Therefore, the drain voltage V0 D and gate voltage V G Equal, source voltage V S Body electrode voltage V B equal.

[0070] During testing, this test structure requires applying preset voltages between each pair of the first test electrode 110, the second test electrode 120, and the third test electrode 130 to measure their conduction current under different biases. For the open-circuit test, a first preset voltage V1 is applied between the first test electrode 110 and the second test electrode 120. The potential of the first test electrode is, for example, higher than the potential of the second test electrode. The first preset voltage V1 = 2V2, where V2 is the second preset voltage, with a value of 0.9V. t2 <V2<V t2 This ensures that all four MOSFETs in the circuit can be turned on or are in a near-on state.

[0071] A first preset voltage V1 is applied to the drain D and gate G of the left MOS1 on the first test electrode. For the test metal layer M1, all MOS1s connected in series at both ends of its serpentine metal line are turned on. At this time, the current of this branch is denoted as I. 1-1 Similarly, the first test branch containing the test metal layer M2 is also in a conducting state, and its current is denoted as I. 1-2 The test mainly focuses on short-circuit conditions in the feedback circuits between the first and third test electrodes, and between the second and third test electrodes. A second preset voltage V2 is applied between the first and third test electrodes. If a short circuit occurs in the test metal layer M1, the left-side MOS1 turns on. At this time, the current in the second test branch of MOS1 is I. 2-1 Similarly, if the test metal layer M2 is short-circuited, the left-side MOS2 will turn on, and the current in the test branch containing MOS2 will be I. 2-2 Similarly, a third preset voltage V3 is applied between the second and third test electrodes. Specifically, V3 = V2. If the test metal layer M1 is short-circuited, the right-side MOS1 turns on, and the current in the third test branch where MOS1 is located is I. 2-1 Similarly, if the test metal layer M2 is short-circuited, the right-side MOS2 will turn on, and the current in the test branch containing MOS2 will be I. 2-2 .

[0072] Figure 3c This is a flowchart illustrating the testing method of the first embodiment of the present invention, as shown below. Figure 3c As shown, the testing method includes the following steps:

[0073] In step S10, a first preset voltage is applied between the first test electrode and the second test electrode, and a first current value between the first test electrode and the second test electrode is detected; wherein, the first preset voltage V1 enables all preset MOSFETs connected in series in each first test branch to conduct in the forward direction, for example, V1 = 2V2, 0.9V. t2 <V2<V t2 And V t2>V t1 , combined Figure 3a As shown, if all tested metal layers show no abnormalities, then the first current value Ix = I 1-1 +I 1-2 .

[0074] In step S20, a second preset voltage is applied between the first test electrode and the third test electrode, and a second current value between the first test electrode and the third test electrode is detected; wherein, the voltage value of the second preset voltage is 0.9 to 1 times the highest turn-on voltage of all preset MOSFETs in the two test branches, for example, the second preset voltage V t2 >V t1 0.9V t2 <V2<V t2 , combined Figure 3a As shown, if all tested metal layers are normal, the second current value Iy = 0.

[0075] In step S30, a third preset voltage is applied between the second test electrode and the third test electrode, and a third current value between the second test electrode and the third test electrode is detected; wherein, the third preset voltage V3 is equal to the second preset voltage V2, combined with Figure 3a As shown, if all tested metal layers are normal, the third current value Iz = 0.

[0076] In step S40, the defect is determined and located based on the first current value, the second current value, and the third current value. Specifically, a test structure can be pre-established based on the test structure of this application, such as... Figure 3d The judgment comparison table shown includes the mapping relationship between different combinations of the first current value Ix, the second current value Iy, and the third current value Iz and the defects. Based on the comparison results of the first current value Ix, the second current value Iy, and the third current value Iz with the judgment comparison table, the defects of the test structure can be judged and the defects can be located. Furthermore, if one or more test metal layers are simultaneously short-circuited and open-circuited, the relative positional relationship between the short circuit and the open circuit can also be determined.

[0077] Figure 3d It shows a determination comparison table of the test structure of the first embodiment of the present invention. Without considering the simultaneous occurrence of multiple short circuit points and open circuit points in the same test metal layer, that is, there is at most one short circuit point in the same test metal layer and at most one open circuit point in the same test metal layer, the situation of each test metal layer can be determined by comparing with this determination comparison table.

[0078] Figure 4 This is a three-dimensional schematic diagram of the test structure according to the second embodiment of the present invention; as shown below. Figure 4As shown, the second embodiment is similar to the first embodiment, except that the test structure of the second embodiment has three test metal layers, M1, M2, and M3. Correspondingly, the first sub-test pads 111, 112, and 113 in the three test metal layers are all connected to the first test electrode 110 of the top layer, the second sub-test pads 121, 122, and 123 in the three test metal layers are all connected to the second test electrode 120 of the top layer, and the third sub-test pads 131, 132, and 133 in the three test metal layers are all connected to the third test electrode 130 of the top layer. Based on the substrate 100, three pairs of six preset MOS transistors are set, namely MOS transistors 141-143 and MOS transistors 151-153. Among them, MOS transistors 141-143 are collectively referred to as the first preset MOS transistors 140, and MOS transistors 151-153 are collectively referred to as the second preset MOS transistors 150. Furthermore, the three MOSFETs 141-143 of the first preset MOSFET 140 have different on-state currents under the same bias, and the three MOSFETs 151-153 of the second preset MOSFET 150 also have different on-state currents under the same bias. In addition, the current of each first test branch is also different under the same test voltage.

[0079] Figure 5a This is a schematic diagram of the equivalent circuit of the test structure according to the second embodiment of the present invention. To simplify the subsequent defect analysis, MOS transistors 141 and 151 are both designated as MOS1, MOS transistors 142 and 152 are both designated as MOS2, and MOS transistors 143 and 153 are both designated as MOS3. That is, the pair of MOS transistors corresponding to the same test metal layer are identical, and the comb-like structure on both sides of the serpentine metal line is simplified to a single-sided form for illustration. Preferably, MOS1, MOS2, and MOS3 are manufactured using the same process, with the only difference being the channel dimensions of the MOS transistors, such as different channel widths and / or lengths, thereby enabling fine-tuning of their turn-on voltages, while the difference in forward conduction current under the same bias is significant.

[0080] Since the test structure of the second embodiment includes three test metal layers, there are many corresponding abnormal situations. A complete judgment comparison table would be too lengthy. Therefore, some situations are selected from the complete judgment comparison table for explanation and detail. Figure 5c , Figure 6b , Figure 7b and Figure 8b All of these are parts of the complete judgment comparison table.

[0081] Figure 5b This is a table showing the electrical performance of each MOS transistor in the second embodiment of the present invention; and... Figure 3b Similarly, the turn-on voltage of MOS1 is denoted as V. t1 The turn-on voltage of MOS2 is denoted as V. t2The turn-on voltage of MOS3 is denoted as V. t3 The turn-on voltages of the three MOSFETs mentioned above are different, for example, V. t1 <V t2 <V t3 The first preset voltage V1 = 2V2, the second preset voltage V2 is equal to the third preset voltage V3, and V2 = V3; where V2 is 0.9V. t3 <V2<V t3 The remaining information will not be repeated here; please refer to [the relevant resources]. Figure 3b .

[0082] Figure 5c This is a judgment comparison table for the test structure of the second embodiment of the present invention. According to... Figure 5a The equivalent circuit diagram shows that when all test metal layers are not abnormal, that is, when test metal layers M1, M2, and M3 are not short-circuited or open-circuited, the first test electrode 110 and the second test electrode 120 are equivalent to three first test branches connected in parallel in the circuit. The first test branch where test metal layer M1 is located includes two MOS1, the first test branch where test metal layer M2 is located includes two MOS2, and the first test branch where test metal layer M3 is located includes two MOS3. There is no bridging (short-circuit) between the comb-shaped structure and the serpentine metal line in the three test metal layers. The second test branch between the first test electrode 110 and the third test electrode 130, and the third test branch between the second test electrode 120 and the third test electrode 130, have no conducting loops.

[0083] A first preset voltage V1 is applied between the first test electrode 110 and the second test electrode 120. Under the first preset voltage V1, MOS1, MOS2, and MOS3 are all turned on, and all three first test branches are conducted. At this time, the first current value Ix of the circuit is: Ix = I 1-1 +I 1-2 +I 1-3 ;

[0084] A second preset voltage V2 is applied between the first test electrode 110 and the third test electrode 130. Since none of the three second test branches are conducting, there is no conducting loop between the first test electrode 110 and the third test electrode 130. Therefore, the second current value Iy between the first test electrode 110 and the third test electrode 130 is 0.

[0085] A third preset voltage V3 is applied between the second test electrode 120 and the third test electrode 130, where V3 = V2. Since none of the three third test branches are conducting, there is no conducting loop between the second test electrode 120 and the third test electrode 130. Therefore, the third current value Iz between the second test electrode 120 and the third test electrode 130 is 0.

[0086] Figure 6a This is an equivalent circuit diagram of the test structure of the second embodiment of the present invention when only a short-circuit anomaly occurs; specifically, for example, when both test metal layer M1 and test metal layer M2 are short-circuited simultaneously, and there is no open-circuit anomaly.

[0087] A first preset voltage V1 is applied between the first test electrode 110 and the second test electrode 120, and the potential of the first test electrode 110 is higher than that of the second test electrode 120. Under the first preset voltage V1, MOS1, MOS2, and MOS3 are all turned on, and the first current value of the circuit is Ix = I 1-1 +I 1-2 +I 1-3 ;

[0088] A second preset voltage V2 is applied between the first test electrode 110 and the third test electrode 130, with the potential of the first test electrode 110 being higher than that of the third test electrode 130. Since both test metal layers M1 and M2 are short-circuited simultaneously, a circuit is formed in both test metal layers M1 and M2. MOS1 on the left side of test metal layer M1 is turned on, and MOS2 on the left side of test metal layer M2 is turned on. At this time, the second current value of the circuit is Iy = I... 2-1 +I 2-2 ;

[0089] A third preset voltage V3, where V3 = V2, is applied between the second test electrode 120 and the third test electrode 130. The potential of the third test electrode 130 is higher than that of the second test electrode 120. Since both test metal layers M1 and M2 are short-circuited simultaneously, a circuit is formed in both test metal layers M1 and M2. MOS1 on the right side of test metal layer M1 is turned on, and MOS2 on the right side of test metal layer M2 is turned on. At this time, the second current value of the circuit is Iz = I 2-1 +I 2-2 .

[0090] Similarly, when only a short-circuit fault occurs, the procedure can be followed as follows: Figure 6b The defect is determined and located using the judgment comparison table shown in Table 2.

[0091] Figure 7a This is a schematic diagram of the equivalent circuit of the test structure in the second embodiment of the present invention when only an open-circuit anomaly occurs. Specifically, for example, when both test metal layer M1 and test metal layer M2 are open-circuited, the first test electrode 110 and the second test electrode 120 are equivalent to only two MOS3s connected in series in the circuit. The connection between the first test electrode 110 and the third test electrode 130, and between the second test electrode 120 and the third test electrode 130, is also shown. Figure 5a As shown in the diagram, none of them can form a pathway.

[0092] When a first preset voltage V1 is applied between the first test electrode 110 and the second test electrode 120, both MOS3s are turned on, and the first current value of the circuit is Ix = I 1-3 A second preset voltage V2 is applied between the first test electrode 110 and the third test electrode 130, and the corresponding second current value Iy = 0 is applied between the second test electrode 120 and the third test electrode 130, and the corresponding third current value Iz = 0 is applied between the second test electrode 120 and the third test electrode 130.

[0093] Similarly, when only the open circuit is faulty, the procedure can be followed as follows: Figure 7b The defect is identified and located using the judgment comparison table shown in Table 3.

[0094] Figure 8a This is an equivalent circuit diagram of the test structure of the second embodiment of the present invention when both short circuit and open circuit abnormalities occur simultaneously; specifically, it is assumed that test metal layer M1 simultaneously experiences short circuit and open circuit, test metal layer M2 simultaneously experiences short circuit and open circuit, and test metal layer M3 has no abnormality.

[0095] Analyzing such cases also requires considering the relative positions of short-circuit and open-circuit anomalies within the same layer of the test structure, such as... Figure 8a As shown, the short-circuit point in the test metal layer M1 is located to the left of the open-circuit point. Due to the open-circuit anomaly, neither of the two MOS1s is connected to the circuit between the first test electrode 110 and the second test electrode 120. Because of the short-circuit anomaly and the short-circuit point being located to the left of the open-circuit point, when the second preset voltage V2 is applied between the first test electrode 110 and the third test electrode 130, the leftmost MOS1 is connected to the circuit between the first test electrode 110 and the third test electrode 130, while neither of the two MOS1s can be connected to the circuit between the second test electrode 120 and the third test electrode 130.

[0096] The abnormal condition of test metal layer M2 is similar to that of test metal layer M1, except that the relative positions of the open circuit point and the short circuit point are different. At this time, a first preset voltage V1 is applied between the first test electrode 110 and the second test electrode 120, and the third test electrode 130 is grounded. Under the first preset voltage V1, both MOS3s are turned on, and the first current value of the circuit is Ix = I... 1-3 A second preset voltage V2 is applied between the first test electrode 110 and the third test electrode 130, corresponding to a second current value Iy = I 2-1 A third preset voltage V3 is applied between the second test electrode 120 and the third test electrode 130, corresponding to a third current value Iz = I 2-2 .

[0097] Similarly, in cases where both short circuits and open circuits occur simultaneously in the same test metal layer, the following procedures can be followed: Figure 8bThe judgment comparison table shown in section four is for judging and locating defects. Furthermore, using this test structure can not only determine the specific circumstances of anomalies occurring in different test metal layers, but also qualitatively provide the relative locations of short-circuit and open-circuit anomalies, which is highly helpful for failure analysis and location.

[0098] The above embodiments do not consider the situation where multiple short-circuit and open-circuit points occur simultaneously on the same test metal layer. Although judgment comparison tables one to four only show some abnormal situations, a complete judgment comparison table can be obtained by analogy based on the above embodiments. In actual testing, the first, second, and third current values ​​obtained from the test are directly compared with the complete judgment comparison table to obtain the short-circuit and open-circuit abnormalities of each test metal layer. Based on this, it can be determined whether an abnormality has occurred in the corresponding metal wiring layer (metal interconnect layer) of the die area (device area) and infer the specific situation such as the location of the abnormality. In addition, according to the statistical results of each comparison table, when short-circuit and open-circuit abnormalities occur simultaneously in one or several test metal layers, this structure can also provide the relative positional relationship of the short-circuit and open-circuit abnormal points. This positional information has important guiding significance for subsequent failure analysis.

[0099] The test structure provided by this invention integrates existing layered short-circuit and open-circuit composite test units into a single test structure. Each composite test unit and its corresponding sub-test pad constitute a test metal layer. By connecting a pair of MOSFETs in series between the test metal layer and the test electrode, a one-to-one mapping relationship is established between various short-circuit or open-circuit abnormalities and current values. Compared with the prior art, the wafer area occupied by the test structure of this invention is reduced to 1 / (N-1) of that of existing test structures, where N is the total number of metal interconnect layers in the integrated circuit, thereby effectively saving wafer area occupied by the test structure.

[0100] In actual testing, compared to existing layered test structures that require testing layer by layer, the test structure of this invention requires only one test, reducing the number of tests to 1 / (N-1) of the existing number. This significantly reduces the number of tests and improves testing efficiency. In particular, the judgment table provided by this invention allows for quick identification of which specific test metal layers or layers have short-circuit or open-circuit problems. Furthermore, it can determine the relative positions of short-circuit and open-circuit anomalies within the same test metal layer, providing crucial clues for subsequent failure analysis and localization. Moreover, by utilizing the differences in the turn-on voltage of the MOSFETs in each test metal layer, a specific voltage can be applied to turn on the corresponding MOSFET, eliminating interference from other test metal layers.

[0101] It should be noted that in the description of this invention, terms such as "first" and "second" are used only to facilitate the description of different orientations, parts, and components, and should not be construed as indicating or implying sequential relationships, relative importance, or implicitly indicating the number of technical features indicated.

[0102] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A test structure, characterized in that, include: Substrate; At least two test metal layers are located on the substrate, each test metal layer including interlaced serpentine metal lines and comb-like structures; The first test electrode to the third test electrode are respectively connected to the first end of the serpentine metal line in each test metal layer, the second test electrode is respectively connected to the second end of the serpentine metal line in each test metal layer, and the third test electrode is connected to the comb-shaped structure in each test metal layer, so that at least two first test branches are formed between the first test electrode and the second test electrode, at least two second test branches are formed between the first test electrode and the third test electrode, and at least two third test branches are formed between the second test electrode and the third test electrode. Among them, a first preset MOS transistor is connected in series between the first test electrode and the first end of the serpentine metal line in each test metal layer, and a second preset MOS transistor is connected in series between the second test electrode and the second end of the serpentine metal line in each test metal layer; the current of each first test branch is different under the same test voltage, the current of each second test branch is different under the same test voltage, and the current of each third test branch is different under the same test voltage.

2. The test structure according to claim 1, characterized in that, The first preset MOSFET and the second preset MOSFET in the same first test branch are the same.

3. The test structure according to claim 1 or 2, characterized in that, The first and second preset MOSFETs in the same first test branch can be connected in forward series through a serpentine metal wire.

4. The test structure according to claim 1 or 2, characterized in that, In the test structure, the absolute value of the difference between any two of the turn-on voltages of the first preset MOSFET and the second preset MOSFET does not exceed 10% of the larger one.

5. The test structure according to claim 3, characterized in that, In the test structure, the absolute value of the difference between any two of the turn-on voltages of the first preset MOSFET and the second preset MOSFET does not exceed 10% of the larger one.

6. The test structure according to claim 4, characterized in that, Both the first preset MOS transistor and the second preset MOS transistor are formed based on the substrate.

7. The test structure according to claim 5, characterized in that, Both the first preset MOS transistor and the second preset MOS transistor are formed based on the substrate.

8. The test structure according to claim 1 or 2, characterized in that, The third test electrode is located between the first test electrode and the second test electrode; The serpentine metal wire comprises two connected parts, one part being located between the first test electrode and the third test electrode, and the other part being located between the third test electrode and the second test electrode.

9. The test structure according to claim 8, characterized in that, The comb-like structure includes a first comb-like structure and a second comb-like structure, wherein the first comb-like structure and the second comb-like structure are respectively inserted into the serpentine metal wire from both sides.

10. The test structure according to claim 9, characterized in that, The comb-like structure includes a comb handle and a plurality of toothed metal strips connected to the comb handle. The comb handles of the first comb-like structure and the comb handles of the second comb-like structure are connected at a position around one end of the serpentine metal wire.

11. A testing method, characterized in that, The test method, employing the test structure described in any one of claims 1-10, comprises the following steps: A first preset voltage is applied between the first test electrode and the second test electrode, and a first current value between the first test electrode and the second test electrode is detected. The first preset voltage enables the first preset MOS transistor and the second preset MOS transistor in the first test branch to be forward-biased. A second preset voltage is applied between the first test electrode and the third test electrode, and a second current value between the first test electrode and the third test electrode is detected. The second preset voltage enables the first preset MOS transistor in the second test branch to be forward-biased. A third preset voltage is applied between the second test electrode and the third test electrode, and a third current value between the second test electrode and the third test electrode is detected. The third preset voltage enables the second preset MOS transistor in the third test branch to be forward-biased. Defects are determined and located based on the first current value, the second current value, and the third current value.

12. The test method according to claim 11, characterized in that, Also includes: Establish a judgment comparison table, which includes the mapping relationship between different combinations of the first current value to the third current value and the defect; Based on the comparison results between the first to third current values ​​and the judgment reference table, the defects are judged and located.

13. The test method according to claim 11 or 12, characterized in that, The voltage value of the first preset voltage is twice the voltage value of the second preset voltage; The voltage value of the third preset voltage is the same as the voltage value of the second preset voltage, and the voltage value of the second preset voltage is 0.9 to 1 times the highest turn-on voltage of the first preset MOSFET and the second preset MOSFET.

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