Self-triggered scr device

Abstract

The application discloses a self-triggered SCR device, which comprises a P substrate, a first P+ injection area, a first gate, a second P+ injection area, a first groove, a first N+ injection area, a second gate, a second N+ injection area, a second groove and a third P+ injection area are sequentially arranged on the upper surface of the P substrate; an N well is arranged below the first P+ injection area, the first gate, the second P+ injection area, the first groove and part of the first N+ injection area; and a P well is arranged below the other part of the first N+ injection area, the second gate, the second N+ injection area, the second groove and the third P+ injection area. The SCR device has a smaller area through structure improvement and overall optimization.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit electrostatic discharge protection technology, and relates to a self-triggered SCR device. Background Technology

[0002] Electrostatic discharge (ESD) is a common natural phenomenon in integrated circuits. ESD events typically cause breakdown of the gate oxide layer and PN junction of transistors, hence the dedicated ESD protection modules in integrated circuits. Furthermore, the shrinking of integrated circuit process nodes often results in thinner gate oxide layers and shallower PN junctions, making these layers more susceptible to breakdown. This presents a significant challenge to the design of ESD protection modules.

[0003] To prevent chip damage during ESD events, diodes, MOSFETs, and bipolar transistors are commonly used as ESD protection devices in circuit design. However, ensuring sufficient robustness requires a large layout area, increasing chip manufacturing costs. In recent years, thyristors (SCRs) have been increasingly used for ESD protection due to their smaller layout area and higher robustness. However, traditional SCRs rely on avalanche breakdown of the reverse-biased NP junction for triggering, typically requiring a high voltage. This voltage can cause internal components to be damaged by the rapidly rising voltage before the SCR can turn on, leading to circuit failure.

[0004] To address the aforementioned issues, auxiliary triggering methods can be used to reduce the trigger voltage of the SCR, with diode-triggered SCRs (DTSCRs) being a commonly used method. However, introducing several auxiliary trigger diodes also increases the layout area. The number of diodes needs to be determined based on the actual circuit; typically, a circuit with a 1V operating voltage requires 2 to 3 additional diodes, resulting in approximately doubling the layout area. Therefore, there is an urgent need to develop a novel structure to provide a new way to further improve the performance of SCRs. Summary of the Invention

[0005] The purpose of this invention is to provide a self-triggered SCR device, which solves the problem that the additional diodes introduced in the existing DTSCR cause a significant increase in layout area.

[0006] The technical solution adopted in this invention is a self-triggered SCR device, including a P substrate. A first P+ injection region, a first gate, a second P+ injection region, a first trench, a first N+ injection region, a second gate, a second N+ injection region, a second trench, and a third P+ injection region are sequentially disposed on the upper surface of the P substrate. An N-well is disposed below the first P+ injection region, the first gate, the second P+ injection region, the first trench, and a portion of the first N+ injection region. Meanwhile, a P-well is disposed below another portion of the first N+ injection region, the second gate, the second N+ injection region, the second trench, and the third P+ injection region.

[0007] The self-triggered SCR device of the present invention is further characterized in that:

[0008] The first P+ injection region is connected in series with PMOS transistors Md1 and Md2 in sequence; the gate and drain of PMOS transistor Md2 are simultaneously connected to resistor R1 and the second gate; the other end of resistor R1, the second N+ injection region and the third P+ injection region are connected to the electrical cathode VSS; the first gate is connected to resistor R2, and the other end of resistor R2 and the second P+ injection region are connected to the electrical anode VDD.

[0009] The first P+ injection region, the first gate, the second P+ injection region, and the lower N-well together constitute the PMOS transistor Mp;

[0010] The first N+ injection region, the second gate, the second N+ injection region and the P-well below together constitute the NMOS transistor Mn;

[0011] The second P+ injection region, N-well, and P-well together constitute the parasitic PNP transistor Qp;

[0012] The first N+ injection region, the P-well, and the second N+ injection region together constitute the parasitic NPN transistor Qn;

[0013] The parasitic PNP transistor Qp and the parasitic NPN transistor Qn together form an SCR1 structure;

[0014] The second P+ injection region forms a parasitic P+ / N-well diode D with the N-well. p+ / Nw The N-well and the P-substrate form a parasitic N-well / P-substrate diode D. Nw / Psub The first N+ injection region and the P substrate form a parasitic N+ / P substrate diode D. n+ / Psub .

[0015] Both the first and second trenches are shallow trenches.

[0016] The N-well, P-well, and P-substrate are all made of Si material.

[0017] The first P+ implantation region, the second P+ implantation region, the first N+ implantation region, the second N+ implantation region, and the third P+ implantation region are all made of Si material.

[0018] The beneficial effect of this invention is that, through structural improvements and overall optimization, the SCR device has a smaller area. Attached Figure Description

[0019] Figure 1 This is a cross-sectional view of the existing DTSCR technology;

[0020] Figure 2 This is a cross-sectional view of the SCR device of the present invention;

[0021] Figure 3 This is the equivalent circuit diagram of the SCR device of the present invention;

[0022] Figure 4 This is a layout diagram of the SCR device of the present invention;

[0023] Figure 5 This is a schematic diagram of the triggering path of the SCR device of the present invention during ESD discharge;

[0024] Figure 6 This is a schematic diagram of the main discharge path of the SCR device of the present invention during ESD discharge;

[0025] Figure 7 This is a voltage simulation diagram of the SCR device of this invention;

[0026] Figure 8 This is a graph showing the test results of the SCR device of the present invention under transmission line pulse test conditions.

[0027] In the figure, 1. P substrate, 2. N well, 3. P well, 4. First trench, 5. Second trench, 6. First gate, 7. Second gate, 8. First P+ implantation region, 9. Second P+ implantation region, 10. First N+ implantation region, 11. Second N+ implantation region, 12. Third P+ implantation region. Detailed Implementation

[0028] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0029] Reference Figure 1This is a cross-sectional view of a conventional DTSCR device. The diagram uses a DTSCR device structure with two additional diodes as an example. Diodes D01 and D02 are common P+ / N-well diodes. The anode region of the SCR0 forms diode D03. D03, D02, and D01 are connected in series. The parasitic PNP transistor in the SCR0 consists of the P+ injection region (equivalent to the emitter) connected to the electrical anode VDD, the N-well (equivalent to the base) below the P+ injection region connected to the electrical anode VDD, and the P-substrate (equivalent to the collector). The parasitic NPN transistor consists of the N-well (equivalent to the collector) below the P+ injection region connected to the electrical anode VDD, the P-substrate (equivalent to the base), and the N+ injection region (equivalent to the emitter) of the SCR0 cathode region. When an ESD event occurs, the VDD potential rises rapidly. When it exceeds the sum of the threshold voltages of the three diodes connected in series, the diode string conducts first. At this point, the base-emitter junction of the PNP transistor is forward biased, turning the PNP transistor on. Meanwhile, the collector junction of the NPN transistor is reverse biased, and the emitter junction is forward biased, turning the NPN transistor on. Ultimately, the PNP and NPN transistors form a positive feedback path, thus rapidly dissipating the ESD current.

[0030] Reference Figure 2 The structure of the SCR device of the present invention includes a P substrate 1, on which a first P+ injection region 8, a first gate 6, a second P+ injection region 9, a first trench 4, a first N+ injection region 10, a second gate 7, a second N+ injection region 11, a second trench 5, and a third P+ injection region 12 are sequentially disposed on the upper surface of the P substrate 1; and an N-well 2 is disposed below the first P+ injection region 8, the first gate 6, the second P+ injection region 9, the first trench 4, and a portion of the first N+ injection region 10; and a P-well 3 is disposed below another portion of the first N+ injection region 10, the second gate 7, the second N+ injection region 11, the second trench 5, and the third P+ injection region 12.

[0031] The above describes the main structure of the SCR device of the present invention. The peripheral structure of the SCR device of the present invention further includes: the first P+ injection region 8 is connected in series with PMOS transistors Md1 and Md2; the gate and drain of PMOS transistor Md2 are simultaneously connected to resistor R1 and the second gate 7; the other end of resistor R1, the second N+ injection region 11 and the third P+ injection region 12 are connected to the electrical cathode VSS; the first gate 6 is connected to resistor R2, and the other end of resistor R2 and the second P+ injection region 9 are connected to the electrical anode VDD.

[0032] In the SCR device of the present invention, a PMOS transistor Mp is formed by the first P+ injection region 8, the first gate 6, the second P+ injection region 9, and the lower N-well 2; an NMOS transistor Mn is formed by the first N+ injection region 10, the second gate 7, the second N+ injection region 11, and the lower P-well 3; a parasitic PNP transistor Qp is formed by the second P+ injection region 9 (equivalent to the emitter region), the N-well 2 (equivalent to the base region), and the P-well 3 (equivalent to the collector region); a parasitic NPN transistor Qn is formed by the first N+ injection region 10 (equivalent to the collector region), the P-well 3 (equivalent to the base region), and the second N+ injection region 11 (equivalent to the emitter region); the parasitic PNP transistor Qp and the parasitic NPN transistor Qn together form the SCR1 structure; the first N+ injection region 10 is connected between the N-well 2 and the P-well 3, and the second P+ injection region 9 and the N-well 2 form a parasitic P+ / N-well diode D. p+ / Nw N-well 2 and P-substrate 1 form a parasitic N-well / P-substrate diode D. Nw / Psub The first N+ injection region 10 and the P substrate 1 form a parasitic N+ / P substrate diode D. n+ / Psub .

[0033] Both the first groove 4 and the second groove 5 are shallow grooves.

[0034] N-well 2, P-well 3, and P-substrate 1 are all made of Si material.

[0035] The first P+ implantation region 8, the second P+ implantation region 9, the first N+ implantation region 10, the second N+ implantation region 11, and the third P+ implantation region 12 are all made of Si material.

[0036] Reference Figure 3 This is an embodiment of the SCR device of the present invention. Figure 2 The equivalent circuit of the structure in the diagram.

[0037] Reference Figure 4 The layout of the SCR device of the present invention is as follows: PMOS transistors Md1, Md2, R1 and R2 are all fabricated in the same N-well as PMOS transistor Mp, and the substrates of PMOS transistors Md1, Md2 and Mp are all connected to the lower end of resistor R2; NMOS transistor Mn is disposed in P-well.

[0038] Reference Figure 5 The triggering path of the SCR device in the initial stage of ESD discharge in this invention is as follows, where D Nw / Psub and D n+ / Psub First connect in parallel, then connect together with D p+ / Nw Series connection. When an ESD event occurs, the VDD voltage rises rapidly, and the Vpg voltage is mainly determined by the aforementioned D. Nw / Psub D n+ / Psub and Dp+ / Nw The voltage drop across the junctions of the three diodes is determined by the parasitic junction capacitances. Due to this voltage division, the voltage at node Vpg will always be lower than VDD, thus turning on the PMOS transistor Mp. When the Vpd voltage rises above the sum of the threshold voltages of the diodes Md1 and Md2 of the PMOS transistors, the Vng voltage will be gradually pulled up until the NMOS transistor Mn turns on. Clearly, as the NMOS transistor Mn turns on, the voltage across the junction of the three diodes (D, D, and Vpg) will decrease. p+ / Nw The path to the NMOS transistor Mn is formed, which allows D p+ / Nw It is in a state of strong conductivity.

[0039] Reference Figure 6 The main discharge path of the SCR device in this invention during ESD discharge is as follows: the diode Dp+ / Nw is the base-emitter junction of the parasitic PNP transistor Qp. As the diode Dp+ / Nw is in a strong conducting state, it means that the parasitic PNP transistor Qp is also in a conducting state, which in turn causes the parasitic NPN transistor Qn to also conduct. At this time, a parasitic positive feedback path is formed, which rapidly discharges the ESD current.

[0040] Simulation verification:

[0041] The triggering characteristics of the SCR device of this invention under ESD events were simulated under the condition that the anode voltage rises to 3V within 10ns, remains there for 100ns, and then drops to 0V within 10ns. The simulation results are in voltage form. The simulation results are as follows: Figure 7 As shown, when the VDD voltage rises to 3V, Vpg is biased at 2.23V and Vng rises to 1.12V, indicating that the NMOS transistor Mn is turned on. This means that the parasitic positive feedback path will be triggered to conduct, thereby discharging the ESD current.

[0042] Experimental test:

[0043] The SCR device of this invention is manufactured using a 0.18μm-1.8V-CMOS process, with a device width of 50μm. The ESD characteristics of the SCR device are verified using transmission-line pulse (TLP) testing, such as... Figure 8 As shown, the SCR device of this invention has a trigger voltage of 2.35V and a sustaining voltage of 2.04V, which meets the requirement of 1.8V operating voltage; the failure current is 2.7A, and the static current at 1.8V is 3nA, indicating good overall performance.

[0044] In summary, the self-triggered SCR device of this invention utilizes parasitic capacitance for ESD event detection, thereby triggering a positive feedback structure to achieve discharge. Simultaneously, the trigger voltage can be adjusted by changing the number of MOSFETs connected to the diode. The main difference between the SCR device of this invention and the traditional DTSCR device lies in the triggering section, while the parasitic positive feedback discharge section is similar; therefore, these two devices possess similar ESD robustness. Traditional DTSCRs require several N-wells for fabricating diodes (e.g., ...). Figure 1 The increase in layout area is more significant for the D01 and D02 in the original paper; however, the SCR device of the present invention only needs to slightly enlarge the N-well to place the introduced resistor and PMOS transistors Md1 and Md2 in the N-well, so the increase in layout area is less.

Claims

1. A self-triggered SCR device, characterized in that: The substrate includes a P substrate (1), on which a first P+ injection region (8), a first gate (6), a second P+ injection region (9), a first trench (4), a first N+ injection region (10), a second gate (7), a second N+ injection region (11), a second trench (5), and a third P+ injection region (12) are sequentially disposed; and an N-well (2) is disposed below the first P+ injection region (8), the first gate (6), the second P+ injection region (9), the first trench (4), and a portion of the first N+ injection region (10); and a P-well (3) is disposed below another portion of the first N+ injection region (10), the second gate (7), the second N+ injection region (11), the second trench (5), and the third P+ injection region (12). The first P+ injection region (8) is connected in series with PMOS transistors Md1 and Md2 in sequence; the gate and drain of PMOS transistor Md2 are connected to resistor R1 and the second gate (7) at the same time; the other end of resistor R1, the second N+ injection region (11) and the third P+ injection region (12) are connected to the electrical cathode VSS; the first gate (6) is connected to resistor R2, and the other end of resistor R2 and the second P+ injection region (9) are connected to the electrical anode VDD. PMOS transistors Md1, Md2, R1, and R2 are all fabricated in the same N-well as PMOS transistor Mp, and the substrates of PMOS transistors Md1, Md2, and Mp are all connected to the lower end of resistor R2; NMOS transistor Mn is disposed in a P-well.

2. The self-triggered SCR device according to claim 1, characterized in that: The first P+ injection region (8), the first gate (6), the second P+ injection region (9), and the lower N-well (2) together constitute the PMOS transistor Mp; The first N+ injection region (10), the second gate (7), the second N+ injection region (11), and the lower P-well (3) together constitute the NMOS transistor Mn; The second P+ injection region (9), N-well (2), and P-well (3) together constitute the parasitic PNP transistor Qp; The first N+ injection region (10), P-well (3), and second N+ injection region (11) together constitute the parasitic NPN transistor Qn; The parasitic PNP transistor Qp and the parasitic NPN transistor Qn together form an SCR1 structure; The second P+ injection region (9) and the N-well (2) form a parasitic P+ / N-well diode Dp+ / Nw, the N-well (2) and the P-substrate (1) form a parasitic N-well / P-substrate diode DNw / Psub, and the first N+ injection region (10) and the P-substrate (1) form a parasitic N+ / P-substrate diode Dn+ / Psub.

3. The self-triggered SCR device according to claim 1, characterized in that: Both the first groove (4) and the second groove (5) are shallow grooves.

4. The self-triggered SCR device according to claim 1, characterized in that: The N-well (2), P-well (3), and P-substrate (1) are all made of Si material.

5. The self-triggered SCR device according to claim 1, characterized in that: The first P+ implantation region (8), the second P+ implantation region (9), the first N+ implantation region (10), the second N+ implantation region (11), and the third P+ implantation region (12) are all made of Si material.

Images