A transition metal sulfide-based tunneling field effect transistor having a surface state region and a method of manufacturing the same

Abstract

The application relates to a transition metal sulfide-based tunneling field effect transistor with a surface electronic state region and a preparation method thereof, which comprises the following parts: a channel: a gate and an oxide layer are prepared on a thin film of transition metal sulfide, and the area covered by the oxide layer and the gate is the channel; electrodes at both ends of the channel: a source electrode and a drain electrode; and a surface electronic state region: atoms at the junction of the electrodes and the channel are cut off to form a fracture surface, and atoms or groups are adsorbed on the fracture surface to saturate the broken atomic bonds, so that the surface electronic state region is formed. Different atoms or groups are adsorbed on the dangling bonds at the interface of the transition metal sulfide, which is favorable for increasing the tunneling probability of the tunneling field effect transistor, thereby increasing the on-state current, and has great guiding significance for the application of low-power-consumption tunneling field effect transistors in future microelectronic devices.

Description

Technical Field

[0001] This invention relates to the field of electronic device technology, and in particular to a tunneling field-effect transistor based on transition metal sulfides with surface electronic state regions and its fabrication method. Background Technology

[0002] As traditional field-effect transistors (FETs) approach their miniaturization limits, a replacement device structure is needed in the post-Moore's Law era. Over the past decade, tunneling field-effect transistors (TEFETs) have attracted widespread attention due to their low power consumption caused by low subthreshold swing. Furthermore, TEEFETs based on transition metal sulfides have been fabricated and extensively studied.

[0003] Unlike conventional field-effect transistors (FETs), tunneling field-effect transistors (FETs) achieve conductivity through inter-band tunneling. This means that charge carriers need to pass through a tunneling barrier to reach the other electrode. However, the existence of the tunneling barrier makes the on-state current of a tunneling FET much smaller than that of a conventional FET made of the same material, which greatly limits the application and development of tunneling FETs.

[0004] To address the issue of low on-state current in tunneling field-effect transistors (TFTSs), current research primarily focuses on heterojunctions formed between narrow bandgap materials and the channel. However, the interface matching between narrow bandgap materials and common channel materials limits the choice of electrode materials, and the effectiveness of this method decreases as the bandgap shrinks. To reduce the influence of the tunneling barrier, methods such as van der Waals heterojunctions have also been extensively studied; however, current TFTSs with high on-state current still lag behind conventional TFTSs made of the same materials by several orders of magnitude. Currently, no TFTS has been reported to have an on-state current on the same order of magnitude as conventional TFTSs made of the same materials. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention proposes a tunneling field-effect transistor (TFET) based on transition metal sulfides with surface electronic state regions.

[0006] The present invention also proposes a method for fabricating the above-mentioned tunneling field-effect transistor.

[0007] The technical solution of this invention is as follows:

[0008] A tunneling field-effect transistor based on a transition metal sulfide with surface electronic state regions includes:

[0009] Channel: A gate and an oxide layer are formed on a thin film of transition metal sulfide, and the area covered by the oxide layer and the gate is the channel;

[0010] The electrodes at both ends of the channel are the source and drain, respectively.

[0011] And the surface electronic state region: cut off the atoms at the junction of the electrode and the channel to form a cross-section, and adsorb atoms or groups on the cross-section to saturate the broken atomic bonds, forming the surface electronic state region.

[0012] According to a preferred embodiment of the present invention, the transition metal sulfide is any one of MoS2, MoSe2, MoTe2, WS2, WSe2, and WTe2.

[0013] According to a preferred embodiment of the present invention, the atom is any one of H, N, O, F, Cl and Br, and the group is any one of OH, NH3 and NH2.

[0014] The fabrication method of the aforementioned tunneling field-effect transistor includes:

[0015] A gate and an oxide layer are fabricated on a thin film of a transition metal sulfide. The area covered by the gate and oxide layer is called a channel, and the two ends of the channel are two electrodes.

[0016] The junction between the channel and the two electrodes is cut off, and atoms or groups are adsorbed on the cross-section to form a surface electronic state region;

[0017] The two electrodes are heavily doped with P-type and N-type doping respectively to form the source and drain electrodes, and the surface electronic state regions are doped in the same way as the adjacent electrodes.

[0018] According to a preferred embodiment of the present invention, the junction between the cutting channel and the two electrodes includes: cutting the thin film of the transition metal sulfide, and cutting the formed vacuum layer.

[0019] According to a preferred embodiment of the present invention, the two electrodes are subjected to P-type and N-type heavy doping, respectively, including: P-type heavy doping of the source electrode and N-type heavy doping of the drain electrode.

[0020] According to a preferred embodiment of the present invention, the source is heavily p-type doped and the drain is heavily n-type doped, with a doping concentration of 3 × 10⁻⁶. 20 e / cm 3 Up to 2×10 21 e / cm 3 .

[0021] A further preferred doping concentration is 8 × 10⁻⁶. 20 e / cm 3 .

[0022] The beneficial effects of this invention are as follows:

[0023] As can be seen from the above technical solutions, the tunneling field-effect transistor based on transition metal sulfides with surface electronic state regions and its preparation method have at least one or more of the following beneficial effects:

[0024] This invention uses transition metal sulfides as electrode and channel materials, and saturates the dangling bonds at the electrode-channel interface by cleaving the transition metal sulfides and adsorbing atoms or groups. This generates surface electronic states in the tunneling barrier, which assist carrier tunneling, thereby increasing the tunneling probability and significantly improving the on-state current. This tunneling field-effect transistor can achieve on-state currents of the same order of magnitude as conventional field-effect transistors made of the same material, with a much smaller subthreshold swing. This has significant guiding significance for tunneling field-effect transistors as a new generation of low-power devices. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the fabrication method of a tunneling field-effect transistor based on transition metal sulfides according to an embodiment of the present invention;

[0026] Figure 2(a) is a schematic diagram of the atomic configuration of the WTe2 surface contact in an embodiment of the present invention;

[0027] Figure 2(b) is a schematic diagram of the electronic band structure and density of states of the WTe2 surface contact in an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the atomic configuration of the surface electronic state region according to an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the structure of a tunneling field-effect transistor with surface electronic state regions according to an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of the tunneling field-effect transistor without a surface electronic state region according to an embodiment of the present invention;

[0031] Figure 6(a) is a schematic diagram of the projected local density of states (PLDOS) and the energy distribution of the current in the tunneling field-effect transistor with surface electronic state region in an embodiment of the present invention.

[0032] Figure 6(b) is a schematic diagram of the projected local density of states (PLDOS) and the energy distribution of the current in the tunneling field-effect transistor without surface electronic state region in the embodiment of the present invention.

[0033] Figure 7(a) is a schematic diagram of the transfer and output characteristics of the tunneling field-effect transistor with surface electronic state region in an embodiment of the present invention.

[0034] Figure 7(b) is a schematic diagram of the transfer and output characteristics of the tunneling field-effect transistor without surface electronic state region in the embodiment of the present invention.

[0035] Figure 8(a) is a schematic diagram of the main performance of eight tunneling field-effect transistors with surface electronic state regions and tunneling field-effect transistors based on other materials in the embodiments of the present invention;

[0036] Figure 8(b) is a schematic diagram of the main performance of the eight types of tunneling field-effect transistors without surface electronic state regions and tunneling field-effect transistors based on other materials in the embodiments of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0038] Certain embodiments of the present invention will be described more fully below with reference to the accompanying drawings, some of which, but not all, will be shown. In fact, various embodiments of the invention may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to enable the invention to meet applicable legal requirements.

[0039] Example 1

[0040] A tunneling field-effect transistor based on a transition metal sulfide with surface electronic state regions includes:

[0041] Channel: A gate and an oxide layer are formed on a thin film of transition metal sulfide, and the area covered by the oxide layer and the gate is the channel;

[0042] The electrodes at both ends of the channel are the source and drain, respectively.

[0043] And surface electronic state regions: These are formed by severing atoms at the junction of the electrode and the channel to create a cross-section, and then adsorbing atoms or groups onto this cross-section to saturate the broken atomic bonds, thus forming surface electronic state regions. The tunneling field-effect transistor with surface electronic state regions shown in the image is illustrated using oxygen atom adsorption as an example. Device results based on surface electronic state regions of other atoms or groups are shown in Figures 8(a) and 8(b).

[0044] This invention adsorbs different atoms or groups onto the dangling bonds at the transition metal sulfide interface. These atoms or groups can introduce surface electronic states within the band gap of the tunneling barrier region. These surface states can assist carrier tunneling, thus increasing the tunneling probability of the tunneling field-effect transistor and consequently increasing its on-state current. This invention has significant guiding significance for the application of low-power tunneling field-effect transistors in future microelectronic devices.

[0045] Example 2

[0046] The difference between the tunneling field-effect transistor based on transition metal sulfides with surface electronic state regions described in Example 1 and the one described in Example 1 is as follows:

[0047] The transition metal sulfide is any one of MoS2, MoSe2, MoTe2, WS2, WSe2, and WTe2.

[0048] The atoms are any one of H, N, O, F, Cl and Br, and the groups are any one of OH, NH3 and NH2.

[0049] Example 3

[0050] The fabrication method of the tunneling field-effect transistor described in Example 1 or 2, such as Figure 1 As shown, it includes:

[0051] Step S110: A gate and an oxide layer are prepared on a thin film of transition metal sulfide. The area covered by the gate and oxide layer is called the channel, and the two ends of the channel are two electrodes. The area covered by the oxide layer and gate is the channel, while the other areas are electrodes, so as to distinguish the electrodes from the channel.

[0052] Step S120: Cut off the junction between the channel and the two electrodes, and adsorb atoms or groups on the cut surface to saturate the broken atomic bonds and form a surface electronic state region;

[0053] Step S130: The two electrodes are heavily doped with P-type and N-type doping respectively to form the source and drain. The surface electronic state region is doped in the same way as its adjacent electrode. This forms a PIN-type tunneling field-effect transistor. The surface electronic state region is chosen to be located at the electrode-channel interface to introduce surface electronic states into the tunneling barrier, thereby increasing the tunneling probability and thus increasing the on-state current.

[0054] Example 4

[0055] The difference between the method for fabricating the tunneling field-effect transistor described in Example 3 and the method described in Example 3 is that:

[0056] The process involves cutting the junction between the channel and the two electrodes, including cutting the thin film of the transition metal sulfide and cutting the resulting vacuum layer.

[0057] The two electrodes are heavily doped with P-type and N-type doping respectively, including: heavily doping the source electrode with P-type doping and heavily doping the drain electrode with N-type doping.

[0058] The source is heavily p-type doped and the drain is heavily n-type doped, with a doping concentration of 3 × 10⁻⁶. 20 e / cm 3 Up to 2×10 21 e / cm 3 .

[0059] Example 5

[0060] The difference between the fabrication method of the tunneling field-effect transistor described in Example 4 and the method described in Example 4 is as follows:

[0061] Doping concentration is 8×10 20 e / cm 3 This helps to reduce the width of the tunnel barrier.

[0062] Specifically, in this embodiment, the transition metal sulfide is WTe2, and the atoms adsorbed in the surface electronic state region are O.

[0063] Figure 2(a) shows a schematic diagram of the atomic configuration of the WTe2 surface contact; Figure 2(b) shows a schematic diagram of the electronic band structure and density of states of the WTe2 surface contact. The band gap of WTe2 is approximately 1 eV, which results in a larger tunneling barrier and lower off-state current compared to common narrow band gap materials, while a smaller tunneling barrier and larger on-state current compared to common wide band gap materials. For ease of demonstration, WTe2 with a moderate band gap is used as an example.

[0064] Figure 3 This is a schematic diagram of the atomic configuration of the surface electronic state region in this embodiment; Figure 4 This is a schematic diagram of the tunneling field-effect transistor with surface electronic state regions in this embodiment; Figure 5 This is a schematic diagram of the tunneling field-effect transistor (TFET) without surface electronic state regions in this embodiment. By adsorbing different atoms or groups onto WTe2, different surface electronic state regions can be formed. When this surface electronic state region is placed at the electrode-channel interface of the TFET, it can be seen that the surface electronic state region is still located in the electrode extension region on one side of the electrode, which also indicates that it will be heavily doped like the electrode. For TFETs without surface electronic state regions, both the electrode and the channel are made of WTe2, and the range of the electrode and the channel is distinguished by doping.

[0065] Figure 6(a) shows the projected local density of states (PLDOS) and current energy distribution of the tunneling field-effect transistor with surface electronic state regions in this embodiment; Figure 6(b) shows the projected local density of states (PLDOS) and current energy distribution of the tunneling field-effect transistor without surface electronic state regions in this embodiment. The tunneling field-effect transistor without surface electronic state regions has a significant potential barrier at the electrode-channel interface, which makes the tunneling probability of charge carriers low, and thus the on-state current of the tunneling field-effect transistor is low; while the tunneling field-effect transistor with surface electronic state regions has a large number of surface electronic states in the potential barrier at the electrode-channel interface due to the presence of surface electronic state regions. These surface electronic states assist charge carrier tunneling, which greatly increases the on-state current compared with the case without surface electronic states. As can be seen from the current energy distribution, the tunneling field-effect transistor with surface electronic states has a relatively large current distribution throughout the entire bias window, while the one without surface electronic states only has a relatively obvious current distribution within a small energy range. This is also the result of surface electronic states assisting tunneling, which occupies almost the entire bias window.

[0066] Figure 7(a) is a schematic diagram of the transfer and output characteristics of the tunneling field-effect transistor with surface electronic state regions in this embodiment. Figure 7(b) is a schematic diagram of the transfer and output characteristics of the tunneling field-effect transistor without surface electronic state regions in this embodiment. The on-state current of the tunneling field-effect transistor with surface electronic state regions is significantly greater than that of the tunneling field-effect transistor without surface electronic state regions because the surface electronic state regions assist in tunneling. It is worth noting that the on-state here is defined by the International Roadmap for Devices and Systems (IRDS) 2028 standard, which first defines a voltage with a current of 0.1 μA / μm as the off-state voltage, and then increases or decreases the bias voltage by an equal value to define the on-state. The on-state current of the tunneling field-effect transistor with surface electronic state regions has reached the standards of IRDS 2028 and the International Technology Roadmap for Semiconductors (ITRS) for high-performance devices (HP). Since this standard is set for traditional field-effect transistors, tunneling field-effect transistors that meet this standard can demonstrate that the surface electronic state region has a significant effect on improving device performance.

[0067] Figure 8(a) shows the main performance characteristics of the eight tunneling field-effect transistors with surface electronic state regions and those based on other materials in this embodiment; Figure 8(b) shows the main performance characteristics of the eight tunneling field-effect transistors without surface electronic state regions and those based on other materials in this embodiment. The tunneling field-effect transistors with surface electronic state regions and those based on other materials exhibit similar performance characteristics in various key parameters (on-state current, off-state current, subthreshold swing SS, on / off ratio I). on / I off In comparisons, it holds an advantage. Among various tunneling field-effect transistors (TFTEs) with surface electronic state regions, the on-state current is greater than that of TFTEs without surface electronic state regions. The subthreshold swing depends on the type of atoms or groups in the surface electronic state regions, varying between TFTEs without surface electronic state regions and those without. TFTEs with surface electronic state regions also have an advantage over TFTEs based on other materials with high on-state current, again stemming from the gain of the on-state current from the surface electronic state regions. The increase in on-state current does not sacrifice the device's on / off ratio because the surface electronic state regions also affect the off-state. However, since the off-state barrier of TFTEs is very large and the off-state current is very low, and the on-state current is the main factor limiting its application, increasing the on-state current while maintaining the on / off ratio is a highly advantageous approach.

[0068] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments; those skilled in the art can easily modify or substitute them, for example:

[0069] Based on the above description, those skilled in the art should have a clear understanding of the tunneling field-effect transistor based on transition metal sulfides with surface electronic state regions disclosed herein and its fabrication method.

[0070] In summary, this disclosure selects transition metal sulfides as the material for tunneling field-effect transistors (TEFETs) and forms surface electronic state regions by adsorbing atoms or groups on the cross-section. This increases the tunneling probability by introducing surface electronic states into the tunneling barrier, thereby significantly enhancing the on-state current of the TFET. This has significant guiding significance for the application and development of TFETs.

[0071] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure.

[0072] Furthermore, the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are merely illustrative of embodiments of this disclosure. Additionally, any reference numerals placed between parentheses in the claims should not be construed as limiting the scope of the claims.

[0073] Unless otherwise stated, the numerical parameters in this specification and the appended claims are approximate values ​​and can be varied according to desired characteristics derived from the content of this disclosure. Specifically, all figures used in the specification and claims to indicate composition, reaction conditions, etc., should be understood to be modified by the term "about" in all cases. Generally, this means that a specific amount may vary by ±10% in some embodiments, ±5% in some embodiments, ±1% in some embodiments, and ±0.5% in some embodiments.

[0074] Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0075] Furthermore, unless specifically described or required to occur in a specific order, the order of the above steps is not limited to those listed above and can be varied or rearranged according to the desired design. Moreover, the above embodiments can be used in combination with each other or with other embodiments based on design and reliability considerations; that is, technical features from different embodiments can be freely combined to form more embodiments.

[0076] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the disclosure, in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof. However, this approach to disclosure should not be construed as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, the aspects of the disclosure consist of fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the disclosure.

[0077] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A tunneling field-effect transistor based on a transition metal sulfide with surface electronic state regions, characterized in that, include: Channel: A gate and an oxide layer are formed on a thin film of transition metal sulfide, and the area covered by the oxide layer and the gate is the channel; The electrodes at both ends of the channel are the source and drain, respectively. And the surface electronic state region: cut off the atoms at the junction of the electrode and the channel to form a cross-section, and adsorb atoms or groups on the cross-section to saturate the broken atomic bonds, forming the surface electronic state region; The atom is any one of H, N, O, F, Cl, and Br; The group is any one of OH, NH3, and NH2.

2. A tunneling field-effect transistor based on a transition metal sulfide with a surface electronic state region according to claim 1, characterized in that, The transition metal sulfide is any one of MoS2, MoSe2, MoTe2, WS2, WSe2, and WTe2.

3. The method for fabricating the tunneling field-effect transistor according to claim 1 or 2, characterized in that, include: A gate and an oxide layer are fabricated on a thin film of a transition metal sulfide. The area covered by the gate and oxide layer is called a channel, and the two ends of the channel are two electrodes. The junction between the channel and the two electrodes is cut off, and atoms or groups are adsorbed on the cross-section to form a surface electronic state region; The two electrodes are heavily doped with P-type and N-type doping respectively to form the source and drain electrodes, and the surface electronic state regions are doped in the same way as the adjacent electrodes.

4. The method for fabricating a tunneling field-effect transistor according to claim 3, characterized in that, The junction between the cutting channel and the two electrodes includes cutting the thin film of the transition metal sulfide, and the vacuum layer formed by the cutting is 5~15 Å.

5. The method for fabricating a tunneling field-effect transistor according to claim 3, characterized in that, The two electrodes are heavily doped with P-type and N-type doping respectively, including: heavily doping the source electrode with P-type doping and heavily doping the drain electrode with N-type doping.

6. The method for fabricating a tunneling field-effect transistor according to claim 5, characterized in that, The source is heavily p-type doped and the drain is heavily n-type doped, with a doping concentration of 3 × 10⁻⁶. 20 e / cm 3 Up to 2×10 21 e / cm 3 .

7. The method for fabricating a tunneling field-effect transistor according to claim 6, characterized in that, Doping concentration is 8×10 20 e / cm 3 .

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