PWM_PFM mode DCDC output ripple suppression circuit and control method

Abstract

The application discloses a circuit and a control method for reducing output ripple of PWM / PFM mode DCDC in light load, comprising a skip cycle enabling circuit, a PWM / PFM mode judging circuit and a ripple suppression circuit. When the circuit is in light load, an error amplifier generates a SKIP_EN skip cycle enabling signal, the SKIP_EN enters the PWM / PFM mode judging circuit to judge whether the skip cycle condition is met, when the load is light enough, a Sleep signal is generated, and the circuit is switched from the PWM mode to the PFM mode. The Sleep signal enters a ripple suppression circuit composed of logic gates and delay circuits to generate a Close_EN signal, and part of PMOS power tubes are closed, so that the inductance current peak value is reduced, and the output ripple suppression is realized.

Description

Technical Field

[0001] This invention belongs to the field of CMOS integrated circuits, specifically relating to a PWM_PFM mode DC-DC output ripple suppression circuit and control method. Background Technology

[0002] Switching power supplies (DC-DC converters) can operate under varying load current conditions. In applications similar to mobile devices, these devices are mostly in sleep or standby mode, consuming little current. Therefore, a power management system is needed to improve efficiency under low load conditions. Currently, there are two main methods to address this issue. The first method uses PSM (Power Controlled Oscillator) frequency conversion control technology. This technology uses an error amplifier to control the frequency of the voltage-controlled oscillator, achieving frequency variation under full load conditions. The frequency has a square-law relationship with the load current. This method improves efficiency while reducing output ripple under light loads; however, full-load frequency conversion increases the EMI noise of the DC-DC converter. Therefore, the second method is more commonly used: PWM-PFM modulation. A dedicated circuit is typically designed to automatically switch the chip from PWM mode to PFM mode under low load current to reduce the average current consumption within the chip, thereby improving efficiency. However, in PFM mode, the chip's operating frequency is modulated and decreases periodically, causing the output voltage ripple to increase as the frequency decreases. This increased ripple limits the application of power supply chips in high-speed, high-precision systems because the resulting noise is difficult to eliminate and may even cause logic errors.

[0003] Therefore, designing a circuit that improves efficiency while reducing output voltage ripple is of great importance for improving the performance of DC-DC converters. Summary of the Invention

[0004] The purpose of this invention is to provide a PWM_PFM mode DC-DC output ripple suppression circuit and control method to solve the problem of large output voltage ripple when the DC-DC circuit enters PWM mode under light load.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] See Figure 1This is a PWM_PFM mode DC-DC output ripple suppression circuit, mainly composed of three parts: a ripple suppression circuit, a main loop, and peripheral circuits. The ripple suppression circuit consists of a mode switching circuit (PWM_PFM Control), a ripple reduction circuit, and an OR gate. The main loop consists of an error amplifier (EA), a pulse width modulation circuit (PWM), an oscillator (OSC), a logic circuit (LOGIC), a driver circuit (DRIVER), and a power transistor (POWERMOS). The peripheral circuit consists of an inductor (LX), a load capacitor (Cload), and voltage divider resistors (RH and RL), where Rload represents the load.

[0007] In the main loop, the feedback signal FB is generated by dividing the output signal Vout using voltage divider resistors RH and RL, serving as the inverting input signal of the error amplifier. The reference signal VREF serves as the non-inverting input signal of the error amplifier EA. The two outputs of the error amplifier EA, SKIP_EN and EA_OUT, are controlled by the FB signal, with one of the outputs, EA_OUT, serving as the non-inverting input signal of the PWM. The inverting input signal SEN of the PWM is generated by POWERMOS. The PWM output signal PWM_OUT, together with the output OSC_OUT of the oscillator OSC, serves as the two input signals of the logic circuit LOGIC, generating the PRE_DRV signal. The PRE_DRV signal is then processed by the internal circuitry of the LOGIC to generate the P_PREDRV1-P_PREDRV3 and N_PREDRV1-N_PREDRV3 signals. P_PREDRV1 is controlled by the ripple suppression circuit to output a Close signal. Close, along with P_PREDRV2-P_PREDRV3 and N_PREDRV1-N_PREDRV3, are input to the driver circuit DRIVER. The outputs P_DRV1-P_DRV3 and N_DRV1-N_DRV3 drive the PMOS power transistors P1-P3 and NMOS power transistors N1-N3, respectively.

[0008] The output SKIP_EN of the error amplifier in the main loop serves as the input to the mode switching circuit PWM_PFM Control in the ripple suppression circuit. The output Sleep of the mode switching circuit PWM_PFM Control is input to the ripple reduction circuit to generate the Close_EN signal. Close_EN and P_PREDRV1 generated in the main loop are input to the OR gate, and the Close signal output of the OR gate is input to the driver circuit of the main loop to participate in the generation of P_DRV1. Under light load conditions, the output of EA is clamped low, and SKIP_EN becomes high. When the SKIP_EN signal is high for a sufficiently long time, indicating a sufficiently light load, the Sleep signal becomes high, and this signal enters the LOGIC logic control circuit to operate in PFM mode. When the load is large, the SKIP_EN signal remains low, or the SKIP_EN signal is high for an insufficient time, and the Sleep signal remains low, and the circuit will operate in PWM mode. When the circuit is operating in PFM mode, the Close signal will keep P_DRV1 high for the first few cycles when the PMOS power transistors P2-P3 are turned on, so P1 being turned off has no effect during this period.

[0009] The inductor LX in the peripheral circuit is connected to the power transistor in the main circuit. The power transistor periodically switches on and off, charging and discharging the energy storage element LX and Cload, ultimately generating a stable voltage Vout. Under light load, the ripple magnitude of Vout is related to the peak value of the current ILX flowing through inductor LX. Therefore, if P1 is turned off in the first few cycles under light load, ILX will decrease, and the Vout ripple will decrease.

[0010] like Figure 2 The diagram shows the waveforms of the SKIP_EN and Sleep signals. Under light load, the output Vout voltage increases cycle by cycle. When it rises high enough, the output of the error amplifier EA is clamped at a low clamping value, at which point the circuit generates a high-level SKIP_EN signal. If the duration of SKIP_EN is greater than t... del Then, a high-level Sleep signal will be generated, which will turn off all power transistors P1-P3 and N1-N3. The output voltage begins to decrease during the high Sleep phase. When it drops to a certain value, the skip-cycle circuit in the error amplifier EA determines that the output SKIP_EN signal has gone low, the circuit exits Sleep mode, and the switching transistors resume normal operation. The entire process of entering and exiting Sleep mode achieves frequency modulation, i.e., PFM mode.

[0011] like Figure 3The waveform shown is the control signal generated by the light load ripple suppression circuit. The generation of a Sleep signal indicates that the circuit is under light load conditions. The Sleep signal, gate circuits, and delay circuits are used to generate the inverted Sleep signal XSleep, the delayed XSleep signal XSleep_Delay, and the inverted XSleep_Delay signal XXSleep_Delay. The XSleep signal and XXSleep_Delay are then ANDed to generate the Close_EN signal.

[0012] like Figure 4 The diagram shows the ripple suppression effect of the ripple suppression circuit. Without the ripple suppression circuit, the peak value of the inductor current is high, resulting in a larger output voltage ripple. When the circuit includes the ripple suppression circuit, the inductor current decreases, and the output voltage ripple decreases.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] 1. The circuit structure is simple. It only needs to use the existing Sleep signal in the PWM_PFM mode DC-DC converter as the input signal of the ripple suppression circuit, and add some gate circuits and delay circuits to achieve ripple suppression in light load mode.

[0015] 2. The turn-off time and number of PMOS power transistors can be freely configured according to design requirements, providing a high degree of design freedom. Attached Figure Description

[0016] Figure 1 It is a system framework for a PWM_PFM mode DC-DC converter;

[0017] Figure 2 This is a waveform diagram of the SKIP_EN and Sleep signals;

[0018] Figure 3 It is the waveform of the control signal generated by the light load ripple suppression circuit;

[0019] Figure 4 This is a schematic diagram illustrating the ripple suppression effect of the ripple suppression circuit; Detailed Implementation

[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0021] See Figure 1A light-load output ripple suppression DC-DC circuit based on PWM_PFM mode is presented. The feedback signal FB and the reference signal VREF serve as inputs to the error amplifier EA. Under light load conditions, the output of EA is low-clamped, and EA outputs an enable signal SKIP_EN that switches between PWM and PFM modes. This signal enters the PWM_PFM mode judgment circuit for evaluation. If the SKIP_EN high-level signal lasts long enough, indicating a sufficiently light load, a Sleep high-level signal is generated, controlling the circuit to operate in PFM mode. When the load is large, no SKIP_EN high-level signal is generated, or the generated SKIP_EN high-level signal is not long enough, and the circuit operates in PWM mode. PWM_OUT and OSC_OUT serve as inputs to the RS flip-flops in the logic circuit, generating switching signals for the power transistors. P_DRV1-P_DRV3 are control signals for the PMOS power transistors, and N_DRV1-N_DRV3 are control signals for the NMOS power transistors.

[0022] See Figure 2 The diagram shows the waveforms of the SKIP_EN and Sleep signals. Under light load, the output Vout voltage increases cycle by cycle. When it rises high enough, the output of the error amplifier EA is clamped at a low clamping value, at which point the circuit generates a high-level SKIP_EN signal. If the duration of the high-level SKIP_EN signal is greater than t... del Then, a high-level Sleep signal will be generated, which will turn off all power transistors P1-P3 and N1-N3. The output voltage begins to decrease during the high Sleep phase. When it drops to a certain value, the SKIP_EN signal output by the error amplifier EA goes low, the circuit exits Sleep mode, and the switching transistors operate normally. The entire process of entering and exiting Sleep mode achieves frequency modulation, i.e., PFM mode.

[0023] See Figure 3The waveform of the control signal generated by the light load ripple suppression circuit. A high-level Sleep signal indicates the circuit is under light load conditions. The Sleep signal, gate circuits, and delay circuits generate the inverted Sleep signal XSleep, the delayed XSleep signal XSleep_Delay, and the inverted XSleep_Delay signal XXSleep_Delay, respectively. The XSleep signal and XXSleep_Delay are ANDed to generate the Close_EN signal. The Close_EN signal and P_PREDRV1 are used as inputs to an OR gate. The Close output, along with P_PREDRV2-P_PREDRV3 and N_PREDRV1-N_PREDRV3, are passed through a driver circuit to improve the driving capability. The driver circuit outputs P_DRV1-P_DRV3 and N_DRV1-N_DRV3, respectively, drive PMOS power transistors P1-P3 and NMOS power transistors N1-N3. When the load is light, the Close_EN signal generated by the ripple suppression circuit will turn off a group of PMOS power transistors in the first few operating cycles, thereby reducing the peak inductor current and reducing output ripple. The power transistor turn-off time is determined by Sleep, t del It is related to the operating frequency of the circuit, and the circuit design can be configured by the user.

[0024] See Figure 4 The diagram illustrates the ripple suppression effect of the ripple suppression circuit. Without the ripple suppression circuit, the peak value of the inductor current is high, resulting in a large output voltage ripple. When the circuit includes the ripple suppression circuit, the inductor current decreases, thus reducing the output voltage ripple.

[0025] The above examples and illustrations are not intended to limit the product form and style of the present invention, nor do they constitute any limitation on the present invention. Obviously, different changes and improvements can be made to the circuit under the concept of the present invention, but these are all within the scope of protection of the present invention.

Claims

1. A PWM / PFM mode DC-DC output ripple suppression circuit, mainly composed of three parts: ripple suppression circuit, main loop and peripheral circuit; The ripple suppression circuit consists of a mode switching circuit PWM / PFM Control, a ripple reduction circuit, and an OR gate; the main loop consists of an error amplifier EA, a pulse width modulation circuit PWM, an oscillator OSC, a logic circuit LOGIC, a driver circuit DRIVER, and a power transistor POWERMOS; the peripheral circuit consists of an inductor LX, a load capacitor Cload, and voltage divider resistors RH and RL, where Rload represents the load. In the main loop, the feedback signal FB is generated by dividing the output signal Vout through voltage divider resistors RH and RL, serving as the inverting input signal of the error amplifier; the reference signal VREF serves as the non-inverting input signal of the error amplifier EA; the two outputs SKIP_EN and EA_OUT of the error amplifier EA are controlled by the FB signal, with one of the outputs EA_OUT serving as the non-inverting input signal of the PWM; the inverting input signal SEN of the PWM is generated by POWERMOS; the PWM output signal PWM_OUT and the output OSC_OUT of the oscillator OSC together serve as the two input signals of the logic circuit LOGIC. The PRE_DRV signal is generated; the PRE_DRV signal is processed by the internal circuit of the LOGIC to generate P_PREDRV1-P_PREDRV3 and N_PREDRV1-N_PREDRV3 signals; P_PREDRV1 is controlled by the ripple suppression circuit to output a Close signal, and Close, along with P_PREDRV2-P_PREDRV3 and N_PREDRV1-N_PREDRV3, is input to the driver circuit DRIVER, which outputs P_DRV1-P_DRV3 and N_DRV1-N_DRV3 to drive PMOS power transistors P1-P3 and NMOS power transistors N1-N3 respectively; The output SKIP_EN of the error amplifier in the main loop is used as the input of the mode switching circuit PWM / PFM Control in the ripple suppression circuit; the output Sleep of the mode switching circuit PWM / PFM Control is input to the ripple suppression circuit Ripple Reduction to generate the Close_EN signal; Close_EN and P_PREDRV1 generated in the main loop are input to the OR gate OR, and the Close signal output by the OR gate OR is input to the driver circuit DRIVER of the main loop to participate in the generation of P_DRV1; the inductor LX in the peripheral circuit is connected to the power transistor in the main circuit, and the power transistor periodically switches to charge and discharge the energy storage element LX and Cload, eventually generating a stable voltage Vout.

2. A control method based on the PWM / PFM mode DC-DC output ripple suppression circuit as described in claim 1, characterized in that: Under light load conditions, the output of EA is low-clamped, and SKIP_EN will become high. When the SKIP_EN signal is high for a long enough time, it means that the load is light enough, and the Sleep signal becomes high. This signal enters the logic circuit LOGIC control circuit and operates in PFM mode. When the load is large, the SKIP_EN signal remains low, or the SKIP_EN signal is high for a short time, and the Sleep signal remains low, the circuit will operate in PWM mode. When the circuit is operating in PFM mode, the Close signal keeps P_DRV1 high for the first few cycles when the PMOS power transistors P2-P3 are turned on, so P1 is turned off and has no effect during this period. Under light load, the output voltage Vout increases cycle by cycle. When it rises high enough, the output of the error amplifier EA is clamped at a low clamping value, at which point the circuit generates a high-level SKIP_EN signal. If the duration of SKIP_EN is greater than t... del Then a high-level Sleep signal will be generated, which will turn off all power transistors P1-P3 and N1-N3; the output voltage Vout will start to drop during the high Sleep phase. When it drops to a certain value, the skip-cycle circuit in the error amplifier EA will determine that the output SKIP_EN signal has gone low, the circuit will exit Sleep, and the switching transistors will resume normal operation; the entire process of entering and exiting Sleep mode realizes the modulation of the operating frequency, i.e., PFM mode. When a Sleep signal is generated, it indicates that the circuit is under light load conditions. The Sleep signal, gate circuit, and delay circuit are used to generate the inverted Sleep signal XSleep signal, the delayed XSleep signal XSleep_Delay signal, and the inverted XSleep_Delay signal XXSleep_Delay signal, respectively. The XSleep signal and XXSleep_Delay signal are ANDed to generate the Close_EN signal.

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