Wireless device, chip and intermediate frequency circuit therefor

Abstract

The application provides a wireless device, a chip, a transmitter and a intermediate frequency circuit, wherein a first differential current signal is input to a common terminal of a first bias MOS tube and a first input amplification MOS tube in a first branch; an output terminal of a third constant current source is grounded through a first bias MOS tube and a second input amplification MOS tube in a second branch, and is grounded through a fourth constant current source; a second differential current signal is input to a common terminal of a first bias MOS tube and a second input amplification MOS tube in the second branch; an input terminal of the fourth constant current source is connected to a gate of the second input amplification MOS tube and a gate of a second mixing amplification MOS tube; gates of the first bias MOS tube in the first branch and the first bias MOS tube in the second branch are commonly input with a first bias voltage; and the first adaptive bias circuit adjusts the first bias voltage to a first set bias voltage when the first bias voltage deviates from the first set bias voltage.

Description

Technical Field

[0001] This invention relates to the field of wireless communication, and more specifically to wireless devices, chips, and intermediate frequency circuits thereof. Background Technology

[0002] In wireless communication systems, baseband digital signals often need to be amplified and up-converted by intermediate frequency circuits to form intermediate frequency signals. These intermediate frequency signals are then amplified and up-converted by radio frequency circuits to form radio frequency signals, which are finally transmitted through an antenna.

[0003] In existing technologies, some solutions use two differential circuit branches (which contain differential amplifier MOSFETs) in the intermediate frequency circuit amplifier section to differentially amplify the two differential analog currents output from the current-to-analog converter. However, since the voltage output by the current-to-analog converter will actually fluctuate, this will cause changes in the DC bias point of the differential circuit branch, thereby reducing the linearity of the differential circuit. Summary of the Invention

[0004] Based on the above situation, the main objective of this invention is to provide wireless devices, chips, and intermediate frequency circuits to improve the linearity of intermediate frequency circuits.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] An intermediate frequency (IF) circuit for a wireless transmitter includes a first differential branch, a second differential branch, a first mixer-amplifier MOSFET, a second mixer-amplifier MOSFET, and a first adaptive bias circuit. The first differential branch includes a first constant current source, a second constant current source, a first bias MOSFET in the first branch, and a first input amplifier MOSFET. The second differential branch includes a third constant current source, a fourth constant current source, a second bias MOSFET in the second branch, and a second input amplifier MOSFET. The output terminal of the first constant current source is grounded through the first bias MOSFET and the first input amplifier MOSFET in the first branch, and also grounded through the second constant current source. A first differential current signal is input to the common terminal of the first bias MOSFET and the first input amplifier MOSFET in the first branch. The input terminal of the second constant current source is connected to the gate of the first input amplifier MOSFET and the gate of the first mixer-amplifier MOSFET. The first mixer-amplifier MOSFET outputs a first differential mixing current to the first input terminal of the mixer under the voltage drive of the gate of the first input amplifier MOSFET. The third constant current source... The output terminal of the current source is grounded through the first bias MOSFET and the second input amplifier MOSFET of the second branch, and also grounded through the fourth constant current source; a second differential current signal is input to the common terminal of the first bias MOSFET and the second input amplifier MOSFET of the second branch; the input terminal of the fourth constant current source is connected to the gate of the second input amplifier MOSFET and the gate of the second mixer amplifier MOSFET, and the second mixer amplifier MOSFET is used to output a second differential mixer current to the second input terminal of the mixer under the voltage drive of the gate of the second input amplifier MOSFET; wherein, the first constant current source and the third constant current source are of the same magnitude, the second constant current source and the fourth constant current source are of the same magnitude, and the first constant current source is greater than the second constant current source; the gates of the first bias MOSFET of the first branch and the first bias MOSFET of the second branch are jointly input with a first bias voltage; the first adaptive bias circuit is used to detect the first bias voltage, and when the first bias voltage deviates from the first set bias voltage, adjust the first bias voltage to the first set bias voltage.

[0007] Preferably, the intermediate frequency circuit further includes a second adaptive bias circuit; the first differential branch further includes a first branch second bias MOS transistor, and the second differential branch further includes a second branch second bias MOS transistor; the output terminal of the first constant current source is grounded through the first branch second bias MOS transistor and the second constant current source; the input terminal of the second constant current source and the common terminal of the first branch second bias MOS transistor are connected to the gate of the first input amplifier MOS transistor and the gate of the first mixer amplifier MOS transistor; the output terminal of the third constant current source is grounded through the second branch second bias MOS transistor and the fourth constant current source; the input terminal of the fourth constant current source and the common terminal of the second branch second bias MOS transistor are connected to the gate of the second input amplifier MOS transistor and the gate of the second mixer amplifier MOS transistor; the gates of the first branch second bias MOS transistor and the second branch second bias MOS transistor share a second bias voltage; the second adaptive bias circuit is used to detect the second bias voltage, and when the second bias voltage deviates from the second set bias voltage, adjust the second bias voltage to the second set bias voltage.

[0008] Preferably, the first adaptive bias circuit includes a fifth constant current source, a sixth constant current source, a first bias detection MOSFET, and a first bias adjustment MOSFET; the output terminal of the fifth constant current source is connected to the gates of the first bias MOSFET of the first branch and the first bias MOSFET of the second branch, the gate of the first bias detection MOSFET, and grounded through the first bias adjustment MOSFET; the power supply voltage is grounded through the first bias detection MOSFET and the sixth constant current source; the common terminal of the input terminals of the first bias detection MOSFET and the sixth constant current source is connected to the gate of the first bias adjustment MOSFET.

[0009] Preferably, the second adaptive bias circuit includes a seventh constant current source, an eighth constant current source, a second bias detection MOSFET, and a second bias adjustment MOSFET; the output terminal of the seventh constant current source is connected to the gates of the first branch second bias MOSFET and the second branch second bias MOSFET, the gate of the second bias detection MOSFET, and grounded through the second bias adjustment MOSFET; the power supply voltage is grounded through the second bias detection MOSFET and the eighth constant current source; the common terminal of the input terminal of the second bias detection MOSFET and the eighth constant current source is connected to the gate of the second bias adjustment MOSFET.

[0010] Preferably, the intermediate frequency circuit further includes a first resistor, a second resistor, and a first capacitor; the gate of the first input amplifying MOS transistor is connected to the gate of the first mixing amplifying MOS transistor through the first resistor; the gate of the second input amplifying MOS transistor is connected to the gate of the second mixing amplifying MOS transistor through the second resistor; and the first capacitor is connected across the gates of the first mixing amplifying MOS transistor and the second mixing amplifying MOS transistor.

[0011] Preferably, the intermediate frequency circuit further includes a third resistor, a fourth resistor, and a second capacitor; the gate of the first input amplifying MOS transistor is connected to the gate of the first mixing amplifying MOS transistor through the first resistor and the third resistor; the gate of the second input amplifying MOS transistor is connected to the gate of the second mixing amplifying MOS transistor through the second resistor and the fourth resistor; the first capacitor is connected across the common terminal of the first resistor and the third resistor and the common terminal of the second resistor and the fourth resistor; the second capacitor is connected across the gates of the first mixing amplifying MOS transistor and the second mixing amplifying MOS transistor.

[0012] Preferably, the intermediate frequency circuit further includes a first linearity correction circuit and a second linearity correction circuit. During the initial correction stage, both the first differential current signal and the second differential current signal are zero. The first linearity correction circuit compares the magnitude of the first reference voltage with the gate voltage of the first input amplifying MOS transistor. When the gate voltage of the first input amplifying MOS transistor is greater than the first reference voltage, the first linearity correction circuit controls the decrease of the constant current value output by the first constant current source. When the gate voltage of the first input amplifying MOS transistor is less than the first reference voltage, the first linearity correction circuit controls the increase of the constant current value output by the first constant current source. The second linearity correction circuit compares the magnitude of the second reference voltage with the gate voltage of the second input amplifying MOS transistor. When the gate voltage of the second input amplifying MOS transistor is greater than the second reference voltage, the second linearity correction circuit controls the decrease of the constant current value output by the third constant current source. When the gate voltage of the second input amplifying MOS transistor is less than the second reference voltage, the second linearity correction circuit controls the increase of the constant current value output by the third constant current source.

[0013] Preferably, the first linearity correction circuit includes a first comparator and a first current selection register. The first constant current source includes multiple first sub-constant current source branches, each of which includes a first sub-constant current source and a first switch. Each first switch is controlled by a corresponding bit of the first current selection register. The second linearity correction circuit includes a second comparator and a second current selection register. The third constant current source includes multiple third sub-constant current source branches, each of which includes a third sub-constant current source and a second switch. Each second switch is controlled by a corresponding bit of the second current selection register. In the initial correction stage, the first current selection register has a first initial value. The first comparator compares the first reference voltage with the gate voltage of the first input amplifying MOSFET at a certain frequency. If the gate voltage of the first input amplifying MOSFET is greater than the first reference voltage, the first comparator outputs a control signal to control the first current selection register to decrement the first initial value by 1 each time it detects that the gate voltage of the first input amplifying MOSFET is greater than the first reference voltage. This process continues until the first comparator detects the first initial value a set number of times. The gate voltage of the first input amplifier MOSFET is less than the first reference voltage. Based on the value of the first current selection register at this time, the first switch of each first sub-constant current source branch is controlled. During the initial calibration phase, the second current selection register has a second initial value. The second comparator compares the second reference voltage with the gate voltage of the second input amplifier MOSFET at a certain frequency. If the gate voltage of the second input amplifier MOSFET is greater than the second reference voltage, the second comparator, upon detecting that the gate voltage of the second input amplifier MOSFET is greater than the second reference voltage, outputs a control signal to decrement the second current selection register by a bit of 1 from the second initial value. This continues until the second comparator detects that the gate voltage of the second input amplifier MOSFET is less than the second reference voltage a set number of times. Based on the value of the second current selection register at this time, the second switch of each third sub-constant current source branch is controlled. Wherein, when the first reference voltage and the second reference voltage are equal, a bit in the values ​​of the first current selection register and the second current selection register is 1 when the corresponding switch is turned on, and 0 when the corresponding switch is turned off.

[0014] Preferably, the first linearity correction circuit includes a first comparator and a first current selection register. The first constant current source includes multiple first sub-constant current source branches, each of which includes a first sub-constant current source and a first switch. Each first switch is controlled by a corresponding bit of the first current selection register. The second linearity correction circuit includes a second comparator and a second current selection register. The third constant current source includes multiple third sub-constant current source branches, each of which includes a third sub-constant current source and a second switch. Each second switch is controlled by a corresponding bit of the second current selection register. In the initial correction stage, the first current selection register has a first initial value. The first comparator compares the first reference voltage with the gate voltage of the first input amplifying MOSFET at a certain frequency. If the gate voltage of the first input amplifying MOSFET is less than the first reference voltage, the first comparator outputs a control signal to control the first current selection register to add a bit 1 to the first initial value each time it detects that the gate voltage of the first input amplifying MOSFET is less than the first reference voltage. This process continues until the first comparator detects the first current a certain number of times. The gate voltage of the first input amplifier MOSFET is greater than the first reference voltage. Based on the value of the first current selection register at this time, the first switch of each first sub-constant current source branch is controlled. During the initial calibration phase, the second current selection register has a second initial value. The second comparator compares the second reference voltage with the gate voltage of the second input amplifier MOSFET at a certain frequency. If the gate voltage of the second input amplifier MOSFET is less than the second reference voltage, the second comparator, upon detecting that the gate voltage of the second input amplifier MOSFET is less than the second reference voltage, outputs a control signal to add a bit 1 to the second current selection register based on the second initial value. This continues until the second comparator detects that the gate voltage of the second input amplifier MOSFET is greater than the second reference voltage a set number of times. Based on the value of the second current selection register at this time, the second switch of each third sub-constant current source branch is controlled. Wherein, when the first reference voltage and the second reference voltage are equal, a bit in the values ​​of the first current selection register and the second current selection register is 1 when the corresponding switch is turned on, and 0 when the corresponding switch is turned off.

[0015] The present invention also provides a wireless transmitter, including any of the intermediate frequency circuits described above, and further including a current digital-to-analog converter, the current digital-to-analog converter being used to output the first differential current signal and the second differential current signal.

[0016] Preferably, the wireless transmitter further includes a mixer, wherein a first input terminal of the mixer is used to input the first differential mixing current and a second input terminal is used to input the second differential mixing current.

[0017] The present invention also provides a wireless chip, including the aforementioned wireless transmitter.

[0018] The present invention also provides a wireless device, including the aforementioned wireless chip.

[0019] In this scheme, the same first bias voltage is applied to the gates of the first bias MOS transistor in the first branch and the first bias MOS transistor in the second branch. The first adaptive bias circuit detects the first bias voltage and adjusts it to the first set bias voltage when the first bias voltage deviates from the first set bias voltage. This stabilizes the voltage at the common terminal of the first bias MOS transistor and the first input amplifier MOS transistor in the first branch, as well as the common terminal of the first bias MOS transistor and the second input amplifier MOS transistor in the second branch, at the first set bias voltage. This avoids a decrease in the linearity of the first bias MOS transistor in the first branch and the first bias MOS transistor in the second branch, thereby preventing a deterioration in the linearity of the intermediate frequency circuit.

[0020] Other beneficial effects of the present invention will be explained in detail through the introduction of specific technical features and technical solutions in specific embodiments. Those skilled in the art should be able to understand the beneficial technical effects brought about by these technical features and technical solutions through the introduction of these technical features and technical solutions. Attached Figure Description

[0021] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. In the drawings:

[0022] Figure 1 This is a circuit diagram of a wireless device according to an embodiment of the present invention;

[0023] Figure 2 This is a circuit diagram of a first adaptive bias circuit according to an embodiment of the present invention;

[0024] Figure 3 This is a circuit diagram of a second adaptive bias circuit according to an embodiment of the present invention;

[0025] Figure 4 This is a circuit diagram of a wireless device according to another embodiment of the present invention;

[0026] Figure 5 The circuit diagram shows a first linearity correction circuit and a first constant current source according to an embodiment of the present invention.

[0027] Figure 6 The circuit diagram shows the second linearity correction circuit and the third constant current source according to one embodiment of the present invention. Detailed Implementation

[0028] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail, but well-known methods, processes, procedures, and elements are not described in detail in order to avoid obscuring the essence of the present invention.

[0029] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0030] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0031] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0032] Figure 1 This is a circuit diagram of a wireless device according to an embodiment of the present invention. The wireless device includes a wireless transmitter and an antenna. The wireless transmitter includes a current-to-analog converter, an intermediate frequency circuit, a mixer, a transformer T, and a power amplifier PA. The current-to-analog converter, the intermediate frequency circuit, and the mixer can be integrated into a single wireless chip.

[0033] The digital signal carrying digital information is converted into an analog first differential current signal and a second differential current signal after passing through a current-to-analog converter. The first differential current signal and the second differential current signal are processed by an intermediate frequency circuit to form a first differential mixing current and a second differential mixing current. The first differential mixing current and the second differential mixing current are fed into a mixer for mixing to obtain a high-frequency signal. The high-frequency signal is isolated and coupled by a transformer T and input to a power amplifier PA. After being amplified by the power amplifier PA, it is transmitted through an antenna to form a wireless signal.

[0034] The intermediate frequency circuit includes a first differential branch, a second differential branch, a first mixer-amplifier MOSFET M7, a second mixer-amplifier MOSFET M8, and a first adaptive bias circuit. The first differential branch includes a first constant current source I1, a second constant current source I2, a first bias MOSFET M1 in the first branch, and a first input amplifier MOSFET M2. The second differential branch includes a third constant current source I3, a fourth constant current source I4, a first bias MOSFET M4 in the second branch, and a second input amplifier MOSFET M5. In this embodiment, the first mixer-amplifier MOSFET M7, the second mixer-amplifier MOSFET M8, the first input amplifier MOSFET M2, the second input amplifier MOSFET M5, the first bias MOSFET M1 in the first branch, and the first bias MOSFET M4 in the second branch are all N-channel MOSFETs.

[0035] The output terminal of the first constant current source I1 is grounded through the first bias MOSFET M1 and the first input amplifier MOSFET M2 in the first branch, and also grounded through the second constant current source I2; the first differential current signal is input to the common terminal A of the first bias MOSFET M1 and the first input amplifier MOSFET M2 in the first branch; the input terminal of the second constant current source I2 is connected to the gate of the first input amplifier MOSFET M2 and the gate of the first mixer amplifier MOSFET M7, and the first mixer amplifier MOSFET M7 is used to output the first differential mixer current to the first input terminal of the mixer under the voltage drive of the gate of the first input amplifier MOSFET M2.

[0036] The output terminal of the third constant current source I3 is grounded through the first bias MOSFET M4 and the second input amplifier MOSFET M5 in the second branch, and also grounded through the fourth constant current source I4; the second differential current signal is input to the common terminal B of the first bias MOSFET M4 and the second input amplifier MOSFET M5 in the second branch; the input terminal of the fourth constant current source I4 is connected to the gate of the second input amplifier MOSFET M5 and the gate of the second mixer amplifier MOSFET M8, which is used to output the second differential mixer current to the second input terminal of the mixer under the voltage drive of the gate of the second input amplifier MOSFET M5.

[0037] The first constant current source I1 and the third constant current source I3 are of the same magnitude, the second constant current source I2 and the fourth constant current source I4 are of the same magnitude, and the first constant current source I1 is greater than the second constant current source I2; the first constant current source I1 and the second constant current source I2 together provide bias current for the first input amplifier MOSFET M2 to operate in the linear region, and similarly, the third constant current source I3 and the fourth constant current source I4 together provide bias current for the second input amplifier MOSFET M5 to operate in the linear region.

[0038] The gates of the first bias MOSFET M1 in the first branch and the first bias MOSFET M4 in the second branch share the first bias voltage vb1. The first adaptive bias circuit is used to detect the first bias voltage vb1 and adjust the first bias voltage vb1 to the first set bias voltage when the first bias voltage vb1 deviates from the first set bias voltage.

[0039] The working process of this wireless transmitter is as follows.

[0040] The current-to-analog converter outputs a first differential current signal to the common terminal A. The current flowing through the first input amplifier MOSFET M2 consists of two parts: one part is the first differential current signal, and the other part is the current flowing out of the first bias MOSFET M1 in the first branch. Therefore, the current flowing through the first input amplifier MOSFET M2 will change with the first differential current signal. According to the square law formula of MOSFET, this change will cause a change in the gate voltage of the first input amplifier MOSFET M2, thus completing the process of converting the first differential current signal into a voltage signal. The gate voltage of the first input amplifier MOSFET M2 drives the first mixer amplifier MOSFET M7 to work, thereby outputting the first differential mixer current to the first input terminal of the mixer, thus completing the process of converting voltage into current. Similarly, the current-to-analog converter outputs a second differential current signal to the common terminal B. The current flowing through the second input amplifier MOSFET M5 consists of two parts: one part is the second differential current signal, and the other part is the current flowing out of the first bias MOSFET M4 in the second branch. Therefore, the current flowing through the second input amplifier MOSFET M5 will change with the second differential current signal. According to the square law formula of MOSFET, this change will cause a change in the gate voltage of the second input amplifier MOSFET M5, thus completing the process of converting the second differential current signal into a voltage signal. The gate voltage of the second input amplifier MOSFET M5 drives the second mixer amplifier MOSFET M8 to work, thereby outputting the second differential mixer current to the first input terminal of the mixer, thus completing the process of converting voltage into current.

[0041] The formula for the square law is: Right now: Among them, I d V is the current flowing through the MOSFET. th V is the gate-source threshold voltage of the MOSFET. gs U is the gate-source voltage of the MOSFET, W is the gate width of the MOSFET, L is the channel length of the MOSFET, and u is the gate-source voltage of the MOSFET. n It is electron mobility, C ox It is the gate capacitance of the MOSFET.

[0042] Because the current flowing into the common terminal A of the first differential current signal fluctuates, the voltage of the common terminal A fluctuates, which in turn causes fluctuations in the gate voltage of the first bias MOSFET M1 in the first branch. This results in a deterioration in the linearity of the first bias MOSFET M1 in the first branch, and consequently, a deterioration in the linearity of the intermediate frequency circuit. Similarly, because the current flowing into the common terminal B of the second differential current signal fluctuates, the voltage of the common terminal B fluctuates, which in turn causes fluctuations in the gate voltage of the first bias MOSFET M4 in the second branch. This results in a deterioration in the linearity of the first bias MOSFET M4 in the second branch, and consequently, a deterioration in the linearity of the intermediate frequency circuit. In this embodiment, the same first bias voltage vb1 is applied to the gates of the first bias MOSFET M1 in the first branch and the first bias MOSFET M4 in the second branch. The first adaptive bias circuit detects the first bias voltage vb1. When the first bias voltage vb1 deviates from the first set bias voltage, the first bias voltage vb1 is adjusted to the first set bias voltage, thereby stabilizing the voltages of the common terminals A and B at the first set bias voltage. This avoids a decrease in the linearity of the first bias MOSFET M1 in the first branch and the first bias MOSFET M4 in the second branch, and thus avoids a deterioration in the linearity of the intermediate frequency circuit.

[0043] In some embodiments, the intermediate frequency circuit further includes a second adaptive bias circuit, the first differential branch further includes a first branch second bias MOS transistor M3, and the second differential branch further includes a second branch second bias MOS transistor M6; the output terminal of the first constant current source I1 is grounded through the first branch second bias MOS transistor M3 and the second constant current source I2; the input terminal of the second constant current source I2 is connected to the gate of the first input amplification MOS transistor M2 and the gate of the first mixer amplification MOS transistor M7 through the common terminal of the first branch second bias MOS transistor M3; the output terminal of the third constant current source I3 is grounded through the second branch second bias MOS transistor M6. The bias MOSFET M6 and the fourth constant current source I4 are grounded; the input terminal of the fourth constant current source I4 and the common terminal of the second bias MOSFET M6 in the second branch are connected to the gate of the second input amplifier MOSFET M5 and the gate of the second mixer amplifier MOSFET M8; the gates of the first branch second bias MOSFET M3 and the second branch second bias MOSFET M6 share the second bias voltage vb2; the second adaptive bias circuit is used to detect the second bias voltage vb2, and when the second bias voltage vb2 deviates from the second set bias voltage, it adjusts the second bias voltage vb2 to the second set bias voltage. In this embodiment, both the first branch second bias MOSFET M3 and the second branch second bias MOSFET M6 are P-channel MOSFETs.

[0044] In this embodiment, by adding the second bias MOSFET M3 in the first branch, the voltage fluctuation at the drain of the first bias MOSFET M1 in the first branch can be reduced, thereby ensuring the linearity of the first bias MOSFET M1 in the first branch as much as possible; similarly, by adding the second bias MOSFET M6 in the second branch, the linearity of the first bias MOSFET M4 in the second branch can be ensured as much as possible. Furthermore, as mentioned earlier, fluctuations in the current flowing from the first differential current signal into the common terminal A will cause voltage fluctuations in the gate of the first input amplification MOS transistor M2, which in turn will cause voltage fluctuations in the gate of the first branch second bias MOS transistor M3. Therefore, in this embodiment, the same second bias voltage vb2 is applied to the gates of the first branch second bias MOS transistor M3 and the second branch second bias MOS transistor M6. The second adaptive bias circuit detects the second bias voltage vb2. When the second bias voltage vb2 deviates from the second set bias voltage, it adjusts the second bias voltage vb2 to the second set bias voltage, thereby stabilizing the voltages of the common terminals A and B at the second set bias voltage. This avoids the reduction in linearity of the first branch second bias MOS transistor M3 and the second branch second bias MOS transistor M6 caused by the fluctuations, and thus avoids a deterioration in the linearity of the intermediate frequency circuit.

[0045] In some embodiments, the first adaptive bias circuit includes a fifth constant current source I5, a sixth constant current source I6, a first bias detection MOSFET M10, and a first bias adjustment MOSFET M9. The output terminal of the fifth constant current source I5 is connected to the gates of the first bias MOSFET M1 in the first branch and the first bias MOSFET M4 in the second branch, the gate of the first bias detection MOSFET M10, and grounded through the first bias adjustment MOSFET M9. The output terminal of the fifth constant current source I5 outputs the first bias voltage vb1. The power supply voltage VCC is grounded through the first bias detection MOSFET M10 and the sixth constant current source I6. The common terminal of the input terminals of the first bias detection MOSFET M10 and the sixth constant current source I6 is connected to the gate of the first bias adjustment MOSFET M9. In this embodiment, both the first bias detection MOSFET M10 and the first bias adjustment MOSFET M9 are N-channel MOSFETs. During operation, if the first bias voltage vb1 is greater than the first set bias voltage, due to the effect of the sixth constant current source I6, the source voltage of the first bias detection MOS transistor M10 will also increase when the first bias voltage vb1 increases, which will cause the gate voltage of the first bias adjustment MOS transistor M9 to also increase. This will promote the reduction of the drain voltage of the first bias adjustment MOS transistor M9, returning it to the first set bias voltage.

[0046] In some embodiments, the second adaptive bias circuit includes a seventh constant current source I7, an eighth constant current source I8, a second bias detection MOSFET M12, and a second bias adjustment MOSFET M11. The output terminal of the seventh constant current source I7 is connected to the gates of the first branch second bias MOSFET M3 and the second branch second bias MOSFET M6, the gate of the second bias detection MOSFET M12, and grounded through the second bias adjustment MOSFET M11. The power supply voltage VCC is grounded through the second bias detection MOSFET M12 and the eighth constant current source I8. The common terminal of the input terminals of the second bias detection MOSFET M12 and the eighth constant current source I8 is connected to the gate of the second bias adjustment MOSFET M11. In this embodiment, both the second bias detection MOSFET M12 and the second bias adjustment MOSFET M11 are N-channel MOSFETs. During operation, if the second bias voltage vb2 is greater than the second set bias voltage, due to the effect of the eighth constant current source I8, the source voltage of the second bias detection MOSFET M12 will also increase when the second bias voltage vb2 increases, which will cause the gate voltage of the second bias adjustment MOSFET M11 to also increase. This will promote the reduction of the drain voltage of the second bias adjustment MOSFET M11, returning it to the second set bias voltage.

[0047] In some embodiments, the intermediate frequency circuit further includes a first resistor R1, a second resistor R2, and a first capacitor C1 capable of implementing first-order filtering; the gate of the first input amplifying MOSFET M2 is connected to the gate of the first mixing amplifying MOSFET M7 through the first resistor R1; the gate of the second input amplifying MOSFET M5 is connected to the gate of the second mixing amplifying MOSFET M8 through the second resistor R2; and the first capacitor C1 is connected across the gates of the first mixing amplifying MOSFET M7 and the second mixing amplifying MOSFET M8.

[0048] In some embodiments, to achieve second-order filtering, the intermediate frequency circuit further includes a third resistor R3, a fourth resistor R4, and a second capacitor C2; the gate of the first input amplifying MOSFET M2 is connected to the gate of the first mixing amplifying MOSFET M7 through the first resistor R1 and the third resistor R3; the gate of the second input amplifying MOSFET M5 is connected to the gate of the second mixing amplifying MOSFET M8 through the second resistor R2 and the fourth resistor R4; the first capacitor C1 is connected between the common terminal of the first resistor R1 and the third resistor R3 and the common terminal of the second resistor R2 and the fourth resistor R4; the second capacitor C2 is connected between the gates of the first mixing amplifying MOSFET M7 and the second mixing amplifying MOSFET M8.

[0049] like Figure 4As shown, in some embodiments, to avoid the impact of differences between the first input amplifying MOSFET M2 and the second input amplifying MOSFET M5, and internal current variations on the linearity of the first input amplifying MOSFET M2 and the second input amplifying MOSFET M5, and to achieve better linearity in the intermediate frequency circuit, the intermediate frequency circuit also includes a first linearity correction circuit and a second linearity correction circuit for correcting the linearity of the intermediate frequency circuit. During the initial correction phase (e.g., during the power-on process of the intermediate frequency circuit), both the first differential current signal and the second differential current signal are zero. The first linearity correction circuit compares the first reference voltage Vref1 with the gate voltage VC of the first input amplifying MOSFET M2. When the gate voltage VC of the first input amplifying MOSFET M2 is greater than the first reference voltage Vref1, the first linearity correction circuit controls the decrease of the constant current value output by the first constant current source I1. When the gate voltage VC of the first input amplifying MOSFET M2 is less than the first reference voltage Vref1, the first linearity correction circuit controls the increase of the constant current value output by the first constant current source I1. The second linearity correction circuit compares the second reference voltage Vref2 with the gate voltage VD of the second input amplifier MOSFET M5. When the gate voltage VD of the second input amplifier MOSFET M5 is greater than the second reference voltage Vref2, the second linearity correction circuit controls the decrease of the constant current value output by the third constant current source I3. When the gate voltage VD of the second input amplifier MOSFET M5 is less than the second reference voltage Vref2, the second linearity correction circuit controls the increase of the constant current value output by the third constant current source I3. Once the correction is completed, it will not be performed again during subsequent operation until the initial correction stage is entered again, such as when power is turned on again. In this embodiment, the gate voltage VC of the first input amplifier MOSFET M2 is used to control the magnitude of the first current source I1, and the gate voltage VD of the second input amplifier MOSFET M5 is used to control the magnitude of the third current source I3, so that the gate voltage VC of the first input amplifier MOSFET M2 is kept as close as possible to the linear operating region, thereby improving the linearity of the intermediate frequency circuit.

[0050] In one embodiment, such as Figure 5 As shown, the first linearity correction circuit includes a first comparator and a first current selection register. The non-inverting and inverting inputs of the first comparator can respectively input a first reference voltage Vref1 and the gate voltage VC of the first input amplifying MOSFET M2. The first constant current source I1 includes multiple first sub-constant current source branches. Each first sub-constant current source branch includes a first sub-constant current source and a first switch. Each first switch is controlled by a corresponding bit in the first current selection register, such as... Figure 5 As shown, the nth (n is an integer greater than 1) first sub-constant current source branch includes the first sub-constant current source I. 1n and the first switch K 1n ;like Figure 6As shown, the second linearity correction circuit includes a second comparator and a second current selection register. The non-inverting and inverting inputs of the second comparator can respectively input the second reference voltage Vref2 and the gate voltage VD of the second input amplifying MOSFET M5. The third constant current source I3 includes multiple third sub-constant current source branches. Each third sub-constant current source branch includes a third sub-constant current source and a second switch. Each second switch is controlled by a corresponding bit in the second current selection register, such as... Figure 6 As shown, the nth (n is an integer greater than 1) third sub-constant current source branch includes the third sub-constant current source I. 3n Second switch K 3n In this configuration, a bit in the first current selection register and the second current selection register is 1 when the corresponding switch is turned on, and 0 when the corresponding switch is turned off. In this embodiment, the first reference voltage Vref1 and the second reference voltage Vref2 are equal, and can be obtained by dividing the voltage VDD using a resistor divider circuit.

[0051] During the initial calibration phase, the first current selection register has a first initial value (e.g., 1000 bits). The first comparator compares the first reference voltage Vref1 with the gate voltage VC of the first input amplifier MOSFET M2 at a frequency (typically, the first comparator compares very quickly, i.e., the frequency is high). If the gate voltage VC of the first input amplifier MOSFET M2 is greater than the first reference voltage Vref1, the first comparator outputs a control signal (e.g., outputs a low level) to control the first current selection register in the first initial calibration phase. The value is decreased by 1 until the first comparator detects that the gate voltage VC of the first input amplifier MOSFET M2 is less than the first reference voltage Vref1 after a set number of consecutive tests. The first switch of each first sub-constant current source branch is controlled according to the value of the first current selection register at this time. For example, the value of the first current selection register is not updated until the first comparator detects that the gate voltage VC of the first input amplifier MOSFET M2 is less than the first reference voltage Vref1 for the first time. The first comparator stops comparing when the first comparator detects that the gate voltage VC of the first input amplifier MOSFET M2 is less than the first reference voltage Vref1 after a set number of consecutive tests.

[0052] During the initial calibration phase, the second current selection register has a second initial value (e.g., 1000 bits). The second comparator compares the second reference voltage Vref2 with the gate voltage VD of the second input amplifier MOSFET M5 at a frequency (typically, the first comparator compares very quickly, i.e., this frequency is high). If the gate voltage VD of the second input amplifier MOSFET M5 is greater than the second reference voltage Vref2, the second comparator, upon detecting that the gate voltage VD of the second input amplifier MOSFET M5 is greater than the second reference voltage Vref2, outputs a control signal (e.g., outputs a low level) to control the second current selection register to decrement the second initial value by 1 bit. The second comparator continues to adjust the gate voltage VD of the second input amplifier MOSFET M5 until it detects a value less than the second reference voltage Vref2 after a set number of consecutive tests. Based on the value of the second current selection register at this time, the second switch of each third sub-constant current source branch is controlled. For example, if the second comparator first detects a value less than the second reference voltage Vref2 for the first time, the value of the second current selection register is not updated. The second comparator stops comparing the gate voltage VD of the second input amplifier MOSFET M5 until it detects a value less than the second reference voltage Vref2 after a set number of consecutive tests (e.g., 2, 3, or 4 times). In this embodiment, by setting a second initial value with a predetermined number of bits, the current selection register can more precisely adjust the first constant current source I1 and the third constant current source I3, which is more beneficial for the linearity correction of the intermediate frequency circuit.

[0053] Table 1 shows an example of the calibration process in a certain initial calibration phase in one embodiment, including the comparator output signal, the number of comparisons, the value of the current selection register before the update, and the value of the current selection register after the update. As can be seen from Table 1, the initial value of the current selection register is 1000. During the first three comparisons of the comparator, the comparator output signal is low level 0, indicating that the gate voltage (VC or VD) is greater than the reference voltage. Until the fourth comparison, the comparator output signal becomes high level 1, indicating that the gate voltage (VC or VD) is less than the reference voltage. From this point on, the current selection register remains unchanged at 0101. Finally, the constant current source is controlled with 0101, that is, the second and fourth switches are turned on, and the remaining switches are turned off.

[0054] Table 1

[0055]

[0056] In one embodiment, during the initial calibration phase, the first current selection register has a first initial value (e.g., 1000 bits). A first comparator compares the first reference voltage Vref1 with the gate voltage VC of the first input amplification MOSFET M2 at a frequency (typically, the first comparator compares very quickly, i.e., the frequency is high). If the gate voltage VC of the first input amplification MOSFET M2 is less than the first reference voltage Vref1, the first comparator, upon detecting that the gate voltage VC of the first input amplification MOSFET M2 is less than the first reference voltage Vref1, outputs a control signal (e.g., a high level) to control the first current selection register in the first calibration phase. An initial value is incremented by a bit of 1 until the first comparator detects that the gate voltage VC of the first input amplifier MOSFET M2 is greater than the first reference voltage Vref1 after a set number of consecutive tests. Based on the value of the first current selection register at this point, the first switch of each first sub-constant current source branch is controlled. For example, if the first comparator first detects that the gate voltage VC of the first input amplifier MOSFET M2 is greater than the first reference voltage Vref1 for the first time, the value of the first current selection register is not updated. The first comparator stops comparing values ​​when the first current selection register and the second current selection register have bits of 1 that control the corresponding switch to be on, and bits of 0 that control the corresponding switch to be off.

[0057] During the initial calibration phase, the second current selection register has a second initial value (e.g., 1000 bits). The second comparator compares the second reference voltage with the gate voltage of the second input amplifier MOSFET M5 at a frequency (typically, the first comparator compares very quickly, i.e., this frequency is high). If the gate voltage VD of the second input amplifier MOSFET M5 is less than the second reference voltage Vref2, the second comparator, upon detecting that the gate voltage VD of the second input amplifier MOSFET M5 is less than the second reference voltage Vref2, outputs a control signal (e.g., a high level) to control the second current selection register to increment by a bit of the second initial value, until the second... If the comparator detects that the gate voltage VD of the second input amplifier MOSFET M5 is greater than the second reference voltage Vref2 after a set number of consecutive tests, it controls the second switch of each third sub-constant current source branch according to the value of the second current selection register at this time. For example, the value of the second current selection register is not updated until the second comparator detects that the gate voltage VD of the second input amplifier MOSFET M5 is greater than the second reference voltage Vref2 for the first time. The second comparator stops comparing when it detects that the gate voltage VD of the second input amplifier MOSFET M5 is greater than the second reference voltage Vref2 after a set number of consecutive tests (e.g., 2, 3 or 4 times).

[0058] In this embodiment, by setting a second initial value with a predetermined number of bits, the current selection register can more precisely adjust the first constant current source I1 and the third constant current source I3, which is more conducive to the linearity correction of the intermediate frequency circuit.

[0059] Table 2 shows an example of the calibration process in a certain initial calibration phase in one embodiment, including the comparator output signal, the number of comparisons, the value of the current selection register before the update, and the value of the current selection register after the update. As can be seen from Table 2, the initial value of the current selection register is 1000. During the first three comparisons of the comparator, the comparator output signal is high level 1, indicating that the gate voltage (VC or VD) is less than the reference voltage. Until the fourth comparison, the comparator output signal becomes low level 0, indicating that the gate voltage (VC or VD) is greater than the reference voltage. From this point on, the current selection register remains unchanged at 1011. Finally, 1011 is used to control the constant current source, that is, to control the first, third, and fourth switches to be turned on and to control the remaining switches to be turned off.

[0060] Table 2

[0061]

[0062] JLKJ132CN1

[0063]

[0064] Those skilled in the art will understand that, without conflict, the above-mentioned preferred solutions can be freely combined and superimposed.

[0065] It should be understood that the above embodiments are merely exemplary and not restrictive. Various obvious or equivalent modifications or substitutions that can be made by those skilled in the art regarding the above details without departing from the basic principles of the present invention will be included within the scope of the claims of the present invention.

Claims

1. An intermediate frequency circuit for a wireless transmitter, characterized in that, It includes a first differential branch circuit, a second differential branch circuit, a first mixer-amplifier MOSFET, a second mixer-amplifier MOSFET, and a first adaptive bias circuit; The first differential branch includes a first constant current source, a second constant current source, a first bias MOSFET and a first input amplifier MOSFET in the first branch, and the second differential branch includes a third constant current source, a fourth constant current source, a first bias MOSFET and a second input amplifier MOSFET in the second branch; The output terminal of the first constant current source is grounded through the first bias MOSFET and the first input amplifier MOSFET of the first branch, and also grounded through the second constant current source; the first differential current signal is input to the common terminal of the first bias MOSFET and the first input amplifier MOSFET of the first branch; The input terminal of the second constant current source is connected to the gate of the first input amplifying MOS transistor and the gate of the first mixing amplifying MOS transistor. The first mixing amplifying MOS transistor is used to output a first differential mixing current to the first input terminal of the mixer under the voltage drive of the gate of the first input amplifying MOS transistor. The output terminal of the third constant current source is grounded through the first bias MOS transistor and the second input amplification MOS transistor of the second branch, and also grounded through the fourth constant current source; the second differential current signal is input to the common terminal of the first bias MOS transistor and the second input amplification MOS transistor of the second branch; the input terminal of the fourth constant current source is connected to the gate of the second input amplification MOS transistor and the gate of the second mixer amplification MOS transistor, and the second mixer amplification MOS transistor is used to output a second differential mixing current to the second input terminal of the mixer under the voltage drive of the gate of the second input amplification MOS transistor; wherein, the first constant current source and the third constant current source are of the same magnitude, the second constant current source and the fourth constant current source are of the same magnitude, and the first constant current source is larger than the second constant current source; The gates of the first bias MOS transistor in the first branch and the first bias MOS transistor in the second branch share the first bias voltage input. The first adaptive bias circuit is used to detect the first bias voltage and adjust the first bias voltage to the first set bias voltage when the first bias voltage deviates from the first set bias voltage.

2. The intermediate frequency circuit according to claim 1, characterized in that, It also includes a second adaptive bias circuit. The first differential branch also includes a first branch second bias MOSFET, and the second differential branch also includes a second branch second bias MOSFET; The output terminal of the first constant current source is grounded through the second bias MOS transistor of the first branch and the second constant current source; the input terminal of the second constant current source and the common terminal of the second bias MOS transistor of the first branch are connected to the gate of the first input amplifier MOS transistor and the gate of the first mixer amplifier MOS transistor. The output terminal of the third constant current source is grounded through the second bias MOS transistor of the second branch and the fourth constant current source; the input terminal of the fourth constant current source is connected to the gate of the second input amplifier MOS transistor and the gate of the second mixer amplifier MOS transistor, together with the common terminal of the second bias MOS transistor of the second branch. The gates of the second bias MOS transistor in the first branch and the second bias MOS transistor in the second branch share the second bias voltage. The second adaptive bias circuit is used to detect the second bias voltage and adjust the second bias voltage to the second set bias voltage when the second bias voltage deviates from the second set bias voltage.

3. The intermediate frequency circuit according to claim 2, characterized in that, The first adaptive bias circuit includes a fifth constant current source, a sixth constant current source, a first bias detection MOSFET, and a first bias adjustment MOSFET; The output terminal of the fifth constant current source is connected to the gate of the first bias MOS transistor of the first branch and the gate of the first bias MOS transistor of the second branch, the gate of the first bias detection MOS transistor, and grounded through the first bias adjustment MOS transistor. The power supply voltage is grounded through the first bias detection MOS transistor and the sixth constant current source. The common terminal of the input terminal of the first bias detection MOS transistor and the sixth constant current source is connected to the gate of the first bias adjustment MOS transistor.

4. The intermediate frequency circuit according to claim 2, characterized in that, The second adaptive bias circuit includes a seventh constant current source, an eighth constant current source, a second bias detection MOSFET, and a second bias adjustment MOSFET; The output terminal of the seventh constant current source is connected to the gate of the second bias MOS transistor of the first branch and the second bias MOS transistor of the second branch, the gate of the second bias detection MOS transistor, and grounded through the second bias adjustment MOS transistor. The power supply voltage is grounded through the second bias detection MOS transistor and the eighth constant current source. The common terminal of the input terminal of the second bias detection MOS transistor and the eighth constant current source is connected to the gate of the second bias adjustment MOS transistor.

5. The intermediate frequency circuit according to claim 2, characterized in that, It also includes a first resistor, a second resistor, and a first capacitor; The gate of the first input amplifier MOSFET is connected to the gate of the first mixer amplifier MOSFET through the first resistor; the gate of the second input amplifier MOSFET is connected to the gate of the second mixer amplifier MOSFET through the second resistor. The first capacitor is connected across the gates of the first mixer amplifier MOS transistor and the second mixer amplifier MOS transistor.

6. The intermediate frequency circuit according to claim 5, characterized in that, It also includes a third resistor, a fourth resistor, and a second capacitor; The gate of the first input amplifier MOSFET is connected to the gate of the first mixer amplifier MOSFET through the first resistor and the third resistor; the gate of the second input amplifier MOSFET is connected to the gate of the second mixer amplifier MOSFET through the second resistor and the fourth resistor. The first capacitor is connected between the common terminal of the first and third resistors and the common terminal of the second and fourth resistors; the second capacitor is connected between the gates of the first and second mixer amplifier MOS transistors.

7. The intermediate frequency circuit according to claim 1, characterized in that, It also includes a first linearity correction circuit and a second linearity correction circuit; During the initial calibration phase, both the first differential current signal and the second differential current signal are zero. The first linearity correction circuit compares the first reference voltage with the gate voltage of the first input amplifying MOSFET. When the gate voltage of the first input amplifying MOSFET is greater than the first reference voltage, the first linearity correction circuit controls the decrease of the constant current value output by the first constant current source. When the gate voltage of the first input amplifying MOSFET is less than the first reference voltage, the first linearity correction circuit controls the increase of the constant current value output by the first constant current source. The second linearity correction circuit compares the second reference voltage with the gate voltage of the second input amplifier MOS transistor. When the gate voltage of the second input amplifier MOS transistor is greater than the second reference voltage, the second linearity correction circuit controls the decrease of the constant current value output by the third constant current source. When the gate voltage of the second input amplifier MOS transistor is less than the second reference voltage, the second linearity correction circuit controls the increase of the constant current value output by the third constant current source.

8. The intermediate frequency circuit according to claim 7, characterized in that, The first linearity correction circuit includes a first comparator and a first current selection register. The first constant current source includes multiple first sub-constant current source branches, each of which includes a first sub-constant current source and a first switch. Each first switch is controlled by a corresponding bit of the first current selection register. The second linearity correction circuit includes a second comparator and a second current selection register. The third constant current source includes multiple third sub-constant current source branches, each of which includes a third sub-constant current source and a second switch. Each second switch is controlled by a corresponding bit of the second current selection register. During the initial calibration phase, the first current selection register has a first initial value. The first comparator compares the first reference voltage with the gate voltage of the first input amplifier MOS transistor at a frequency. If the gate voltage of the first input amplifier MOS transistor is greater than the first reference voltage, the first comparator outputs a control signal to control the first current selection register to decrement the first bit by 1 from the first initial value each time it detects that the gate voltage of the first input amplifier MOS transistor is less than the first reference voltage after a set number of consecutive tests. Based on the value of the first current selection register at this time, the first switch of each first sub-constant current source branch is controlled. During the initial calibration phase, the second current selection register has a second initial value. The second comparator compares the second reference voltage with the gate voltage of the second input amplifier MOSFET at a frequency. If the gate voltage of the second input amplifier MOSFET is greater than the second reference voltage, the second comparator outputs a control signal to control the second current selection register to decrement the second initial value by 1 each time it detects that the gate voltage of the second input amplifier MOSFET is greater than the second reference voltage. This continues until the second comparator detects that the gate voltage of the second input amplifier MOSFET is less than the second reference voltage after a set number of consecutive tests. Based on the value of the second current selection register at this time, the second switch of each third sub-constant current source branch is controlled. Wherein, the first reference voltage and the second reference voltage are equal, and when the bit in the values ​​of the first current selection register and the second current selection register is 1, the corresponding switch is turned on, and when it is 0, the corresponding switch is turned off.

9. The intermediate frequency circuit according to claim 7 or 8, characterized in that, The first linearity correction circuit includes a first comparator and a first current selection register. The first constant current source includes multiple first sub-constant current source branches, each of which includes a first sub-constant current source and a first switch. Each first switch is controlled by a corresponding bit of the first current selection register. The second linearity correction circuit includes a second comparator and a second current selection register. The third constant current source includes multiple third sub-constant current source branches, each of which includes a third sub-constant current source and a second switch. Each second switch is controlled by a corresponding bit of the second current selection register. During the initial calibration phase, the first current selection register has a first initial value. The first comparator compares the first reference voltage with the gate voltage of the first input amplifier MOSFET at a frequency. If the gate voltage of the first input amplifier MOSFET is less than the first reference voltage, the first comparator outputs a control signal to control the first current selection register to add bit 1 to the first initial value each time it detects that the gate voltage of the first input amplifier MOSFET is greater than the first reference voltage. This continues until the first comparator detects that the gate voltage of the first input amplifier MOSFET is greater than the first reference voltage a set number of times. Based on the value of the first current selection register at this time, the first switch of each first sub-constant current source branch is controlled. During the initial calibration phase, the second current selection register has a second initial value. The second comparator compares the second reference voltage with the gate voltage of the second input amplifier MOSFET at a certain frequency. If the gate voltage of the second input amplifier MOSFET is less than the second reference voltage, the second comparator will output a control signal to control the second current selection register to add bit 1 to the second initial value each time it detects that the gate voltage of the second input amplifier MOSFET is greater than the second reference voltage. The second switch of each third sub-constant current source branch is controlled according to the value of the second current selection register at this time. Wherein, the first reference voltage and the second reference voltage are equal, and when the bit in the values ​​of the first current selection register and the second current selection register is 1, the corresponding switch is turned on, and when it is 0, the corresponding switch is turned off.

10. A wireless transmitter, characterized in that, The circuit includes the intermediate frequency circuit as described in any one of claims 1-9, and further includes a current digital-to-analog converter, the current digital-to-analog converter being used to output the first differential current signal and the second differential current signal.

11. The wireless transmitter according to claim 10, characterized in that, It also includes mixers, The first input terminal of the mixer is used to input the first differential mixing current, and the second input terminal is used to input the second differential mixing current.

12. A wireless chip, characterized in that, Includes the wireless transmitter as described in claim 10.

13. A wireless device, characterized in that, Including the wireless chip as described in claim 12.

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