A clock generator based on CMOS process

Abstract

The application provides a clock generator based on a CMOS process, which comprises a starting circuit, a current source, an oscillation circuit, a feedback control circuit, a sampling circuit and an output circuit; the starting circuit is used for making the first output end and the second output end of the output circuit have a voltage difference according to an enabling signal output by an external MCU; the sampling circuit is used for sampling the voltage of the first output end and the second output end of the output circuit to obtain a sampling voltage; the feedback control circuit is used for controlling the oscillation circuit to output an oscillation signal according to the sampling voltage, and is also used for sending the oscillation signal to the output circuit, so that the output circuit outputs a clock signal according to the oscillation signal; the application samples the voltage of the two output ends of the output circuit by the sampling circuit to obtain a sampling voltage, so that the feedback control circuit controls the oscillation circuit to oscillate at a predetermined frequency according to the sampling voltage, thereby making the output circuit output a stable clock signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a clock generator based on CMOS technology. Background Technology

[0002] As semiconductor devices become increasingly faster and more integrated, they are evolving towards lower power consumption, smaller size, and lower cost. Precise clock generators are also trending towards on-chip integration, higher precision, and higher frequency. Currently, the circuits that provide clock signals to various circuit chips are typically based on ring oscillators. However, these are susceptible to the influence of external power supply and temperature, resulting in poor output stability of the integrated on-chip clock circuits.

[0003] It is evident that clock circuits in existing technologies suffer from poor stability. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a clock generator based on CMOS technology, which solves the problem of poor stability in existing clock circuits.

[0005] This invention provides a clock generator based on CMOS technology. The clock generator includes: a startup circuit, a current source, an oscillation circuit, a feedback control circuit, a sampling circuit, and an output circuit. The startup circuit is connected to an external MCU and also to the output terminal of the output circuit. It is used to create a voltage difference between the first and second output terminals of the output circuit based on an enable signal output by the external MCU. The sampling circuit is connected to the output circuit and is used to sample the voltages at the first and second output terminals of the output circuit to obtain a sampled voltage. The feedback control circuit is connected to the sampling circuit, the oscillation circuit, and the output circuit respectively. It is used to control the oscillation circuit to output an oscillation signal based on the sampled voltage and also to send the oscillation signal to the output circuit so that the output circuit outputs a clock signal based on the oscillation signal. The current source is connected to the oscillation circuit and the sampling circuit respectively and is used to provide a constant current.

[0006] Optionally, the oscillation circuit includes: a first PMOS capacitor, a second PMOS capacitor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; the source of the first NMOS transistor is connected to the first output terminal of the current source through the first PMOS capacitor, and the drain of the first NMOS transistor is connected to an external power supply; the source of the second NMOS transistor is connected to the second output terminal of the current source through the second PMOS capacitor, and the drain of the second NMOS transistor is connected to an external power supply; the drain, gate, fourth gate, and fifth gate of the third NMOS transistor are respectively connected to the third output terminal of the current source, and the sources of the third, fourth, and fifth NMOS transistors are grounded; wherein, the gate of the first NMOS transistor and the gate of the second NMOS transistor serve as the first input terminal and the second input terminal of the oscillation circuit, respectively, and the drain of the first NMOS transistor and the drain of the second NMOS transistor serve as the first output terminal and the second output terminal of the oscillation circuit, respectively.

[0007] Optionally, the oscillation circuit further includes: a first programmable resistor and a second programmable resistor; a first end of the first programmable resistor is connected to the external power supply, a second end of the first programmable resistor is connected to the drain of the first NMOS transistor, and a control terminal of the first programmable resistor is connected to an external MCU; a first end of the second programmable resistor is connected to the external power supply, a second end of the second programmable resistor is connected to the drain of the second NMOS transistor, and a control terminal of the second programmable resistor is connected to an external MCU.

[0008] Optionally, each programmable resistor includes: a first register, n control switches, and n fixed resistors; the input terminal of the first register is connected to an external MCU, and the n output terminals of the first register are respectively connected to the control terminals of the n control switches, for controlling the opening and closing of each control switch according to the control signal output by the external MCU; wherein, the n control switches are connected in series, and each control switch is connected in parallel with a fixed resistor.

[0009] Optionally, the feedback control circuit includes: a programmable current source, a sixth NMOS transistor, and a seventh NMOS transistor; the gate of the sixth NMOS transistor is connected to the first output terminal of the oscillation circuit, the drain of the sixth NMOS transistor is connected to an external power supply, the source of the sixth NMOS transistor is connected to the programmable current source, and the source of the sixth NMOS transistor is also connected to the second input terminal of the oscillation circuit; the gate of the seventh NMOS transistor is connected to the second output terminal of the oscillation circuit, the drain of the seventh NMOS transistor is connected to an external power supply, the source of the seventh NMOS transistor is connected to the programmable current source, and the source of the seventh NMOS transistor is also connected to the first input terminal of the oscillation circuit.

[0010] Optionally, the sampling circuit includes an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor; the drain of the eighth NMOS transistor is connected to the feedback control circuit, the gate of the eighth NMOS transistor is connected to the first output terminal of the output circuit, the drain of the ninth NMOS transistor is connected to the feedback control circuit, and the gate of the ninth NMOS transistor is connected to the second output terminal of the output circuit; the drain of the tenth NMOS transistor is connected to the source of the eighth NMOS transistor and the source of the ninth NMOS transistor, respectively, the gate of the tenth NMOS transistor is connected to the current source, and the source of the tenth NMOS transistor is grounded.

[0011] Optionally, the output circuit includes: a first PMOS transistor, a second PMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor; the gate of the first PMOS transistor is connected to the feedback control circuit, the source of the first PMOS transistor is connected to an external power supply, and the drain of the first PMOS transistor is connected to the drain of the eleventh NMOS transistor and the gate of the twelfth NMOS transistor; the gate of the second PMOS transistor is connected to the feedback control circuit, the source of the second PMOS transistor is connected to an external power supply, and the drain of the second PMOS transistor is connected to the drain of the twelfth NMOS transistor and the gate of the eleventh NMOS transistor; the source of the eleventh NMOS transistor and the source of the twelfth NMOS transistor are grounded; the drain of the first PMOS transistor is the first output terminal of the output circuit, and the drain of the second PMOS transistor is the second output terminal of the output circuit.

[0012] Optionally, the startup circuit includes: a first register, a thirteenth NMOS transistor, and a fourteenth NMOS transistor; the input terminal of the first register is connected to an external MCU and is used to output a pulse signal according to the control signal of the external MCU; the gates of the thirteenth NMOS transistor and the fourteenth NMOS transistor are respectively connected to the output terminal of the first register, the drain of the thirteenth NMOS transistor is connected to the first output terminal of the output circuit, the drain of the fourteenth NMOS transistor is connected to the second output terminal of the output circuit, and the sources of the thirteenth NMOS transistor and the fourteenth NMOS transistor are grounded.

[0013] Optionally, the clock generator further includes a shaping circuit connected to the output terminal of the output circuit, used to shape the clock signal output by the output circuit.

[0014] Optionally, the shaping circuit includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a seventeenth NMOS transistor; the gates of the third PMOS transistor, the fourth PMOS transistor, the fifteenth NMOS transistor, and the sixteenth NMOS transistor are respectively connected to the output terminal of the output circuit; the source of the third PMOS transistor is connected to an external power supply; the drains of the third PMOS transistor and the source of the fourth PMOS transistor are respectively connected to the drain of the fifth PMOS transistor; the drains of the fourth PMOS transistor, the fifteenth NMOS transistor, and the gate of the fifth PMOS transistor are respectively connected to the gate of the seventeenth NMOS transistor; and the source of the fifteenth NMOS transistor and the drain of the sixteenth NMOS transistor are respectively connected to the drain of the seventeenth NMOS transistor.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] This invention provides a constant current to the oscillation circuit and sampling circuit through a current source, and controls the voltage difference between the two output terminals of the output circuit through a startup circuit to initialize the output circuit when the system is powered on; furthermore, the sampling circuit samples the voltage of the two output terminals of the output circuit to obtain a sampling voltage, so that the feedback control circuit controls the oscillation circuit to oscillate at a predetermined frequency according to the sampling voltage, thereby enabling the output circuit to output a stable clock signal. Attached Figure Description

[0017] Figure 1 A schematic diagram of a clock generator based on CMOS technology is provided for an embodiment of the present invention;

[0018] Figure 2 A circuit diagram of a clock generator based on CMOS technology is provided for an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of the structure of a programmable resistor provided in an embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram of a programmable current source provided in an embodiment of the present invention;

[0021] Figure 5 A circuit diagram of a startup circuit provided in an embodiment of the present invention;

[0022] Figure 6 A circuit diagram of a shaping circuit provided in an embodiment of the present invention;

[0023] Figure 7 This is a circuit diagram of a constant current source provided in an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] In the examples of this invention, functional units with the same reference numerals have the same and similar structures and functions.

[0026] Figure 1 A schematic diagram of a clock generator based on CMOS technology is provided for an embodiment of the present invention, as shown below. Figure 1 As shown, the clock generator 100 includes:

[0027] The circuit includes a startup circuit 110, a current source 120, an oscillation circuit 130, a feedback control circuit 140, a sampling circuit 150, and an output circuit 160.

[0028] The startup circuit 110 is connected to the external MCU 200 and also to the output terminal of the output circuit 160. It is used to create a voltage difference between the first output terminal and the second output terminal of the output circuit 160 according to the enable signal output by the external MCU 200.

[0029] The sampling circuit 150 is connected to the output circuit 160 and is used to sample the voltage of the first output terminal and the second output terminal of the output circuit 160 to obtain the sampled voltage.

[0030] The feedback control circuit 140 is connected to the sampling circuit 150, the oscillation circuit 130 and the output circuit 160 respectively. It is used to control the oscillation circuit 130 to output an oscillation signal according to the sampling voltage, and also to send the oscillation signal to the output circuit 160 so that the output circuit 160 outputs a clock signal according to the oscillation signal.

[0031] The current source 120 is connected to the oscillation circuit 130 and the sampling circuit 150 respectively, and is used to provide a constant current.

[0032] In this embodiment, when the system is powered on, a constant current is provided to the oscillation circuit and the sampling circuit through a current source, and a voltage difference is maintained between the two output terminals of the output circuit through a start-up circuit to initialize the output circuit. Furthermore, the sampling circuit samples the voltage of the two output terminals of the output circuit to obtain a sampling voltage, so that the feedback control circuit controls the oscillation circuit to oscillate at a predetermined frequency according to the sampling voltage, thereby enabling the output circuit to output a stable clock signal.

[0033] Figure 2 A circuit diagram of a clock generator based on CMOS technology is provided for an embodiment of the present invention, as shown below. Figure 2 As shown, the oscillation circuit 130 includes:

[0034] The system comprises a first PMOS capacitor C1, a second PMOS capacitor C2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5. The source of the first NMOS transistor N1 is connected to the first output terminal of the current source through the first PMOS capacitor C1, and the drain of the first NMOS transistor N1 is connected to an external power supply. The source of the second NMOS transistor N2 is connected to the second output terminal of the current source through the second PMOS capacitor C2, and the drain of the second NMOS transistor N2 is connected to an external power supply. The third NMOS transistor N3... The drain, the gate of the third NMOS transistor N3, the gate of the fourth NMOS transistor N4, and the gate of the fifth NMOS transistor N5 are respectively connected to the third output terminal of the current source, and the source of the third NMOS transistor N3, the source of the fourth NMOS transistor N4, and the source of the fifth NMOS transistor N5 are grounded; wherein, the gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2 serve as the first input terminal and the second input terminal of the oscillation circuit, respectively, and the drain of the first NMOS transistor N1 and the drain of the second NMOS transistor N2 serve as the first output terminal and the second output terminal of the oscillation circuit, respectively.

[0035] In this embodiment, the gate of the first PMOS capacitor is connected to the source of the first NMOS transistor, and the source and drain of the first PMOS capacitor are connected to the first output terminal of the current source. The gate of the second PMOS capacitor is connected to the source of the second NMOS transistor, and the source and drain of the second PMOS capacitor are connected to the second output terminal of the current source. The substrate of the first PMOS capacitor is connected to the source and drain of the second PMOS capacitor, and the substrate of the second PMOS capacitor is connected to the source and drain of the first PMOS capacitor. In this embodiment, capacitors C1 and C2 are CMOS devices, requiring no additional process layers, resulting in lower cost. Capacitors C1 and C2 operate in the strong inversion region, achieving maximum and stable capacitance. Furthermore, capacitors C1 and C2 have no ports directly connected to power or ground, providing strong immunity to power and ground interference, enabling the oscillation circuit to output a stable oscillation signal, thereby obtaining a highly stable clock signal.

[0036] In this embodiment, the oscillation circuit further includes: a first programmable resistor VR1 and a second programmable resistor VR2; the first terminal of the first programmable resistor VR1 is connected to the external power supply VCC, the second terminal of the first programmable resistor VR1 is connected to the drain of the first NMOS transistor, and the control terminal of the first programmable resistor VR1 is connected to the external MCU200; the first terminal of the second programmable resistor VR2 is connected to the external power supply, the second terminal of the second programmable resistor VR2 is connected to the drain of the second NMOS transistor N2, and the control terminal of the second programmable resistor VR2 is connected to the external MCU200.

[0037] It should be noted that the resistance values ​​of the first and second programmable resistors can be adjusted via an external MCU, thereby adjusting the oscillation frequency of the oscillation circuit and thus regulating the output frequency of the clock signal. The clock generator in this embodiment has a spread spectrum function, modulating the output switching frequency and expanding the spectrum at the switching frequency, thereby reducing radiated energy and exhibiting low electromagnetic radiation.

[0038] like Figure 3 As shown, in this embodiment, each programmable resistor includes: a first register, n control switches, and n fixed resistors; the input terminal of the first register is connected to an external MCU, and the n output terminals of the first register are respectively connected to the control terminals of the n control switches, for controlling the opening and closing of each control switch according to the control signal output by the external MCU; wherein, the n control switches are connected in series, and each control switch is connected in parallel with a fixed resistor.

[0039] It should be noted that this programmable resistor consists of two or more resistors connected in series, each with a control switch connected in parallel; the resistance values ​​of the series resistors in this programmable resistor increase sequentially. The opening and closing of the control switch is adjusted by a configuration register to regulate the resistance value and precision, thereby modulating the output clock frequency, expanding the spectrum at the clock frequency, and thus reducing electromagnetic radiation energy.

[0040] Furthermore, it can be seen that in current technology, oscillation circuits connect one end of the charging / discharging capacitor directly to the power supply and / or ground, thus subjecting the capacitor to interference from the power supply and / or ground. In this solution, one end of the capacitor is connected to the MOSFET, and the other end is connected to the current bias. The current bias itself has the ability to resist power supply interference, so the oscillation circuit in this solution is not affected by power supply and ground interference, resulting in a clock signal with strong anti-interference ability and high stability.

[0041] In this embodiment, the feedback control circuit includes: a programmable current source, a sixth NMOS transistor N6, and a seventh NMOS transistor N7; the gate of the sixth NMOS transistor N6 is connected to the first output terminal of the oscillation circuit, the drain of the sixth NMOS transistor N6 is connected to an external power supply, the source of the sixth NMOS transistor N6 is connected to the programmable current source, and the source of the sixth NMOS transistor N6 is also connected to the second input terminal of the oscillation circuit; the gate of the seventh NMOS transistor N7 is connected to the second output terminal of the oscillation circuit, the drain of the seventh NMOS transistor N7 is connected to an external power supply, the source of the seventh NMOS transistor N7 is connected to the programmable current source, and the source of the seventh NMOS transistor N7 is also connected to the first input terminal of the oscillation circuit.

[0042] It should be noted that, as Figure 4 As shown, the programmable current source is the sum of two or more current biases, and each current bias has a current control switch connected in series with it; the current values ​​of each parallel current bias in this programmable current source increase sequentially, and the opening and closing of the switch is adjusted by the configuration register U3 to regulate the magnitude of the output current.

[0043] In this embodiment, the sampling circuit includes an eighth NMOS transistor N8, a ninth NMOS transistor N9, and a tenth NMOS transistor N10. The drain of the eighth NMOS transistor N8 is connected to the feedback control circuit, and the gate of the eighth NMOS transistor N8 is connected to the first output terminal of the output circuit. The drain of the ninth NMOS transistor N9 is connected to the feedback control circuit, and the gate of the ninth NMOS transistor N9 is connected to the second output terminal of the output circuit. The drain of the tenth NMOS transistor N10 is connected to the source of the eighth NMOS transistor N8 and the source of the ninth NMOS transistor N9, respectively. The gate of the tenth NMOS transistor N10 is connected to the current source, and the source of the tenth NMOS transistor N10 is grounded.

[0044] In this embodiment, the output circuit includes: a first PMOS transistor P1, a second PMOS transistor P2, an eleventh NMOS transistor N11, and a twelfth NMOS transistor N12; the gate of the first PMOS transistor P1 is connected to the feedback control circuit, the source of the first PMOS transistor P1 is connected to an external power supply, and the drain of the first PMOS transistor P1 is connected to the drain of the eleventh NMOS transistor N11 and the gate of the twelfth NMOS transistor N12; the gate of the second PMOS transistor P2 is connected to the feedback control circuit, the source of the second PMOS transistor P2 is connected to an external power supply, and the drain of the second PMOS transistor P2 is connected to the drain of the twelfth NMOS transistor N12 and the gate of the eleventh NMOS transistor N11; the sources of the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12 are grounded; the drain of the first PMOS transistor P1 is the first output terminal of the output circuit, and the drain of the second PMOS transistor P2 is the second output terminal of the output circuit.

[0045] like Figure 5 As shown, the startup circuit includes: a first register U1, a thirteenth NMOS transistor N13, and a fourteenth NMOS transistor N14; the input terminal of the first register U1 is connected to an external MCU and is used to output a pulse signal according to the control signal of the external MCU; the gates of the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14 are respectively connected to the output terminal of the first register U1, the drain of the thirteenth NMOS transistor N13 is connected to the first output terminal of the output circuit, the drain of the fourteenth NMOS transistor N14 is connected to the second output terminal of the output circuit, and the sources of the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14 are grounded.

[0046] It should be noted that, due to the different dimensions of the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14, when a high-level signal is output through the first register U1, the amount of charge stored on the gate capacitors of the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor is different; when the output level signal of the first register U1 changes from high to low, the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor release different amounts of charge to their respective drain terminals H and J, thereby creating a voltage difference between the first output terminal H and the second output terminal J of the output circuit.

[0047] In this embodiment, the clock generator further includes a shaping circuit 170, which is connected to the output terminal of the output circuit and is used to shape the clock signal output by the output circuit.

[0048] like Figure 6 As shown, the shaping circuit 170 includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a fifteenth NMOS transistor M15, a sixteenth NMOS transistor M16, and a seventeenth NMOS transistor M17; the gates of the third PMOS transistor P3, the fourth PMOS transistor P4, the fifteenth NMOS transistor M15, and the sixteenth NMOS transistor M16 are respectively connected to the output terminal of the output circuit, and the source of the third PMOS transistor P3 is connected to the external... With the power supply connected, the drain of the third PMOS transistor P3 and the source of the fourth PMOS transistor P4 are respectively connected to the drain of the fifth PMOS transistor P5. The drain of the fourth PMOS transistor P4, the drain of the fifteenth NMOS transistor M15, and the gate of the fifth PMOS transistor P5 are respectively connected to the gate of the seventeenth NMOS transistor M17. The source of the fifteenth NMOS transistor M15 and the drain of the sixteenth NMOS transistor M16 are respectively connected to the drain of the seventeenth NMOS transistor M17.

[0049] like Figure 2 As shown, the current source 120 in this embodiment includes a constant current source 121, PMOS transistors P6, PMOS transistors P7, PMOS transistors P8 and PMOS transistors P9, which are used to convert the reference voltage output by the reference voltage generation circuit and the output voltage VDD of the external power supply into constant currents I0, I1, I2 and I3.

[0050] It should be noted that the clock generator based on CMOS technology provided in this embodiment operates on the principle of charging and discharging a capacitor using a constant DC source to obtain a clock output at a fixed frequency. The detailed working process is as follows:

[0051] like Figure 2As shown, assuming that N1 and N2 are both off during the initial power-up phase, N4 and N5 begin to draw current, and capacitors C1 and C2 discharge through N4 and N5 respectively until the voltage at points A and B is 0. Since N1 and N2 are both off, the gate potentials of N7 and N6 are VDD. After the system powers on, the startup circuit creates a voltage difference between nodes H and J, resulting in different gate potentials for NMOS devices N8 and N9. Since the source potentials of N8 and N9 are the same, their VGS voltages are different, leading to different currents flowing through them. This means that the source potentials of N7 and N8 are different. For either N7 or N6, when VGS > Vth, that device turns on. If VGS6-Vth6 is greater than 0, then device N6 will turn on first. When device N6 turns on, the potential at point F rises. When the potential at point F (the gate potential of device N2) rises to a level greater than the threshold voltage Vth2 of device N2, device N2 turns on. At this time, the current of N2 increases, and the voltage at point D will change from VDD in the initial power-on state to VDD-IR2. That is, the voltage at point D decreases, which means the gate voltage of N7 decreases. When the gate voltage of N7 decreases to the threshold of P1, P1 turns on, the potential at point H rises, device N8 turns on, the current flowing through N8 increases, and the voltage at point E is pulled down to 0 through device N8, and N1 is completely turned off. At this time, N1 is off, N2 is on, C1 is discharging, and C2 is charging.

[0052] When N2 is on and N1 is off, C2 is charging. As C2 completes charging, the potential at point B rises (the source voltage of N2 increases), the VG-VS of N2 gradually decreases, and the current flowing through N2 decreases. At this time, the potential D at the drain of N2 gradually increases, causing P1 to turn off, the potential at point H to decrease, and N8 to turn off. When N8 turns off, due to the rise in the voltage at point D, N7 turns on, and the potential at point E rises (the gate potential of N1 rises). Since capacitor C1 discharged through device N4 during the previous off state, the potential at point A gradually decreases, while the gate voltage (E) of N1 gradually increases, causing N1 to gradually turn on. When N1 turns on, the voltage at point C decreases, P2 turns on, the potential at point J rises to VDD, N9 turns on, the potential at point F decreases, and N2 turns off. At this time, it enters the state of N1 being on and N2 being off, that is, the state of C1 charging and C2 discharging.

[0053] At this point, N1 is on and N2 is off. Then, because N2 is off, N5 discharges through capacitor C2, causing the voltage at the source of N2 to decrease until N2 is on and N1 is off. The alternating on and off of N1 and N2 achieves the alternating charging and discharging of capacitors C1 and C2, and the circuit enters its normal oscillation mode.

[0054] In this embodiment, the derivation process of the clock generator's output frequency is as follows:

[0055] The maximum rechargeable voltage of the capacitor:

[0056] V max =VDD-V GS6 -V GS2

[0057] Minimum voltage for capacitor discharge:

[0058] V min =VDD-I5R2-V GS7 -V GS1

[0059] Because: VGS2 = VGS1

[0060] Subtracting the results above, we can obtain:

[0061] The charge / discharge voltage difference between the drain terminals of N4 and N5 is:

[0062] ΔV=V max -V min =V GS7 -V GS6 +I5R2

[0063] And because:

[0064]

[0065] Since devices N7 and N6 have the same W / L value, the above formula can be written as:

[0066]

[0067] During the N1 off phase, the charge on the capacitor discharges using a constant current source N4. Let the discharge current be: I N4 ;

[0068] The formula for calculating the frequency is as follows:

[0069]

[0070] The formula for calculating frequency can be further described as follows:

[0071] The bias currents involved in this scheme all originate from the current source module. The currents in each branch are different, and their ratios to the source currents vary. Assuming the source current is I0, I... N4 = a*I0, I6=I7=m*I0, I8=n*I0, I5=k*I0; the capacitors in this scheme are PMOS capacitors with a capacitance of (Cox*Wc*Lc); therefore, the above formula can be further described as:

[0072]

[0073] In this example, the constant current source 121 includes amplifier A1, MOSFET M0, and resistor R0, with the specific connections as follows: Figure 7 As shown, I0 is the bandgap reference voltage (independent of power supply and temperature) V. BG It is generated by a resistor R0. Substituting into the above equation, we get:

[0074]

[0075] In the above equation, the first term in the denominator is much smaller than the second term. Therefore, ignoring the first term, the equation can be rewritten as:

[0076]

[0077] Where VGS1, VGS2, VGS7, and VGS6 represent the differences between the gate voltage (VG) and source voltage (VS) of devices N1, N2, N7, and N6, respectively; I represents the current flowing through the source and drain terminals of the devices; μ represents the electron migration rate; Cox represents the gate oxide capacitance per unit area; and W / L represents the width-to-length ratio of the MOS device. In this embodiment, the currents I1 and I2 are equal, the currents I4 and I5 are equal, the currents I6 and I7 are equal, Wc and Lc are the width and length of the PMOS capacitor C1 (C2), respectively, and a, m, n, and k are coefficients related to the multiplier.

[0078] As can be seen from the rewritten frequency calculation formula above, the output frequency of the clock generator in this application is only related to the resistor R2, the gate oxide capacitance Cox per unit area, the width Wc of the PMOS capacitor, and the length Lc of the PMOS capacitor, and is independent of other factors such as power supply and temperature. Therefore, the clock generator of the CMOS process in this application is not affected by factors such as power supply and temperature, which makes the output clock signal have high stability.

[0079] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0080] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A clock generator based on CMOS technology, characterized in that, The clock generator includes: Start-up circuit, current source, oscillation circuit, feedback control circuit, sampling circuit, and output circuit; The startup circuit is connected to an external MCU and also to the output terminal of the output circuit. It is used to create a voltage difference between the first output terminal and the second output terminal of the output circuit according to the enable signal output by the external MCU. The sampling circuit is connected to the output circuit and is used to sample the voltages at the first and second output terminals of the output circuit to obtain the sampled voltage. The feedback control circuit is connected to the sampling circuit, the oscillation circuit and the output circuit respectively. It is used to control the oscillation circuit to output an oscillation signal according to the sampling voltage, and also to send the oscillation signal to the output circuit so that the output circuit outputs a clock signal according to the oscillation signal. The current source is connected to the oscillation circuit and the sampling circuit respectively, and is used to provide a constant current; The oscillation circuit includes: First PMOS capacitor, second PMOS capacitor, first NMOS transistor, second NMOS transistor, third NMOS transistor, fourth NMOS transistor and fifth NMOS transistor; The source of the first NMOS transistor is connected to the first output terminal of the current source through the first PMOS capacitor, and the drain of the first NMOS transistor is connected to an external power supply; the source of the second NMOS transistor is connected to the second output terminal of the current source through the second PMOS capacitor, and the drain of the second NMOS transistor is connected to an external power supply. The drain, gate, gate, and fifth gate of the third NMOS transistor are respectively connected to the third output terminal of the current source, and the source of the third NMOS transistor, the source of the fourth NMOS transistor, and the source of the fifth NMOS transistor are grounded. The gates of the first NMOS transistor and the second NMOS transistor serve as the first and second input terminals of the oscillation circuit, respectively, and the drains of the first and second NMOS transistors serve as the first and second output terminals of the oscillation circuit, respectively.

2. A clock generator based on CMOS technology as described in claim 1, characterized in that, The oscillation circuit also includes: First programmable resistor and second programmable resistor; The first end of the first programmable resistor is connected to the external power supply, the second end of the first programmable resistor is connected to the drain of the first NMOS transistor, and the control terminal of the first programmable resistor is connected to an external MCU. The first end of the second programmable resistor is connected to the external power supply, the second end of the second programmable resistor is connected to the drain of the second NMOS transistor, and the control terminal of the second programmable resistor is connected to an external MCU.

3. A clock generator based on CMOS technology as described in claim 2, characterized in that, Each programmable resistor includes: The system consists of a first register, n control switches, and n fixed resistors. The input terminal of the first register is connected to an external MCU, and the n output terminals of the first register are respectively connected to the control terminals of n control switches, which are used to control the opening and closing of each control switch according to the control signal output by the external MCU; wherein, the n control switches are connected in series, and each control switch is connected in parallel with a fixed resistor.

4. A clock generator based on CMOS technology as described in claim 1, characterized in that, The feedback control circuit includes: Programmable current source, sixth NMOS transistor and seventh NMOS transistor; The gate of the sixth NMOS transistor is connected to the first output terminal of the oscillation circuit, the drain of the sixth NMOS transistor is connected to an external power supply, the source of the sixth NMOS transistor is connected to the programmable current source, and the source of the sixth NMOS transistor is also connected to the second input terminal of the oscillation circuit. The gate of the seventh NMOS transistor is connected to the second output terminal of the oscillation circuit, the drain of the seventh NMOS transistor is connected to an external power supply, the source of the seventh NMOS transistor is connected to the programmable current source, and the source of the seventh NMOS transistor is also connected to the first input terminal of the oscillation circuit.

5. A clock generator based on CMOS technology as described in claim 1, characterized in that, The sampling circuit includes: The eighth, ninth, and tenth NMOS transistors; The drain of the eighth NMOS transistor is connected to the feedback control circuit, and the gate of the eighth NMOS transistor is connected to the first output terminal of the output circuit. The drain of the ninth NMOS transistor is connected to the feedback control circuit, and the gate of the ninth NMOS transistor is connected to the second output terminal of the output circuit. The drain of the tenth NMOS transistor is connected to the source of the eighth NMOS transistor and the source of the ninth NMOS transistor, respectively. The gate of the tenth NMOS transistor is connected to the current source, and the source of the tenth NMOS transistor is grounded.

6. A clock generator based on CMOS technology as described in claim 1, characterized in that, The output circuit includes: First PMOS transistor, second PMOS transistor, eleventh NMOS transistor, and twelfth NMOS transistor; The gate of the first PMOS transistor is connected to the feedback control circuit, the source of the first PMOS transistor is connected to an external power supply, and the drain of the first PMOS transistor is connected to the drain of the eleventh NMOS transistor and the gate of the twelfth NMOS transistor. The gate of the second PMOS transistor is connected to the feedback control circuit, the source of the second PMOS transistor is connected to an external power supply, and the drain of the second PMOS transistor is connected to the drain of the twelfth NMOS transistor and the gate of the eleventh NMOS transistor. The source of the eleventh NMOS transistor and the source of the twelfth NMOS transistor are grounded; the drain of the first PMOS transistor is the first output terminal of the output circuit, and the drain of the second PMOS transistor is the second output terminal of the output circuit.

7. A clock generator based on CMOS technology as described in claim 1, characterized in that, The startup circuit includes: First register, thirteenth NMOS transistor, and fourteenth NMOS transistor; The input terminal of the first register is connected to an external MCU and is used to output pulse signals according to the control signals of the external MCU; The gates of the thirteenth NMOS transistor and the fourteenth NMOS transistor are respectively connected to the output terminal of the first register. The drain of the thirteenth NMOS transistor is connected to the first output terminal of the output circuit, and the drain of the fourteenth NMOS transistor is connected to the second output terminal of the output circuit. The sources of the thirteenth NMOS transistor and the fourteenth NMOS transistor are grounded.

8. A clock generator based on CMOS technology as described in claim 1, characterized in that, The clock generator also includes: A shaping circuit, connected to the output terminal of the output circuit, is used to shape the clock signal output by the output circuit.

9. A clock generator based on CMOS technology as described in claim 8, characterized in that, The shaping circuit includes: The third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, and the seventeenth NMOS transistor; The gates of the third PMOS transistor, the fourth PMOS transistor, the fifteenth NMOS transistor, and the sixteenth NMOS transistor are respectively connected to the output terminal of the output circuit. The source of the third PMOS transistor is connected to an external power supply. The drains of the third PMOS transistor and the source of the fourth PMOS transistor are respectively connected to the drain of the fifth PMOS transistor. The drains of the fourth PMOS transistor, the drains of the fifteenth NMOS transistor, and the gate of the fifth PMOS transistor are respectively connected to the gate of the seventeenth NMOS transistor. The source of the fifteenth NMOS transistor and the drain of the sixteenth NMOS transistor are respectively connected to the drain of the seventeenth NMOS transistor.

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