Starting transmission of frames with a predetermined start polarity and related systems, methods and apparatus

Abstract

Systems, methods, and apparatuses for communicating a source of 10SPE wake-up are disclosed. Such communications can be performed over a low pin count hardware interface having a split arrangement of 10SPE physical layer (PHY) modules. A controller side of a 10SPE PHY can perform a local or remote 10SPE wake-up in advance in response to a communicated source of wake-up. A digital interface for operatively coupling a PHY controller to a PHY transceiver via a low pin count connection is also disclosed, where the digital interface includes circuitry for checking integrity of circuitry of the digital interface. A PHY transceiver of a 10SPE PHY is also disclosed, where the transceiver includes circuitry for controlling a start polarity of a frame.

Description

Technical Field

[0001] This disclosure generally relates to single-pair Ethernet networks. Some examples relate to a limited number of connections for a 10SPE physical layer module with a separate arrangement. Some examples relate to initiating the transmission of a frame with a predetermined start polarity and controlling that transmission at the physical layer transceiver of the Ethernet PHY. Background Technology

[0002] Interconnection is widely used to facilitate communication between devices, subsystems, and systems within a network. Generally, electrical signals are transmitted over a physical medium (e.g., a bus, coaxial cable, or twisted pair, often simply referred to as a "line" or "bus") by a device coupled to that physical medium.

[0003] According to the Open Systems Interconnection (OSI) model, Ethernet-based computer networking technology uses baseband transmission (i.e., electrical signals are discrete electrical pulses) to transmit data packets and ultimately the messages relayed between network devices. According to the OSI model, dedicated circuitry or controllers, called Physical Layer (PHY) devices, are used to bridge the gap between the analog domain of the line and the digital domain of the Data Link Layer (also referred to herein as the "Link Layer"), which operates according to packet signaling. While the Data Link Layer may include one or more sublayers, in Ethernet-based computer networking, it typically includes at least a Media Access Control (MAC) layer that provides an abstraction for control over the Physical Layer. As a non-limiting example, when transmitting data to another device on the network, the MAC controller can prepare frames for the physical medium, add error correction elements, and implement collision avoidance. Furthermore, when receiving data from another device, the MAC controller can ensure the integrity of the received data and prepare frames for higher layers.

[0004] Various network topologies exist that implement physical and data link layers (and may include, but are not limited to, other layers). Since the early 1990s, both the Peripheral Component Interconnect (PCI) standard and the Parallel Advanced Technology Annex (Parallel ATA) standard have been able to implement multi-station bus topologies. Since the early 2000s, the trend has been to use point-to-point bus topologies, such as the PCI Express (PCIe) standard and the Serial ATA (SATA) standard, to implement point-to-point topologies.

[0005] A typical point-to-point bus topology may implement lines between each device (e.g., unrestricted, dedicated point-to-point) or lines between a device and a switch (e.g., unrestricted, switched point-to-point). In a multi-station bus topology, the physical transmission medium is a shared bus, and each network device is coupled to the shared bus, for example, via circuitry selected based on the type of physical medium (e.g., not limited to coaxial cable or twisted pair).

[0006] Point-to-point bus topologies (such as dedicated point-to-point or switched point-to-point topologies) require more wiring and more expensive materials than multi-station topologies, partly due to the greater number of links between devices. In some applications (such as automotive), there may be physical constraints that make it difficult to directly connect devices, and therefore topologies that do not require direct connections or as many direct connections in a network or subnetwork (e.g., not limited to multi-station topologies) may be less susceptible to such constraints or obstacles.

[0007] Devices on a baseband network (e.g., but not limited to multi-station networks) share the same physical transmission medium and typically use the entire bandwidth of that medium for transmission (in other words, the digital signal used for baseband transmission occupies the entire bandwidth of the medium). Therefore, only one device on a baseband network can transmit at a given time. Consequently, media access control methods are sometimes used to handle contention for such shared transmission media. Attached Figure Description

[0008] To facilitate identification of any discussion of a particular element or action, the most important one or more numbers in the reference markings refer to the figure number where the element was first introduced.

[0009] Figure 1 It is a block diagram depicting a portion of a physical layer transceiver, including a test pulse control circuit, according to one or more examples.

[0010] Figure 2 It is a flowchart depicting a portion of the process for performing cable diagnostics at a PHY transceiver, based on one or more examples.

[0011] Figure 3 The description depicts a flowchart of the process used to control the start polarity of the start frame transmission of the PHY transceiver.

[0012] Figure 4 This explains one aspect of the subject matter based on an example.

[0013] Figure 5 It is a block diagram depicting some or all of the features or elements disclosed for one or more examples. Detailed Implementation

[0014] In the following detailed description, reference is made to the accompanying drawings, which form a part of this disclosure, and specific examples of how this disclosure may be practiced are shown by way of example in the drawings. These examples have been described in sufficient detail to enable those skilled in the art to practice this disclosure. However, other examples may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of this disclosure.

[0015] The illustrations presented herein are not intended to be actual views of any particular method, system, apparatus, or structure, but are merely idealized representations used to describe examples of this disclosure. The figures presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the figures may be numbered the same or similarly; however, similarity in numbering does not imply that the structure or component is necessarily identical in size, composition, configuration, or any other property.

[0016] The following description may include examples to help enable those skilled in the art to practice the disclosed examples. The use of the terms “exemplary,” “for example,” and “e.g.” means that the related description is illustrative, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the examples or the scope of this disclosure to the specified parts, steps, features, functions, etc.

[0017] It will be readily understood that the components of the examples described herein and illustrated in the accompanying drawings can be arranged and designed in a wide variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of this disclosure, but rather represents only various examples. While various aspects of the examples are presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0018] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Components, circuits, and functions are illustrated in block diagram form to avoid obscuring this disclosure with unnecessary detail. Rather, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Additionally, block definitions and logical partitioning between blocks are examples of specific embodiments. It will be apparent to those skilled in the art that this disclosure can be practiced with many other partitioning solutions. In most cases, details such as timing considerations have been omitted, where such details are not necessary to obtain a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0019] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and skills. For clarity of presentation and description, some figures may illustrate a signal as a single signal. Those skilled in the art will understand that a signal may represent a signal bus, wherein the bus may have multiple bit widths, and this disclosure may be implemented on any number of data signals, including a single data signal.

[0020] The various illustrative logic blocks, modules, and circuits described herein can be implemented or performed using general-purpose processors, special-purpose processors, digital signal processors (DSPs), integrated circuits (ICs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a "host processor" or simply a "host") may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. When a general-purpose computer including a processor is configured to execute computational instructions (e.g., software code) related to the examples of this disclosure, the general-purpose computer is considered a special-purpose computer.

[0021] Examples can be described based on a process depicted as a flowchart, schematic diagram, structural diagram, or block diagram. While a flowchart may describe actions as a continuous process, many of these actions may be performed in another sequence, in parallel, or substantially simultaneously. Furthermore, the order of actions can be rearranged. A process may correspond to (but is not limited to) a method, thread, function, procedure, subroutine, or subroutine. Moreover, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, the function may be stored or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another.

[0022] Any reference to elements in this document using names such as "first," "second," etc., does not limit the number or order of those elements unless such limitation is explicitly stated. Rather, these names may be used herein as a convenient way to distinguish between two or more elements or instances of elements. Thus, mentioning a first element and a second element does not imply that only two elements may be used there, or that the first element must somehow precede the second element. Furthermore, unless otherwise specified, a group of elements may include one or more elements.

[0023] As used herein, any relational terms (such as "above", "below", "on", "under", "upper", "lower", etc.) are used for clarity and convenience in understanding this disclosure and the accompanying drawings, and such relational terms do not imply or depend on any particular preference, orientation or order unless the context clearly indicates otherwise.

[0024] As used herein, the term "substantially" with respect to a given parameter, property, or condition means, to the extent that a person skilled in the art would understand, that a given parameter, property, or condition experiences minor variations, such as within acceptable manufacturing tolerances. For example, a particular parameter, property, or condition may be substantially satisfied at least 90%, at least 95%, or even at least 99%, depending on whether it is substantially satisfied.

[0025] In this description, the term “coupled” and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as “coupled” to another element, then the element may be in direct physical or electrical contact, or there may be an intermediary element or layer. In contrast, when an element is described as “directly coupled” to another element, then there is no intermediary element or layer. The terms “on” and “connected” are used interchangeably with the term “coupled” in this description and have the same meaning unless otherwise expressly indicated or the context will otherwise indicate to a person skilled in the art.

[0026] As used herein, the terms “assert,” “deassert,” and their derivatives used with respect to the pin and component are referred to respectively to assert or deassert the signal associated with the pin (e.g., (not limited to) a signal specifically assigned to or to the pin).

[0027] Vehicles, such as cars, trucks, buses, ships, and / or aircraft, can all include vehicle communication networks. The complexity of a vehicle communication network can vary depending on the numerous electronic devices within the network. For example, an advanced vehicle communication network may include various control modules for (as a non-limiting example) engine control, transmission control, safety control (e.g., anti-lock braking), and emissions control. To support these modules, the automotive industry relies on a variety of communication protocols.

[0028] 10SPE (i.e., 10Mbps single-pair Ethernet) is currently used in IEEE 802.3cg. TM Network technologies under the specified specifications. 10SPE can be used to provide (but is not limited to) collision-free deterministic transmission over, for example, multi-station networks or shared transmission media.

[0029] Bits of a frame are encoded using some bit-level coding process, where the data of such encoded frames is insensitive to polarity. As a non-limiting example, in a Differential Manchester Coded (DME) frame used in a 10SPE transmission scheme, the bits of the frame are encoded by state transitions in the signal, and more specifically, by the presence of rising or falling edges in the signal. Generally, whether a given state transition is a rising or falling edge does not affect the encoding of the DME frame; only the presence of such a transition matters. The inventors of this disclosure understand that, in some cases, selective control of the frame polarity by the PHY transceiver can be desirable.

[0030] As used herein, the term “polarity” as used in the reference frame refers to the rising or falling edge of a bit transition in the frame, and the term “start polarity” as used in the reference frame refers to the rising or falling edge of the first transition of the first bit in the frame; wherein the rising edge is defined as the first polarity and the falling edge is defined as the second polarity.

[0031] To give a non-limiting example, the start polarity of a frame (Ethernet or not) can sometimes affect electromagnetic emissions (EME) in a given electronic system, and therefore actively sending frames with specific or randomly generated polarity patterns can be an effective strategy for minimizing or controlling EME. Ethernet frame data (1s and 0s) is typically encoded using Manchester coding (such as, but not limited to, DME), and the start polarity of the Ethernet frame does not affect the Manchester-coded data.

[0032] To give another non-limiting example, PHYs sometimes support the detection and / or diagnosis of cable faults on networks including 10SPE networks via time-domain reflectometry (TDR), which can benefit from the different start polarities of pulses generated for cable fault diagnosis. Many applications, such as in vehicle communication networks utilizing 10SPE, require cable fault diagnosis. Various types of cable faults can be detected and diagnosed, including cable "open circuit" and cable "short circuit" faults, as well as cable mismatches based on TDR. The absence of a cable fault can also be detected via TDR.

[0033] For cable fault diagnosis, a pulse is transmitted from the PHY, and if a reflection is detected at the PHY, a cable fault can be determined. Furthermore, the type of cable fault can be determined based on the detected reflection (e.g., phase and / or orientation (positive or negative)). For example, if the detected reflection includes a shape similar to the transmitted pulse, an "open circuit" fault can be determined. If the detected reflection includes a shape similar to but opposite to the transmitted pulse, a "short circuit" fault can be determined. Furthermore, if the detected reflection includes an amplitude different from that of the transmitted pulse, a "mismatch" fault can be determined. More specifically, if the detected reflection includes a shape similar to the transmitted pulse, and the reflection and the transmitted pulse have different amplitudes, an "open circuit mismatch" fault can be determined. Furthermore, if the detected reflection includes a shape similar to but opposite to the transmitted pulse, and the reflection and the transmitted pulse have different amplitudes, a "short circuit mismatch" fault can be determined.

[0034] To identify the type of cable fault, the PHY generates a first short-circuit frame (i.e., a pulse) with a first starting polarity and then generates a second short-circuit frame with a second, opposite starting polarity. Information from the reflected frames can be used to identify the type of cable fault. However, in situations such as those caused by… Figure 1 In the depicted split arrangement, the control logic unit for cable fault diagnosis is typically located in the PHY controller (e.g., PHY controller 104), and although this control logic unit can instruct the PHY's transmission circuitry to generate pulses and then observe the reflections, conventional PHY controllers known to the inventors cannot control or instruct the initial polarity of the pulses generated by the transmission circuitry of the PHY transceiver in such a split arrangement.

[0035] One or more examples generally relate to controlling the start polarity of frames generated by a PHY transceiver. As a non-limiting example, the PHY transceiver may be a PHY transceiver with a discrete arrangement or a different architecture. The PHY transceiver may be a transceiver provided at the 10SPE physical layer or another Ethernet physical layer. The signal conditioner of the PHY transceiver may include a polarity controller to selectively control the start polarity to be exhibited by the frame to be transmitted. A signal generator provided at the polarity controller may control the generation of a reference signal exhibiting a first state or a second state in response to a polarity setting register. This reference signal may be provided to a transmitter, which controls the start polarity of the next transmission of the frame in response to the state of the reference signal. A configuration logic unit (config logic unit) of the PHY transceiver may set the polarity setting of the polarity setting register. In some examples, the signal generator of the polarity controller may include logic for generating a reference signal according to polarity rules, which is enabled in response to the polarity setting register.

[0036] Figure 1 This is a block diagram depicting a signal conditioner 130 of a PHY transceiver section 100 according to one or more examples, which transmits frames exhibiting a predetermined start polarity. The signal conditioner 130 includes a transmitter 120 and a polarity controller 126. The transmitter 120 is configured to generally respond to a frame command 124 (e.g., received from a PHY controller) and a reference signal 114 generated by the polarity controller 126 to initiate frame transmission over a shared transmission medium. The transmitter 120 includes a driver controller 110 that generates control signals for a driver 104 in response to the state of the reference signal 114. The driver 104 (e.g., a voltage signal driver) generates differential signals at pins TRXP 106 and TRXN 108 in response to the control signals provided by the driver controller 110 and the frame command 124, and thus exhibits a state transition. As a non-limiting example, a state transition can be generated at pins TRXP 106 and TRXN 108 and, consequently, at a shared transmission medium (e.g., transmission medium 114) coupled to the differential pins by: applying a first voltage signal of 0V to one of TRXP 106 and TRXN 108 and applying a second, higher voltage signal to the other of TRXP 106 and TRXN 108; and then switching the respective pins to which the first and second voltage signals are applied.

[0037] The initial polarity exhibited by frames generated by such signals can be controlled in response to the state of reference signal 114. Polarity controller 126 generally generates reference signal 114 exhibiting a predetermined state, such that voltage signals driven by driver 104 at differential pins TRXP 106 and TRXN 108 in response to the reference signal exhibit a predetermined initial polarity.

[0038] A reference signal 114 is generated by a signal generator 102 of the polarity controller 126. The signal generator 102 generally generates the reference signal 114 in at least part of response to internal signal generation logic (such as a logic module in logic module 134 that sets the initial polarity by setting the state of the reference signal 114 in response to the value of the polarity setting register 112 (i.e., in response to polarity setting 116)) and the polarity setting 116 available at the polarity setting register 112 of the polarity controller 126. The polarity setting 116 is available at the polarity setting register 112, which has a value of a polarity setting indication 118 provided by the processor 132 (executing config firmware 122) in response to a configuration command 128 from a PHY controller (PHY controller not shown). Figure 1 and Figure 1 The expected operation is that when a configuration command 128 is received from the PHY controller at PHY transceiver section 100, the internal state machine transitions to the configuration state. Figure 1 The PHY transceiver section 100 waits for and executes configuration commands until it is reset by a command, at which point the internal state machine transitions to the normal state ("NORMAL").

[0039] In one or more examples, processor 132 (e.g., by executing config firmware 122) may enable rules for the start polarity of frames. Non-limiting examples of start polarity rules include: transmitting every frame with the same start polarity; alternating the start polarity of every nth frame (e.g., for cable fault detection or EME reduction, not limited to); and randomizing the start polarity of every frame (e.g., for EME reduction, not limited to).

[0040] By way of a non-limiting example of intended operation, in the case of PHY performing cable fault diagnosis, configuration command 128 includes instructions to alternate the start polarity of the generated frames, because during cable fault diagnosis, the state of the cable is revealed more by reflections of test pulses with different polarities than by the case where each pulse has the same start polarity. Frame instruction 124 may include instructions to send "short-circuit" frames (e.g., exhibiting a waveform typically resembling a pulse train). Processor 132 executing config firmware 122 programs polarity setting register 112 such that polarity setting 116 initializes a logic module in logic module 134 at polarity controller 126 to alternate the start polarity of every Nth frame. When driver controller 110 controls driver 104 to generate a set of short-circuit frames, driver controller 110 controls driver 104 to generate short-circuit frames exhibiting a first start polarity in response to the state of reference signal 114. Signal generator 102 may automatically change the start polarity of subsequent frames to a second start polarity by changing the state of reference signal 114. When driver controller 110 controls driver 104 to generate a second set of short-circuit frames, the driver controller generates short-circuit frames exhibiting a second initial polarity in response to a change in the state of reference signal 114. In the case of cable fault diagnosis, reflections (if any) are captured by an optional signal detector (not depicted) and sent to the ED pin of the digital interface coupled to the PHY controller via a valid signal indication.

[0041] By way of another non-limiting example of intended operation, the PHY may transmit Manchester-coded frames with random start polarities in an attempt to reduce the impact of electromagnetic emissions (EME) or other EME generated by the transmission. In this example, configuration command 128 includes instructions to cause config firmware 122 to program polarity setting register 112 to generate polarity setting 116, which initializes a logic module in logic module 134 at polarity controller 126 to randomize the start polarity of each frame. When the PHY transceiver transitions from configuration state back to normal state or transmission state and begins transmission, the start polarity of each frame is random (including, but not limited to, truly random or approximately random).

[0042] Figure 2 It is a flowchart depicting a process 200 for controlling the start polarity according to one or more examples, at which the PHY transceiver begins transmitting frames.

[0043] At operation 202, process 200 optionally enters the configuration state of the 10SPE PHY transceiver, and in operation 204, process 200 receives a first configuration command indicating a polarity setting corresponding to a predetermined start polarity in order to begin transmitting the next frame (e.g., (not limited to) a 10SPE frame). In this configuration state, the processor 132 of the 10SPE PHY transceiver (executing config firmware 122) can receive a configuration command 228 including the polarity setting and program the polarity setting register 212 accordingly.

[0044] At operation 206, process 200 configures the state of the reference signal in at least part of response to a predetermined start polarity being a first state or a second state. The first state corresponds to a first start polarity when a frame is started, and the second state corresponds to a second start polarity when a frame is started.

[0045] At operation 208, process 200 generates a reference signal that reflects the configured state. This reference signal may be reference signal 214, which is used by driver controller 210 to control driver 204 to generate differential signals for DME encoded frames.

[0046] At operation 210, process 200 configures the transmitter to initiate the next transmission of a frame (e.g., a 10SPE frame) exhibiting a predetermined start polarity, at least in part, by providing the transmitter (e.g., transmitter 220) with a reference signal that demonstrates the configured state.

[0047] At operation 212, process 200 begins transmitting the next frame exhibiting a predetermined start polarity (e.g., (not limited to) a 10SPE frame). Initiating transmission of the next frame exhibiting the predetermined start polarity may include: applying a first voltage signal to a first pin and applying a second voltage signal to a second pin; changing the voltage level exhibited by the first voltage signal from a first level to a second level; and substantially simultaneously changing the voltage level exhibited by the second voltage signal from the second level to the first level. The first level and the second level may correspond at least partially to a first start polarity responsive to a reference signal exhibiting a first state, or the first level and the second level may correspond at least partially to a second start polarity responsive to a reference signal exhibiting a second state.

[0048] Figure 3This is a flowchart depicting a process 300 for controlling the start polarity according to one or more examples, at which the PHY transceiver begins transmitting frames. As discussed above, in some examples, the logic module 134 at the polarity controller 126 may be initialized by the processor 132 executing config firmware 122 in response to a configuration command 128 indicating a rule for the start polarity at which one or more frames begin transmission. Non-limiting examples of the rule include a random start polarity, an alternating start polarity every nth frame, and the same start polarity for every frame.

[0049] At operation 302, process 300 enters the configuration mode of the 10SPE PHY transceiver (e.g., with the configuration mode provided by...). Figure 2 (As depicted in the state diagram). In configuration mode, the PHY controller can read (e.g., via the RX / ED pin) and / or program (e.g., via the TX pin) the polarity setting register 212 in response to configuration command 228 via processor 232 executing config firmware 222.

[0050] At operation 304, process 300 receives a configuration command that indicates a rule for the start polarity of frames that the transmitter will begin transmitting at its location. Non-limiting examples of the rule include: each frame begins with a first start polarity (e.g., positive or negative); the start polarity of every Nth frame is alternated, i.e., changed; or a first or second start polarity is randomly selected for a series of frames.

[0051] At operation 306, process 300 initializes a logic module in logic module 234 of signal generator 202 corresponding to the rule indicated by the configuration command. Logic module 234 may include combinational logic or other primitive logic circuitry for performing signal generation of reference signal 214 according to one or more rules, including the rule indicated by the configuration command. As a non-limiting example, logic module 234 may set the state of reference signal 214 such that when polarity setting 216 exhibits the associated state: each frame exhibits the same starting polarity, the starting polarity changes every nth frame, or the starting polarity of each frame is random. Processor 232 may initialize one of the logic modules in logic module 234 by setting the value at polarity setting register 212.

[0052] At operation 308, process 300 enters the normal state of the 10SPE PHY transceiver, in which the transceiver performs frame transmission.

[0053] At operation 310, process 300 begins to transmit one or more frames, each exhibiting an initial polarity according to the rule.

[0054] Example of a split PHY architecture

[0055] Those skilled in the art will understand that controlling the start polarity of a 10SPE frame at the physical layer transceiver may be desirable in other PHY architectures (e.g., other than a split arrangement), and may be desirable for frames in other transmission schemes (e.g., other than 10SPE) and bit-level encoding processes (e.g., other than DME) where data is not sensitive to polarity. Examples of start polarity control are particularly applicable to PHY transceivers with a split arrangement. The use of the disclosed polarity controller in other architectures different from those with a split arrangement is particularly contemplated within the scope of this disclosure, and does not extend beyond that scope.

[0056] PHYs can be designed and / or manufactured during high-voltage temperature processes; however, such processes may not be suitable (e.g., (not limited to) potentially damaging or testing may be too expensive) (as a non-limiting example): (not limited to) PHY designs with large and / or fast digital blocks, random access memory (RAM), and / or once-programmable (OTP) memory. A non-limiting example of a high-voltage temperature process is total current injection (BCI) susceptibility testing. Junction temperatures of approximately 175 degrees Celsius can be achieved during BCI and other high-voltage temperature processes known to the inventors of this disclosure.

[0057] One option for addressing some of these issues is to simplify the digital design of high-voltage, temperature processes to meet timing requirements or to fit them on the die. However, the design may not be simplified enough to meet such timing or die space requirements. Nevertheless, the size of the die or package can be increased, and the size of both the die and package is generally proportional to the total processing cost; the larger the die or package, the higher the processing cost.

[0058] The 10BASE-T1S transceiver interface standard (hereinafter referred to as the "TC14 standard"), currently developed under the specifications of the Open Consortium Technical Committee 14, defines a 3-pin hardware interface for discrete (controller-transceiver) 10SPE PHYs (discrete PHYs).

[0059] Figure 4This is a block diagram depicting a system 400 according to one or more examples, including a discrete PHY 402 coupled to a transmission medium 414 via a bus network interface 412. For now, the discrete PHY 402 includes a 3-pin hardware interface (hardware interface 408) defined by the TC14 standard. Generally, the first part of the discrete PHY (PHY controller 404) includes digital blocks that are susceptible to damage during high-voltage temperature processes and may be located on a first die that does not experience high-voltage temperature processes. The second part of the discrete PHY (PHY transceiver 406), including analog and digital blocks that are less sensitive to high-voltage temperature processes (either individually or as a whole), may be located on a second die that can experience high-voltage temperature processes. The PHY transceiver 406 includes a signal conditioner 420 for transmitting frames exhibiting a predetermined starting polarity, such as (but not limited to) a signal conditioner 130.

[0060] Hardware interface 408 includes three connections for signaling between PHY transceiver 406 and PHY controller 404: TX connection 416, RX connection 418, and ED connection 410. These three connections are typically implemented via corresponding pins attached to the respective integrated circuits of the discrete PHY, and thus each of the three connections is associated with a corresponding pin of PHY transceiver 406 and PHY controller 404. For now, the TC14 standard specifies the purpose of these connections, with some connections associated with specific states of the PHY transceiver. In normal operation, TX connection 416 is used to transmit transmission frames from PHY controller 404 to PHY transceiver 406, RX connection 418 is used to transmit received frames from PHY transceiver 406 to PHY controller 404, and ED connection 410 is used to identify valid signals from PHY transceiver 406 to PHY controller 404. Currently, the TC14 standard specifies that RX connection 418 is a comparator output indicating whether the transceiver's signal is above or below a threshold, ED connection 410 is a signal detector output indicating whether the transceiver is within or outside a threshold (i.e., indicating in-band and out-of-band signals), and TX is the transceiver's clockless state input.

[0061] Split PHYs enable more efficient power consumption. Some parts of a split PHY can enter a low-power or "sleep" mode to save power consumption through the split PHY, while other parts of the split PHY (e.g., (not limited to) transceivers or other hardware attachments) supplied by an uninterruptible power supply can perform at least some of the functions of the split PHY, while the split PHY as a whole is in a low-power mode.

[0062] In some cases, it may be necessary to locate specific functions or operations at portions of a discrete PHY within an uninterruptible power domain so that they can operate to some extent while in a low-power mode. As a non-limiting example, these could be functions associated with low-power or wake-up detection of a discrete PHY, node, network segment, or network, or functions associated with fault detection on the physical transmission medium (“cable fault detection”).

[0063] As mentioned above, in a typical discrete PHY, the first and second parts of the discrete PHY are coupled through three wired hardware interfaces. Each of these first and second parts of the discrete PHY may include interface logic components configured to associate individual pins with specific signals of the hardware interface and to handle communication and signal propagation over the connections of that hardware interface. Any suitable number of pins and connections can be used to implement the hardware interfaces of the discrete PHY. Furthermore, designers can consider communication over these hardware interfaces when choosing where to locate the digital blocks of features and functions used to implement the discrete PHY architecture.

[0064] Despite the challenges of the foregoing or other specific implementations, a discrete PHY architecture allows a discrete PHY (and systems and devices incorporating the discrete PHY, such as (but not limited to) network switches, bridges and endpoints) to be more digitally intensive and more power-efficient than some single PHY architectures, and thus enables designers to take these aspects into account.

[0065] Those skilled in the art will understand that the functional elements (e.g., functions, operations, actions, processes, and / or methods) of the examples disclosed herein can be implemented in any suitable hardware, software, firmware, or a combination thereof. Figure 5 Non-limiting examples of specific implementations of the functional elements disclosed herein are described. In some examples, some or all portions of the functional elements disclosed herein may be executed by hardware specifically configured to perform the functional elements.

[0066] Figure 5This is a block diagram of circuit 500, which in some examples may be used to implement the various functions, operations, actions, processes, and / or methods disclosed herein. Circuit 500 includes one or more processors (sometimes referred to herein as "processor 502") operatively coupled to one or more data storage devices (sometimes referred to herein as "storage device 504"). Storage device 504 includes machine-executable code 506 stored thereon, and processor 502 includes logic circuitry 508. Machine-executable code 506 includes information describing functional elements that may be implemented (e.g., executed by) logic circuitry 508. Logic circuitry 508 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 506. Circuit 500 should be considered as dedicated hardware configured to execute the functional elements disclosed herein when executing the functional elements described by machine-executable code 506. In some examples, processor 502 may be configured to execute the functional elements described by machine-executable code 506 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel process flows.

[0067] When implemented by the logic circuitry 508 of the processor 502, the machine-executable code 506 is configured to adapt the processor 502 to perform the operations of the examples disclosed herein. For example, the machine-executable code 506 may be configured to adapt the processor 502 to perform operations by... Figures 1 to 4 The depicted boxes and processes comprise at least a portion or all of them. As another example, machine-executable code 506 may be configured to adapt processor 502 to perform at least a portion or all of the operations discussed herein for one or more of the PHY transceivers or discrete PHY transceivers. As another example, machine-executable code 506 may be configured to adapt processor 502 to perform at least a portion or all of the operations discussed for polarity controller 126, polarity setting register 112, signal generator 102, raw logic unit 134, transmitter 120, driver controller 110, driver 104, and processor 132.

[0068] As a specific, non-limiting example, machine-executable code 506 may be configured to adapt processor 502 to perform some or all of the signal conditioning or polarity control discussed herein.

[0069] Processor 502 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. When a general-purpose computer including a processor is configured to perform functional elements corresponding to the machine-executable code 506 (e.g., software code, firmware code, hardware description) associated with the examples of this disclosure, the general-purpose computer is considered a special-purpose computer. It should be noted that the general-purpose processor (which may also be referred to herein as a host processor or simply host) may be a microprocessor, but alternatively, processor 502 may include any conventional processor, controller, microcontroller, or state machine. Processor 502 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0070] In some examples, storage device 504 includes volatile data storage devices (e.g., random access memory (RAM)) and non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), etc.). In some examples, processor 502 and storage device 504 may be implemented as a single device (e.g., (not limited to) a semiconductor device product, system-on-a-chip (SOC), or system base chip). In some examples, processor 502 and storage device 504 may be implemented as separate devices.

[0071] In some examples, the machine-executable code 506 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored in storage device 504, directly accessed by processor 502, and executed by processor 502 using at least logic circuitry 508. Again, as a non-limiting example, the computer-readable instructions may be stored on storage device 504, transferred to a memory device (not shown) for execution, and executed by processor 502 using at least logic circuitry 508. Therefore, in some examples, logic circuitry 508 includes logic circuitry 508 that can be electrically configured.

[0072] In some examples, machine-executable code 506 may describe the hardware (e.g., circuitry) to be implemented in logic circuitry 508 to perform functional elements. This hardware may be described at any of a range of abstraction levels, from low-level transistor layout to high-level description languages. At high-level abstraction, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), may be used. As a non-limiting example, Verilog may be used. TM SystemVerilog TM Or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL) TM ).

[0073] HDL descriptions can be converted into descriptions at any of a number of other levels of abstraction, as pre-defined. As a non-limiting example, a high-level description can be converted into a logic-level description, such as Register Transfer Language (RTL), Gate-level (GL) description, layout-level description, or mask-level description. As a non-limiting example, micro-operations performed by the hardware logic circuitry of logic circuitry 508 (e.g., gates, flip-flops, registers) can be described in RTL and then converted into a GL description by a synthesis tool, and the GL description can be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, discrete gate or transistor logic unit, discrete hardware unit, or a combination thereof of a programmable logic device. Therefore, in some examples, machine-executable code 506 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0074] In an example where machine-executable code 506 includes a hardware description (at any level of abstraction), a system (not shown, but including storage device 504) may be configured to implement the hardware description described by machine-executable code 506. As a non-limiting example, processor 502 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 508 may be electrically controlled to implement circuitry corresponding to the hardware description into logic circuitry 508. Again, as a non-limiting example, logic circuitry 508 may include hardwired logic components manufactured by a manufacturing system (not shown, but including storage device 504) according to the hardware description of machine-executable code 506.

[0075] Regardless of whether the machine-executable code 506 includes computer-readable instructions or a hardware description, the logic circuit 508 is adapted to execute the functional elements described by the machine-executable code 506 when the functional elements of the machine-executable code 506 are implemented. It should be noted that although the hardware description may not directly describe the functional elements, it indirectly describes the functional elements that the hardware elements described by the hardware description can execute.

[0076] The terms used in this disclosure, and especially in the appended claims (e.g., the main part of the appended claims), are generally defined as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “at least having”, the term “includes” should be interpreted as “including but not limited to”, etc.).

[0077] Furthermore, if a specific number of introduced claim statements are anticipated, such an intent will be explicitly stated in the claims, and without such a statement, such an intent does not exist. For example, as an aid to understanding, the appended claims may use the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be construed as implying that introducing a claim statement with the indefinite article "a" limits any particular claim containing such introduced claim statements to examples containing only one such statement, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" (e.g., "a" should be interpreted as meaning "at least one" or "one or more"); the same applies to the use of definite articles to introduce claim statements.

[0078] Furthermore, even if a specific number of the introduced claims are explicitly stated, those skilled in the art will recognize that such statements should be interpreted as meaning at least the number stated (e.g., the unmodified statement "two statements" means at least two statements, or two or more statements, in the absence of other modifying elements). Moreover, in cases where conventions such as "at least one of A, B, and C" or "one or more of A, B, and C" are used, such constructions are generally intended to include only A, only B, only C, both A and B, both A and C, both B and C, or all three A, B, and C, etc.

[0079] Furthermore, any separate word or phrase presenting two or more alternative terms in the specification, claims, or drawings should be understood to include the possibility of including one term, any one term, or both terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B". As used herein, "each" means some or all.

[0080] In this description, any characterization of something as "typical," "conventional," "known," etc., does not necessarily mean that the object is disclosed in the prior art or that the aspects in question are known in the prior art. Nor does such characterization necessarily mean that it is well-known, fully understood, or routinely used in the relevant art. Such characterization should be understood as meaning "known to the inventors of this disclosure."

[0081] Additional non-limiting embodiments of this disclosure include:

[0082] Example 1: A signal conditioner for a 10SPE physical layer transceiver, the signal conditioner comprising: a transmitter that transmits 10SPE frames; and a polarity controller that controls the transmitter to begin transmitting the next frame exhibiting a predetermined starting polarity.

[0083] Example 2: The signal conditioner according to Example 1, wherein the transmitter is configured to generate a differential Manchester coded signal corresponding to the next frame, wherein the initial state transition exhibited by the differential Manchester coded signal is at least partially responsive to the configuration state of the reference signal.

[0084] Example 3: A signal conditioner according to any one of Examples 1 and 2, wherein the polarity controller includes: a polarity setting register; and a signal generator configured to generate a reference signal representing the configuration state in response to the value of the polarity setting register.

[0085] Example 4: A signal conditioner according to any one of Examples 1 to 3, wherein the polarity setting register can be programmed by the 10SPE physical layer controller.

[0086] Example 5: A signal conditioner according to any one of Examples 1 to 4, wherein the transmitter is configured to perform the following operations: apply a first voltage signal to a first pin; apply a second voltage signal to a second pin; change the voltage level represented by the first voltage signal from a first level to a second level; and change the voltage level represented by the second voltage signal from the second level back to the first level.

[0087] Example 6: A signal conditioner according to any one of Examples 1 to 4, wherein: the corresponding values ​​of the first level and the second level correspond to a first start polarity that is at least partially responsive to the reference signal exhibiting a first state, and the corresponding values ​​of the first level and the second level correspond to a second start polarity that is at least partially responsive to the reference signal exhibiting a second state.

[0088] Example 7: A method for transmitting a 10SPE frame, the method comprising: receiving a polarity setting corresponding to a predetermined start polarity for initiating transmission of a 10SPE frame; configuring a transmitter to initiate transmission of a next 10SPE frame having the predetermined start polarity; and initiating transmission of a next 10SPE frame exhibiting the predetermined start polarity.

[0089] Example 8: According to the method of Example 7, configuring the transmitter to start transmitting the next 10SPE frame having the predetermined start polarity includes: configuring the transmitter to start transmitting the next 10SPE frame having the predetermined start polarity in response to the state of the reference signal.

[0090] Example 9: The method according to any one of Examples 7 and 8, the method includes configuring the state of the reference signal to a first state or a second state.

[0091] Example 10: The method according to any one of Examples 7 to 9, the method includes generating a reference signal that displays the configuration state.

[0092] Example 11: The method according to any one of Examples 7 to 10, the method includes providing the reference signal showing the configuration state to the transmitter.

[0093] Example 12: The method according to any one of Examples 7 to 11, wherein starting transmission of the next 10SPE frame exhibiting the predetermined start polarity includes: applying a first voltage signal to a first pin; applying a second voltage signal to a second pin; changing the voltage level exhibited by the first voltage signal from a first level to a second level; and changing the voltage level exhibited by the second voltage signal from the second level back to the first level.

[0094] Example 13: The method according to any one of Examples 7 to 12, wherein the first level and the second level correspond to a first start polarity that is at least partially responsive to a reference signal exhibiting a first state, or the first level and the second level correspond to a second start polarity that is at least partially responsive to a reference signal exhibiting a second state.

[0095] Example 14: A system comprising: a signal conditioner configured to generate Ethernet frames; and a processor and configuration firmware, wherein the configuration firmware, when executed by the processor, is configured to enable the processor to initialize a logic module of the signal conditioner, the logic module corresponding to a rule for the start polarity of the Ethernet frame at which transmission begins.

[0096] Example 15: The system according to Example 14, wherein the rule for the start polarity of the Ethernet frame at which transmission begins is a random start polarity.

[0097] Example 16: The system according to any of Examples 14 and 15, wherein the rule for the start polarity of the Ethernet frame at which transmission begins is an alternating start polarity for every Nth frame.

[0098] Example 17: The system according to any of Examples 14 to 16, wherein the rule for the start polarity of the Ethernet frame at which transmission begins is the same start polarity for each frame.

[0099] Example 18: A system according to any one of Examples 14 to 17, wherein the configuration firmware, when executed by the processor, is configured to enable the processor to receive a command instructing the rule and to initialize the logic module of the signal conditioner in at least part of response to the command.

[0100] While this disclosure has been described with reference to certain illustrated examples, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, many additions, deletions, and modifications may be made to the illustrated and described examples without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one example may be combined with features from another example while still being included within the scope of the invention as intended by the inventors.

Claims

1. A signal conditioner for a 10SPE physical layer transceiver, the signal conditioner comprising: A transmitter that transmits 10SPE frames encoded according to a polarity-insensitive coding scheme. and A polarity controller controls the transmitter to begin transmitting the next frame exhibiting a predetermined starting polarity by switching corresponding differential pins, wherein switching the corresponding differential pins includes: Apply a first voltage signal to the first pin; Apply a second voltage signal to the second pin; The voltage level represented by the first voltage signal is changed from a first level to a second level; and The voltage level represented by the second voltage signal is changed from the second level to the first level.

2. The signal conditioner of claim 1, wherein the transmitter generates a differential Manchester coded signal corresponding to the next frame, wherein the initial state transition exhibited by the differential Manchester coded signal is at least partially responsive to the configuration state of the reference signal.

3. The signal conditioner according to claim 2, wherein the polarity controller comprises: Polarity setting register; and A signal generator that generates a reference signal representing the configuration state in response to the value of the polarity setting register.

4. The signal conditioner of claim 3, wherein the polarity setting register is programmable by the 10SPE physical layer controller.

5. The signal conditioner according to claim 2, wherein: The corresponding values ​​of the first level and the second level correspond at least partially to the first starting polarity of the reference signal exhibiting the first state, and The corresponding values ​​of the first level and the second level correspond at least partially to the second starting polarity of the reference signal exhibiting the second state.

6. A method for transmitting 10SPE frames, the method comprising: Receive the polarity setting corresponding to the predetermined start polarity to begin transmitting a 10SPE frame; Configure the transmitter to transmit 10SPE frames encoded according to a polarity-insensitive coding scheme; as well as The transmission of the next 10SPE frame, exhibiting the predetermined start polarity, is initiated by switching the corresponding differential pin. Switching the corresponding differential pins includes: Apply a first voltage signal to the first pin; Apply a second voltage signal to the second pin; The voltage level represented by the first voltage signal is changed from a first level to a second level; and The voltage level represented by the second voltage signal is changed from the second level to the first level, and The next 10SPE frame is encoded according to a polarity-insensitive coding scheme.

7. The method of claim 6, wherein configuring the transmitter to begin transmission of the next 10SPE frame having the predetermined start polarity comprises: The transmitter is configured to begin transmission of the next 10SPE frame having the predetermined start polarity in response to the state of the reference signal.

8. The method of claim 7, wherein the method includes configuring the state of the reference signal to a first state or a second state.

9. The method of claim 7, wherein the method includes generating the reference signal that displays the configuration state.

10. The method of claim 9, the method comprising providing the reference signal representing the configuration state to the transmitter.

11. The method of claim 7, wherein the first level and the second level correspond to a first start polarity at least partially responsive to a reference signal exhibiting a first state, or the first level and the second level correspond to a second start polarity at least partially responsive to a reference signal exhibiting a second state.

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